Digitally Programmable Delay Units sens: ppu-13256F (8-Bit) TTL Interfaced . Aas eS a pope 4 2 ns whichever is greater. arr? I @ Inherent delay (Too): 15 ns on pin 6 oe | | 18nsonpind5 Features: : m Propagation delay: @ Input & output TTL buffered Address to output (Tsua) 12 ns typ. @ 8-BIT TTL programmable delay line Enable to output (Tsue) 12 ns typ. Specifications: a Delay variation: Monotonic in one direction. _ i Programmed delay tolerance: +5% or typical Test Conditions: a Input pulse-width: 2150% of Max. delay. w Input pulse spacing: 23 times of Max, delay. g Input pulse voltage: TTL logic. w Measurements taken @ @ Two (2) separate outputs; inverting & non-inverting mg Completely interfaced @ Compact & low profile w Power dissipation: Ta = 25C; Vcc = 5V. .95 w max. mw Supply voltage: 5 Vdc + 5%. uw Operating temperature: 0-70C. @ Temperature coefficient: 100 PPM/C. a DC parameters: See TTL-Fast Schottky Logic Table on Page 6. 2450 le - it Lape war Ww yey Y aes servel 2.900 + Vee a | WoL) DELAY H-{>l+ our 075 TYP ~o4 ate. al NETWORK | : = + oro St ____| pe ont 2 | | 400 Loe 4 TRUTH TABLE Address (Bit No.) 817 )]6)5)]4]3 | 2 41 | Enable | Delay Out (E,) O10 ];/0];0/0];0};0]0 0 T, Oo;o0;0/0];]0;/0],0)]1 0 Y, o7;o;oO;}oOof;oO;or 4] 0 0 Ty, olojolofojoj;1]1 0 Ts Oo1fro;,;o;/o/;/O0 71,1 4f 0 40 0 T, oj/ao;olojo}t1y1]4 0 T, oj/ojojo]/1}ofofo 0 Ts o,;OoOTo;o ;]1]41],1]71 0 Ts oj;o;/o;1t]}]oao];o7o]o 0 Te o;o;oO;1]1 71 )7]471 0 T,, O;O71];/0)/0 70]0] 0 0 T 5. ofoltryatr yr tardy 0 Tes o;i};O;oO];O};O}ToToO 0 T54 oy;i fiat r1tapargr)da 0 Toy 1}o}]o];/o]lofololo 0 Tog TEV tp_P ryt prt prtyt ) Toss {OOO OL Oo} oO ]9 1 1 Logic 0 0 Logic 1 T, Reference or inherent delay of unit. T 9 Don't care. 17 Tos, Multiplier of incremental delay. 56 Incremental Delay Total Programmed Part No. Per Step (ns) Delay (ns) PDU-13256F-.5 54+ 3 127.5 PDU-13256F-1 1245 255 PDU-13256F-2 2+ 5 510 PDU-13256F -3 3 10 785 PDU-13256F-4 4 +10 1,020 PDU-13256F-5 15 1275 PDU-13256F-6 6 15 1,530 PDU-13256F-7 7 15 1,71 PDU-13256F-8 8 +20 2,040 PDU-13256F-9 9 +20 2,295 PDU-13256F-10 10 +2.0 2,50 NOTE: 1. Forthe sake of simplicity all 256 programmabl:- steps are not shown in this truth table. 2. After Bit 6. the incremental delay tolerance is 5% of programmed delay. 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 @ (201) 773-2299 m FAX (201) 773-9672