MX25L25735E MX25L25735E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1586 REV. 1.0, JUL. 01, 2010 1 MX25L25735E Contents FEATURES................................................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 7 Table 1. Additional Features ............................................................................................................................... 7 PIN CONFIGURATION................................................................................................................................................. 8 PIN DESCRIPTION....................................................................................................................................................... 8 BLOCK DIAGRAM........................................................................................................................................................ 9 DATA PROTECTION................................................................................................................................................... 10 Table 2. Protected Area Sizes........................................................................................................................... 11 Table 3. 4K-bit Secured OTP Definition............................................................................................................. 11 Memory Organization................................................................................................................................................ 12 Table 4. Memory Organization......................................................................................................................... 12 DEVICE OPERATION................................................................................................................................................. 13 Figure 1. Serial Modes Supported (for Normal Serial mode)............................................................................ 13 HOLD FEATURES...................................................................................................................................................... 14 Figure 2. Hold Condition Operation . ................................................................................................................ 14 COMMAND DESCRIPTION........................................................................................................................................ 15 Table 5. Command Sets.................................................................................................................................... 15 (1) Write Enable (WREN).................................................................................................................................. 17 (2) Write Disable (WRDI)................................................................................................................................... 17 (3) Read Identification (RDID)........................................................................................................................... 17 (4) Read Status Register (RDSR)..................................................................................................................... 18 (5) Write Status Register (WRSR)..................................................................................................................... 19 Protection Modes.............................................................................................................................................. 19 (6) Read Data Bytes (READ)............................................................................................................................ 20 (7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 20 (8) 2 x I/O Read Mode (2READ)....................................................................................................................... 20 (9) Dual Read Mode (DREAD).......................................................................................................................... 20 (10) 4 x I/O Read Mode (4READ)..................................................................................................................... 21 (11) Quad Read Mode (QREAD)....................................................................................................................... 21 (12) Sector Erase (SE)...................................................................................................................................... 22 (13) Block Erase (BE)....................................................................................................................................... 22 (14) Block Erase (BE32K)................................................................................................................................. 22 (15) Chip Erase (CE)......................................................................................................................................... 23 (16) Page Program (PP)................................................................................................................................... 23 (17) 4 x I/O Page Program (4PP)...................................................................................................................... 23 Program/Erase Flow(1) - verify by reading array data...................................................................................... 25 Program/Erase Flow(2) - verify by reading program/erase fail flag bit.............................................................. 26 (18) Continuously program mode (CP mode)................................................................................................... 27 (19) Deep Power-down (DP)............................................................................................................................. 28 (20) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 28 (21) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)........................................... 28 Table 6. ID Definitions ...................................................................................................................................... 29 (22) Enter Secured OTP (ENSO)...................................................................................................................... 29 (23) Exit Secured OTP (EXSO)......................................................................................................................... 29 P/N: PM1586 REV. 1.0, JUL. 01, 2010 2 MX25L25735E (24) Read Security Register (RDSCUR)........................................................................................................... 29 Security Register Definition............................................................................................................................... 30 (25) Write Security Register (WRSCUR)........................................................................................................... 30 (26) Write Protection Selection (WPSEL).......................................................................................................... 31 BP and SRWD if WPSEL=0.............................................................................................................................. 31 The individual block lock mode is effective after setting WPSEL=1.................................................................. 32 WPSEL Flow..................................................................................................................................................... 33 (27) Single Block Lock/Unlock Protection (SBLK/SBULK)................................................................................ 34 Block Lock Flow................................................................................................................................................ 34 Block Unlock Flow............................................................................................................................................. 35 (28) Read Block Lock Status (RDBLOCK)........................................................................................................ 36 (29) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 36 (30) Clear SR Fail Flags (CLSR)....................................................................................................................... 36 (31) Enable SO to Output RY/BY# (ESRY)....................................................................................................... 36 (32) Disable SO to Output RY/BY# (DSRY)...................................................................................................... 36 POWER-ON STATE.................................................................................................................................................... 37 ELECTRICAL SPECIFICATIONS............................................................................................................................... 38 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 38 Figure 3. Maximum Negative Overshoot Waveform......................................................................................... 38 CAPACITANCE TA = 25C, f = 1.0 MHz............................................................................................................ 38 Figure 4. Maximum Positive Overshoot Waveform........................................................................................... 38 Figure 5. OUTPUT LOADING.......................................................................................................................... 39 Table 7. DC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V ~ 3.6V) .. 40 Table 8. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V ~ 3.6V) .41 Timing Analysis......................................................................................................................................................... 43 Figure 6. Serial Input Timing............................................................................................................................. 43 Figure 7. Output Timing..................................................................................................................................... 43 Figure 8. Hold Timing........................................................................................................................................ 44 Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1.................................................. 44 Figure 10. Write Enable (WREN) Sequence (Command 06)............................................................................ 45 Figure 11. Write Disable (WRDI) Sequence (Command 04)............................................................................. 45 Figure 12. Read Identification (RDID) Sequence (Command 9F)..................................................................... 45 Figure 13. Read Status Register (RDSR) Sequence (Command 05)............................................................... 46 Figure 14. Write Status Register (WRSR) Sequence (Command 01).............................................................. 46 Figure 15. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 47 Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 47 Figure 17. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 48 Figure 18. Dual Read Mode Sequence (Command 3B)................................................................................... 48 Figure 19. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 49 Figure 20. Quad Read Mode Sequence (Command 6B).................................................................................. 49 Figure 21. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)........................................... 50 Figure 22. Sector Erase (SE) Sequence (Command 20)................................................................................. 50 Figure 23. Block Erase (BE/EB32K) Sequence (Command D8/52)................................................................. 51 Figure 24. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 51 Figure 25. Page Program (PP) Sequence (Command 02).............................................................................. 51 Figure 26. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................. 52 P/N: PM1586 REV. 1.0, JUL. 01, 2010 3 MX25L25735E Figure 27. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD).................. 52 Figure 28. Deep Power-down (DP) Sequence (Command B9)....................................................................... 53 Figure 29. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB). .......................................................................................................................................................................... 53 Figure 30. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 53 Figure 31. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)......... 54 Figure 32. Write Protection Selection (WPSEL) Sequence (Command 68)..................................................... 54 Figure 33. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)...................... 55 Figure 34. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)................................. 55 Figure 35. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)....................................... 55 Figure 36. Power-up Timing.............................................................................................................................. 56 Table 9. Power-Up Timing................................................................................................................................. 56 INITIAL DELIVERY STATE............................................................................................................................... 56 OPERATING CONDITIONS........................................................................................................................................ 57 Figure 37. AC Timing at Device Power-Up........................................................................................................ 57 Figure 38. Power-Down Sequence................................................................................................................... 58 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 59 DATA RETENTION..................................................................................................................................................... 59 LATCH-UP CHARACTERISTICS............................................................................................................................... 59 ORDERING INFORMATION....................................................................................................................................... 60 PART NAME DESCRIPTION...................................................................................................................................... 61 PACKAGE INFORMATION......................................................................................................................................... 62 REVISION HISTORY ................................................................................................................................................. 64 P/N: PM1586 REV. 1.0, JUL. 01, 2010 4 MX25L25735E 256M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL * Serial Peripheral Interface compatible -- Mode 0 and Mode 3 * 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O mode) structure * 8192 Equal Sectors with 4K bytes each - Any Sector can be erased individually * 1024 Equal Blocks with 32K bytes each - Any Block can be erased individually * 512 Equal Blocks with 64K bytes each - Any Block can be erased individually * Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * 4-bytes address interface * Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE * High Performance VCC = 2.7~3.6V - Normal read - 50MHz - Fast read - 1 I/O: 80MHz with 8 dummy cycles - 2 I/O: 70MHz with 4 dummy cycles - 4 I/O: 70MHz with 6 dummy cycles - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Continuously Program mode (automatically increase address under word program mode) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.5s(typ.) /block (32K-byte per block); 0.7s(typ.) /block (64K-byte per block); 160s(typ.) /chip * Low Power Consumption - Low active read current: 45mA(max.) at 80MHz, 40mA(max.) at 70MHz and 30mA(max.) at 50MHz - Low active programming current: 25mA (max.) - Low active erase current: 25mA (max.) - Standby current: 200uA (max.) - Deep power down current: 80uA (max.) * Typical 100,000 erase/program cycles SOFTWARE FEATURES * Input Data Format - 1-byte Command code * Advanced Security Features - BP0-BP3 block group protect - Flexible individual block protect when OTP WPSEL=1 P/N: PM1586 REV. 1.0, JUL. 01, 2010 5 MX25L25735E - Additional 4K bits secured OTP for unique identifier * Auto Erase and Auto Program Algorithms - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programed should have page in the erased state first.) * Status Register Feature * Electronic Identification - JEDEC 1-byte Manufacturer ID and 2-byte Device ID - RES command for 1-byte Device ID - Both REMS, REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID HARDWARE FEATURES * SCLK Input - Serial clock input * SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode * SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode * WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O mode * HOLD#/SIO3 - HOLD# pin or serial data Input/Output for 4 x I/O mode, an internal weak pull up on the pin * PACKAGE - 16-pin SOP (300mil) - 8 WSON (8x6mm) - All Pb-free devices are RoHS Compliant P/N: PM1586 REV. 1.0, JUL. 01, 2010 6 MX25L25735E GENERAL DESCRIPTION MX25L25735E is 268,435,456 bits serial Flash memory with 4-bytes address interface, which is configured as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. The MX25L25735E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. MX25L25735E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and multi-I/O features. When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte), block (32K-byte/64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 200uA DC current. The MX25L25735E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Additional Features Additional Features Part Name MX25L25735E Protection and Security Read Performance Flexible or Individual block (or sector) protection 4K-bit secured OTP 1 I/O Read (80 MHz) 2 I/O Read (70 MHz) 4 I/O Read (70 MHz) V V V V V Additional Features Part Name MX25L25735E Identifier RES REMS REMS2 REMS4 RDID (command: AB hex) (command: 90 hex) (command: EF hex) (command: DF hex) (command: 9F hex) 18 (hex) C2 18 (hex) C2 18 (hex) P/N: PM1586 C2 18 (hex) C2 20 19 (hex) REV. 1.0, JUL. 01, 2010 7 MX25L25735E PIN CONFIGURATION PIN DESCRIPTION 16-PIN SOP (300mil) HOLD#/SIO3 VCC NC NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SYMBOL DESCRIPTION CS# Chip Select Serial Data Input (for 1xI/O)/ Serial Data SI/SIO0 Input & Output (for 2xI/O or 4xI/O mode) Serial Data Output (for 1xI/O)/Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O mode) SCLK Clock Input Write protection: connect to GND or WP#/SIO2 Serial Data Input & Output (for 4xI/O mode) HOLD#/ HOLD# pin or Serial Data Input & Output SIO3 (for 4xI/O mode) VCC + 3.3V Power Supply GND Ground NC No Connection SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 8-WSON (8x6mm) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC HOLD#/SIO3 SCLK SI/SIO0 P/N: PM1586 REV. 1.0, JUL. 01, 2010 8 MX25L25735E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SRAM Buffer Sense Amplifier CS# WP#/SIO2 HOLD#/SIO3 SCLK Mode Logic State Machine HV Generator Clock Generator Output Buffer SO/SIO1 P/N: PM1586 REV. 1.0, JUL. 01, 2010 9 MX25L25735E DATA PROTECTION MX25L25735E is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. * Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. * Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP, 4PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE, BE32K) command completion - Chip Erase (CE) command completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion - Write Security Register (WRSCUR) instruction completion - Write Protection Selection (WPSEL) instruction completion * Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Signature command (RES). I. Block lock protection - The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protected Area Sizes". - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O mode, the feature of HPM will be disabled. - MX25L25735E provide individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with GBLK instruction and unlock the whole chip with GBULK instruction. P/N: PM1586 REV. 1.0, JUL. 01, 2010 10 MX25L25735E Table 2. Protected Area Sizes Status bit Protection Area BP3 BP2 BP1 BP0 256Mb 0 0 0 0 0 (none) 0 0 0 1 1 (2 blocks, block 510th-511th) 0 0 1 0 2 (4 blocks, block 508th-511th) 0 0 1 1 3 (8 blocks, block 504th-511th) 0 1 0 0 4 (16 blocks, block 496th-511th) 0 1 0 1 5 (32 blocks, block 480th-511th) 0 1 1 0 6 (64 blocks, block 448nd-511th) 0 1 1 1 7 (128 blocks, block 384th-511th) 1 0 0 0 8 (256 blocks, block 256th-511th) 1 0 0 1 9 (512 blocks, all) 1 0 1 0 10 (512 blocks, all) 1 0 1 1 11 (512 blocks, all) 1 1 0 0 12 (512 blocks, all) 1 1 0 1 13 (512 blocks, all) 1 1 1 0 14 (512 blocks, all) 1 1 1 1 15 (512 blocks, all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Secured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1586 Customer Lock Determined by customer REV. 1.0, JUL. 01, 2010 11 MX25L25735E Memory Organization Table 4. Memory Organization Sector ... 8183 1FF7000h 1FF7FFFh ... 1FF0FFFh 1FEF000h 1FEFFFFh ... 1FE8FFFh 1FE7000h 1FE7FFFh ... 1FE0000h 1FE0FFFh 8159 1FDF000h 1FDFFFFh ... ... 8160 1019 509 ... 1FE8000h 8167 ... 8168 1020 individual block lock/unlock unit:64K-byte ... 1FF0000h 8175 ... 8176 1021 8152 1FD8000h 1FD8FFFh 8151 1FD7000h 1FD7FFFh ... ... ... 1018 individual 16 sectors lock/unlock unit:4K-byte ... ... 1FF8FFFh ... 1FF8000h 1022 510 1FFFFFFh 8184 1023 511 Address Range 1FFF000h ... 8191 ... Block(64K-byte) Block(32K-byte) 8144 1FD0000h 1FD0FFFh 47 002F000h 002FFFFh 0020000h 0020FFFh 31 001F000h 001FFFFh 0018000h 0018FFFh 23 0017000h 0017FFFh ... 2 24 P/N: PM1586 8 0008000h 0008FFFh 7 0007000h 0007FFFh ... ... 000FFFFh ... 0010FFFh 000F000h ... 0 0010000h 15 ... 0 16 ... 1 ... 1 ... 32 ... ... 0027FFFh ... 0028FFFh 027000h ... 3 0028000h 39 ... 4 individual block lock/unlock unit:64K-byte 40 ... 2 ... ... 5 ... individual block lock/unlock unit:64K-byte 0 0000000h 0000FFFh individual 16 sectors lock/unlock unit:4K-byte REV. 1.0, JUL. 01, 2010 12 MX25L25735E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD, RDBLOCK, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, ENPLM, EXPLM, ESRY, DSRY and CLSR the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported (for Normal Serial mode) CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1586 REV. 1.0, JUL. 01, 2010 13 MX25L25735E HOLD FEATURES HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2. Figure 2. Hold Condition Operation CS# SCLK HOLD# Hold Condition (standard) Hold Condition (non-standard) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. Note 1: The HOLD feature is disabled during Quad I/O mode in 16-SOP package. P/N: PM1586 REV. 1.0, JUL. 01, 2010 14 MX25L25735E COMMAND DESCRIPTION Table 5. Command Sets COMMAND WREN (write WRDI (write RDID (read (byte) enable) disable) identification) Command (hex) Input Cycles Dummy Cycles Action COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action 06 04 9F RDSR WRSR READ (read (read status (write status data) register) register) 05 2READ (2 x I/O read command) Note1 DREAD (1I 2O read) 01 03 BB 3B Data(8) ADD(32) ADD(16) ADD(32) 4 8 sets the resets the outputs JEDEC to read out to write new n bytes read n bytes read n bytes read (WEL) write (WEL) write ID: 1-byte the values values to out until CS# out by 2 x I/ out by Dual enable latch enable latch Manufacturer of the status the status goes high O until CS# output until bit bit ID & 2-byte register register goes high CS# goes Device ID high FAST READ (fast read data) 4READ (4 x I/O read command) QREAD (1I 4O read) 4PP (quad page program) SE (sector erase) 0B EB 6B 38 20 D8 52 ADD(32) ADD(8)+ indicator(2) ADD(32) ADD(8)+ Data(512) ADD(32) ADD(32) ADD(32) 8 4 8 to erase the selected 64KB block to erase the selected 32KB block n bytes read n bytes read n bytes read quad input to erase the out until CS# out by 4 x I/ out by Quad to program selected goes high O until CS# output until the selected sector goes high CS# goes page high PP (Page program) CE (chip erase) 60 or C7 to erase whole chip CP RDP REMS (read REMS2 (read REMS4 (read (Continuously DP (Deep (Release RES (read electronic ID for 2x I/O ID for 4x I/O program power down) from deep electronic ID) manufacturer mode) mode) mode) power down) & device ID) 02 AD ADD(32)+ Data(2048) ADD(32)+ Data(16) B9 AB AB 24 to program the selected page BE (block BE 32K (block erase 64KB) erase 32KB) 90 EF DF ADD(8) ADD(8) ADD(8) 16 16 16 continously enters deep release from to read out output the output the output the program power down deep power 1-byte Device Manufacturer Manufacturer Manufacturer whole mode down mode ID ID & Device ID & Device ID & device chip, the ID ID ID address is automatically increase P/N: PM1586 REV. 1.0, JUL. 01, 2010 15 MX25L25735E COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action COMMAND (byte) Command (hex) Input Cycles Dummy Cycles Action ESRY DSRY HPM (High ENSO (enter EXSO (exit RDSCUR WRSCUR CLSR (Clear (enable SO (disable SO Performsecured secured (read security (write security SR Fail to output RY/ to output RY/ ance Enable OTP) OTP) register) register) Flags) BY#) BY#) Mode) B1 C1 2B 2F 70 80 30 A3 to enter to exit the 4K- to read value to set the to enable SO to disable SO clear security Quad I/O the 4K-bit bit Secured of security lock-down bit to output RY/ to output RY/ register bit 6 high PerformSecured OTP OTP mode register as "1" (once BY# during BY# during and bit 5 ance mode mode lock-down, CP mode CP mode cannot be updated) WPSEL (write SBLK (single SBULK RDBLOCK GBLK (gang GBULK (gang protection block lock) (single block (block protect block lock) block unlock) selection) *Note 2 unlock) read) 68 36 39 3C ADD(32) ADD(32) ADD(32) to enter individual and enable block (64Kindividal byte) or block protect sector (4Kmode byte) write protect 7E individual read whole chip block (64Kindividual write protect byte) or block or sector sector write (4K-byte) protect status unprotect 98 whole chip unprotect Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 2: In individual block write protection mode, all blocks/sectors is locked as defualt. Note 3: The number in parentheses afer "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles for the data in. P/N: PM1586 REV. 1.0, JUL. 01, 2010 16 MX25L25735E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, BE32K, CE, WRSR, WRSCUR, WPSEL, SBLK, SBULK, GBLK and GBULK, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low sending WREN instruction code CS# goes high. (Please refer to Figure 10) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low sending WRDI instruction code CS# goes high. (Please refer to Figure 11) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP, 4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE, BE32K) instruction completion - Chip Erase (CE) instruction completion - Continuously Program mode (CP) instruction completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion - Write Security Register (WRSCUR) instruction completion - Write Protection Selection (WPSEL) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6) The sequence of issuing RDID instruction is: CS# goes low sending RDID instruction code 24-bits ID data out on SO to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 12) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1586 REV. 1.0, JUL. 01, 2010 17 MX25L25735E (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low sending RDSR instruction code Status Register data out on SO (Please refer to Figure 13). The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and will reset WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, HOLD# are enable. While QE is "1", it performs Quad I/O mode and WP#, HOLD# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and HOLD# will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) 1= Quad 1=status Enable register write 0=not Quad disable Enable Non-volatile Non-volatile bit bit bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note 1: see the Table 2 "Protected Area Size" in page 11. P/N: PM1586 REV. 1.0, JUL. 01, 2010 18 MX25L25735E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low sending WRSR instruction code Status Register data on SI CS# goes high. (Please refer to Figure 14) The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system goes into four I/O mode, the feature of HPM will be disabled. P/N: PM1586 REV. 1.0, JUL. 01, 2010 19 MX25L25735E (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low sending READ instruction code 4-byte address on SI data out on SO to end READ operation can use CS# to high at any time during data out. (Please refer to Figure 15) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low sending FAST_READ instruction code 4-byte address on SI 1-dummy byte (default) address on SI data out on SO to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to Figure 16) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) 2 x I/O Read Mode (2READ) The 2READ instruction enables Double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 4-byte address interleave on SIO1 & SIO0 4-bit dummy cycle on SIO1 & SIO0 data out interleave on SIO1 & SIO0 to end 2READ operation can use CS# to high at any time during data out (Please refer to Figure 17 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (9) Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instrucP/N: PM1586 REV. 1.0, JUL. 01, 2010 20 MX25L25735E tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low sending DREAD instruction 4-byte address on SI 8-bit dummy cycle data out interleave on SO1 & SO0 to end DREAD operation can use CS# to high at any time during data out (Please refer to Figure 18 for Dual Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) 4 x I/O Read Mode (4READ) The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low sending 4READ instruction 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 19 for 4 x I/O Read Mode Timing Waveform). Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low sending 4 READ instruction 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling bit P[7:0] 4 dummy cycles data out still CS# goes high CS# goes low (reduce 4 Read instruction) 4-byte address random access address (Please refer to Figure 21 for 4x I/O Read Enhance Performance Mode timing waveform). In the performance-enhancing mode (the waveform figure), P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (11) Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status register must be set to "1" before sending the QREAD. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low sending QREAD instruction 4-byte address on SI 8-bit dummy cycle data out interleave on SO3, SO2, SO1 & SO0 to end QREAD operation can use CS# to high at any time during data out (Please refer to Figure 20 for Quad Read Mode Timing Waveform). P/N: PM1586 REV. 1.0, JUL. 01, 2010 21 MX25L25735E While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (12) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (Table of memory organization) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing SE instruction is: CS# goes low sending SE instruction code 4-byte address (depending on mode state) on SI CS# goes high. (Please refer to Figure 22) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (13) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Table of memory organization) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low sending BE instruction code 4-byte address on SI CS# goes high. (Please refer to Figure 23) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (14) Block Erase (BE32K) The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32). Any address of the block (Table of memory organization) is a valid address for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32 instruction is: CS# goes low sending BE32 instruction code 4-byte address on SI CS# goes high. (Please refer to Figure 23) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in P/N: PM1586 REV. 1.0, JUL. 01, 2010 22 MX25L25735E Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. (15) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low sending CE instruction code CS# goes high. (Please refer to Figure 24) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset. (16) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low sending PP instruction code 4-byte address on SI at least 1-byte on data on SI CS# goes high. (Please refer to Figure 25) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. (17) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, P/N: PM1586 REV. 1.0, JUL. 01, 2010 23 MX25L25735E and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low sending 4PP instruction code 4-byte address on SIO[3:0] at least 1-byte on data on SIO[3:0] CS# goes high. (Please refer to Figure 26) If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. P/N: PM1586 REV. 1.0, JUL. 01, 2010 24 MX25L25735E The Program/Erase function instruction function flow is as follows: Program/Erase Flow(1) - verify by reading array data Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase fail Program/erase successfully CLSR(30h) command Program/erase another block? No Yes * * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1586 REV. 1.0, JUL. 01, 2010 25 MX25L25735E Program/Erase Flow(2) - verify by reading program/erase fail flag bit Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes RDSCUR command REGPFAIL/REGEFAIL=1? Yes No Program/erase fail Program/erase successfully CLSR(30h) command Program/erase Yes another block? No * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1586 REV. 1.0, JUL. 01, 2010 26 MX25L25735E (18) Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# goes low sending CP instruction code 4-byte address on SI pin two data bytes on SI CS# goes high to low sending CP instruction and then continue two data bytes are programmed CS# goes high to low till last desired two data bytes are programmed CS# goes high to low sending WRDI (Write Disable) instruction to end CP mode send RDSR instruction to verify if CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 27 of CP mode timing waveform) Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not accepted unless the completion of CP mode. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. P/N: PM1586 REV. 1.0, JUL. 01, 2010 27 MX25L25735E (19) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low sending DP instruction code CS# goes high. (Please refer to Figure 28) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (20) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 8. Once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/write cycles in progress. The sequence is shown as Figure 29, 30. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power-down Mode. (21) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2, and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 28. The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1586 REV. 1.0, JUL. 01, 2010 28 MX25L25735E Table 6. ID Definitions Command Type RDID manufacturer ID C2 RES REMS/REMS2/REMS4 manufacturer ID C2 MX25L25735E memory type 20 electronic ID 18 device ID 18 memory density 19 (22) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low sending ENSO instruction to enter Secured OTP mode CS# goes high. Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not acceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands are valid. (23) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low sending EXSO instruction to exit Secured OTP mode CS# goes high. (24) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low sending RDSCUR instruction Security Register data out on SO CS# goes high. The definition of the Security Register is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit Secured OTP mode, array access is not allowed. P/N: PM1586 REV. 1.0, JUL. 01, 2010 29 MX25L25735E Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can indicate whether one or more of program operations fail, and can be reset by command CLSR (30h) Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate whether one or more of erase operations fail, and can be reset by command CLSR (30h) Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully. Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. Security Register Definition bit7 bit6 bit5 bit4 bit3 bit2 x x bit1 bit0 WPSEL E_FAIL P_FAIL Continuously Program mode (CP mode) LDSO (lock-down 4K-bit 4K-bit Se- Secured OTP cured OTP) 0 = not lockdown 0= 1 = locknonfactory down lock (cannot 1 = factory program/ lock erase OTP) 0=normal WP mode 1=individual WP mode (default=0) 0=normal Erase succeed 1=indicate Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) 0=normal Program mode 1=CP mode (default=0) reserved reserved non-volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit OTP Read Only Read Only Read Only Read Only Read Only OTP Read Only (25) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low sending WRSCUR instruction CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1586 REV. 1.0, JUL. 01, 2010 30 MX25L25735E (26) Write Protection Selection (WPSEL) There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0, flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value of WPSEL is "0". WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to "0". If the flash is put on BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode is disabled. Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted. BP protection mode, WPSEL=0: ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by "SRWD=1 and WP#=0", where SRWD is bit 7 of status register that can be set by WRSR command. Individual block protection mode, WPSEL=1: Blocks are individually protected by their own SRAM lock bits which are set to "1" after power up. SBULK and SBLK command can set SRAM lock bit to "0" and "1". When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. The sequence of issuing WPSEL instruction is: CS# goes low sending WPSEL instruction to enter the individual block protect mode CS# goes high. WPSEL instruction function flow is as follows: BP and SRWD if WPSEL=0 WPB pin BP3 BP2 BP1 BP0 SRWD 64KB 64KB 64KB (1) BP3~BP0 is used to define the protection group region. (The protected area size see Table2) (2) "SRWD=1 and WPB=0" is used to protect BP3~BP0. In this case, SRWD and BP3~BP0 of status register bits can not be changed by WRSR . . . 64KB P/N: PM1586 REV. 1.0, JUL. 01, 2010 31 MX25L25735E The individual block lock mode is effective after setting WPSEL=1 SRAM SRAM ... ... TOP 4KBx16 Sectors 4KB 4KB 4KB SRAM SRAM ... 64KB SRAM ... ...... Uniform 64KB blocks 64KB 4KB SRAM ... ... Bottom 4KBx16 Sectors 4KB SRAM * Power-Up: All SRAM bits=1 (all blocks are default protected). All array cannot be programmed/erased * SBLK/SBULK(36h/39h): - SBLK(36h) : Set SRAM bit=1 (protect) : array can not be programmed /erased - SBULK(39h): Set SRAM bit=0 (unprotect): array can be programmed /erased - All top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and unprotected SRAM bits individually by SBLK/SBULK command set. * GBLK/ GBULK(7Eh/98h): - GBLK(7Eh):Set all SRAM bits=1,whole chip are protected and cannot be programmed / erased. - GBULK(98h):Set all SRAM bits=0,whole chip are unprotected and can be programmed / erased. - All sectors and blocks SRAM bits of whole chip can be protected and unprotected at one time by GBLK/GBULK command set. * RDBLOCK(3Ch): - use RDBLOCK mode to check the SRAM bits status after SBULK /SBLK/GBULK/GBLK command set. SBULK / SBLK / GBULK / GBLK / RDBLOCK P/N: PM1586 REV. 1.0, JUL. 01, 2010 32 MX25L25735E WPSEL Flow start RDSCUR(2Bh) command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command WIP=0? No Yes RDSCUR(2Bh) command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by individual lock (SBLK, SBULK, ... etc). P/N: PM1586 REV. 1.0, JUL. 01, 2010 33 MX25L25735E (27) Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block(or sector) of memory, using address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CS# goes low send SBLK/SBULK (36h/39h) instruction send 4-byte address assign one block (or sector) to be protected on SI pin CS# goes high. (Please refer to Figure 33) The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. SBLK/SBULK instruction function flow is as follows: Block Lock Flow Start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBLK command ( 36h address ) RDSR command WIP=0? No Yes RDBLOCK command ( 3Ch address ) Data = FFh ? No Yes Block lock successfully Lock another block? Block lock fail Yes No Block lock completed P/N: PM1586 REV. 1.0, JUL. 01, 2010 34 MX25L25735E Block Unlock Flow start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBULK command ( 39h address ) RDSR command No WIP=0? Yes Unlock another block? Yes Unlock block completed? P/N: PM1586 REV. 1.0, JUL. 01, 2010 35 MX25L25735E (28) Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block(or sector), using address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low send RDBLOCK (3Ch) instruction send 4-byte address to assign one block on SI pin read block's protection lock status bit on SO pin CS# goes high. (Please refer to Figure 34) (29) Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low send GBLK/GBULK (7Eh/98h) instruction CS# goes high. (Please refer to Figure 35) The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. (30) Clear SR Fail Flags (CLSR) The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed before program/erase another block during programming/erasing flow without read array data. The sequence of issuing CLSR instruction is: CS# goes low send CLSR instruction code CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. (31) Enable SO to Output RY/BY# (ESRY) The ESRY instruction is for outputting the ready/busy status to SO during CP mode. The sequence of issuing ESRY instruction is: CS# goes low sending ESRY instruction code CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. (32) Disable SO to Output RY/BY# (DSRY) The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after DSRY issued. The sequence of issuing DSRY instruction is: CS# goes low send DSRY instruction code CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1586 REV. 1.0, JUL. 01, 2010 36 MX25L25735E POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not Deep Power-down mode) - Write Enable Latch (WEL) bit is reset - 4-byte address mode The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1586 REV. 1.0, JUL. 01, 2010 37 MX25L25735E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Industrial grade Ambient Operating Temperature Storage Temperature -40C to 85C -55C to 125C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 3, 4. Figure 4. Maximum Positive Overshoot Waveform Figure 3. Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25C, f = 1.0 MHz SYMBOL PARAMETER CIN COUT MIN. TYP MAX. UNIT Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V P/N: PM1586 CONDITIONS REV. 1.0, JUL. 01, 2010 38 MX25L25735E Figure 5. OUTPUT LOADING DEVICE UNDER 2.7K ohm TEST CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=30/15pF Including jig capacitance P/N: PM1586 REV. 1.0, JUL. 01, 2010 39 MX25L25735E Table 7. DC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V ~ 3.6V) SYMBOL PARAMETER NOTES MIN. MAX. UNITS TEST CONDITIONS ILI Input Load Current 1 4 uA VCC = VCC Max, VIN = VCC or GND, HOLD# = VCC ILO Output Leakage Current 1 4 uA VCC = VCC Max, VIN = VCC or GND ISB1 VCC Standby Current 1 200 uA VIN = VCC or GND, CS# = VCC, HOLD# = VCC ISB2 Deep Power-down Current 80 uA VIN = VCC or GND, CS# = VCC, HOLD# = VCC 45 mA f=80MHz, fQ=70MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 40 mA fT=70MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 30 mA f=50MHz, SCLK=0.1VCC/0.9VCC, SO=Open 25 mA Program in Progress, CS# = VCC 40 mA Program status register in progress, CS#=VCC 1 25 mA Erase in Progress, CS#=VCC 1 40 mA Erase in Progress, CS#=VCC 0.8 V ICC1 VCC Read VIL VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 ICC3 ICC4 ICC5 1 1 -0.5 0.7VCC VCC+0.4 0.4 VCC-0.2 P/N: PM1586 V V IOL = 1.6mA V IOH = -100uA REV. 1.0, JUL. 01, 2010 40 MX25L25735E Table 8. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter fSCLK fC fRSCLK fR fT fQ fTSCLK f4PP tCH(1) tCLH tCL(1) tCLL tCLCH(2) tCHCL(2) tSLCH tCSS tCHSL tDVCH tDSU tCHDX tDH tCHSH tSHCH tSHSL(3) tCSH tSHQZ(2) tDIS tCLQV tV tCLQX tHLCH tCHHH tHHCH tCHHL tHO tHHQX(2) tLZ tHLQZ(2) tHZ tWHSL(4) tSHWL(4) tDP(2) Min. Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR Clock Frequency for READ instructions Clock Frequency for 2READ/DREAD instructions Clock Frequency for 4READ/QREAD instructions Clock Frequency for 4PP (Quad page program) Fast_Read Clock High Time Read Fast_Read Clock Low Time Read Clock Rise Time (3) (peak to peak) Clock Fall Time (3) (peak to peak) CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) Data In Setup Time Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read CS# Deselect Time Write/Erase/ Program 2.7V-3.6V Output Disable Time 3.0V-3.6V 1 I/O Clock Low to Output Valid Loading: 15pF 2 I/O & 4 I/O VCC=2.7V~3.6V Loading: 30pF 2 I/O & 4 I/O Output Hold Time HOLD# Setup Time (relative to SCLK) HOLD# Hold Time (relative to SCLK) HOLD Setup Time (relative to SCLK) HOLD Hold Time (relative to SCLK) 2.7V-3.6V HOLD to Output Low-Z 3.0V-3.6V 2.7V-3.6V HOLD# to Output High-Z 3.0V-3.6V Write Protect Setup Time Write Protect Hold Time CS# High to Deep Power-down Mode P/N: PM1586 Max. Unit 80 MHz 50 70 70 20 5.5 9 5.5 9 0.1 0.1 8 5 2 5 5 8 15 MHz MHz MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns 100 ns D.C. 2 8 5 8 5 20 100 Typ. 12 10 12 12 15 12 10 12 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us REV. 1.0, JUL. 01, 2010 41 MX25L25735E Symbol tRES1(2) tRES2(2) tW tBP tPP tSE tBE tBE tCE tWPS tWSR Alt. Parameter CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time (4KB) Block Erase Cycle Time (32KB) Block Erase Cycle Time (64KB) Chip Erase Cycle Time Write Protection Selection Time Write Security Register Time Min. Typ. 40 9 1.4 60 0.5 0.7 160 Max. Unit 100 us 100 us 100 300 5 300 2 2 400 1 1 ms us ms ms s s s ms ms Notes: 1. tCH + tCL must be greater than or equal to 1/ fC. 2. Value guaranteed by characterization, not 100% tested in production. 3.Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. P/N: PM1586 REV. 1.0, JUL. 01, 2010 42 MX25L25735E Timing Analysis Figure 6. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 7. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tSHQZ tCLQX LSB SO tQLQH tQHQL SI ADDR.LSB IN P/N: PM1586 REV. 1.0, JUL. 01, 2010 43 MX25L25735E Figure 8. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# * SI is "don't care" during HOLD operation. Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI SO High-Z P/N: PM1586 REV. 1.0, JUL. 01, 2010 44 MX25L25735E Figure 10. Write Enable (WREN) Sequence (Command 06) CS# 0 1 2 3 4 5 6 7 5 6 7 SCLK Command SI 06 High-Z SO Figure 11. Write Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 SCLK Command SI 04 High-Z SO Figure 12. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification SO High-Z Device Identification D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 MSB D3 D2 D1 D0 MSB P/N: PM1586 REV. 1.0, JUL. 01, 2010 45 MX25L25735E Figure 13. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI SO Status Register Out High-Z D7 D6 D5 D4 D3 D2 D1 D0 MSB Figure 14. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI SO command Status Register In 01 D7 D6 D5 D4 D3 D2 D1 D0 MSB High-Z P/N: PM1586 REV. 1.0, JUL. 01, 2010 46 MX25L25735E Figure 15. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command 32 ADD Cycles 03 SI A31 A30 A29 A3 A2 A1 A0 MSB Data Out 1 High-Z SO Data Out 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 MSB MSB Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Command SI SO 0B 32 ADD Cycles A31 A30 A29 8 Dummy Cycles A3 A2 A1 A0 Data Out 1 High-Z Data Out 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 MSB P/N: PM1586 REV. 1.0, JUL. 01, 2010 47 MX25L25735E Figure 17. 2 x I/O Read Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 SCLK Command 4 dummy cycle 16 ADD Cycle BB(hex) SI/SIO0 SO/SIO1 22 23 24 25 26 27 28 29 30 31 32 33 9 High Impedance Data Out 1 Data Out 2 A30 A28 A2 A0 P2 P0 D6 D4 D2 D0 D6 D4 A31 A29 A3 A1 P3 P1 D7 D5 D3 D1 D7 D5 Note: 1. SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or P3=P1 is necessary. Figure 18. Dual Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 Command SI/SIO0 SO/SIO1 38 39 40 9 SCLK 3B 32 ADD Cycle A31 A30 High Impedance 47 48 49 50 51 52 53 A1 A0 8 dummy cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 P/N: PM1586 REV. 1.0, JUL. 01, 2010 48 MX25L25735E Figure 19. 4 x I/O Read Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCLK Command EB SI/SIO0 SO/SIO1 WP#/SIO2 HOLD#/SIO3 8 ADD Cycles High Impedance High Impedance High Impedance Performance Enhance Indicator (Note1, 2) 4 dummy cycles Data Data Out 1 Out 2 Data Out 3 A28 A24 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 A29 A25 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 A30 A26 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 A31 A27 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 Note: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7P3, P6P2, P5P1 & P4P0 (Toggling) will result in entering the performance enhance mode. Figure 20. Quad Read Mode Sequence (Command 6B) CS# 0 1 2 3 4 5 6 7 8 ... Command SI/SO0 SO/SO1 WP#/SO2 HOLD#/SO3 37 38 39 40 41 9 SCLK 6B ... 32 ADD Cycles A31 A30 ... High Impedance 46 47 48 49 50 A2 A1 A0 8 dummy cycles Data Data Out 1 Out 2 Data Out 3 D4 D0 D4 D0 D4 D5 D1 D5 D1 D5 High Impedance D6 D2 D6 D2 D6 High Impedance D7 D3 D7 D3 D7 P/N: PM1586 REV. 1.0, JUL. 01, 2010 49 MX25L25735E Figure 21. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) CS# 0 1 SCLK SI/SIO0 SO/SIO1 WP#/SIO2 HOLD#/SIO3 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 n+1 n+11 n+9 n+15 4 dummy cycles Command 8 ADD Cycles EB A28 A24 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 A28 A0 P4 P0 D4 D0 D4 D0 D4 A29 A25 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 A29 A1 P5 P1 D5 D1 D5 D1 D5 A30 A26 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 A30 A2 P6 P2 D6 D2 D6 D2 D6 A31 A27 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 A31 A3 P7 P3 D7 D3 D7 D3 D7 High Impedance High Impedance High Impedance Performance enhance indicator (Note) Data Data Out 1 Out 2 8 ADD Cycles Performance enhance indicator (Note) 4 dummy cycles Data Data Out 1 Out 2 Data Out 3 Note: 1. Performance enhance mode, if P7P3 & P6P2 & P5P1 & P4P0 (Toggling), ex: A5, 5A, 0F 2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF Figure 22. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 SCLK ... 32 ADD Cycles Command SI 37 38 39 A31 A30 20 ... A2 A1 A0 MSB P/N: PM1586 REV. 1.0, JUL. 01, 2010 50 MX25L25735E Figure 23. Block Erase (BE/EB32K) Sequence (Command D8/52) CS# 0 1 2 3 4 5 6 7 8 9 37 38 39 SCLK 32 ADD Cycles Command SI D8/52 A31 A30 A2 A1 A0 MSB Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Figure 25. Page Program (PP) Sequence (Command 02) 2087 2086 2085 2084 2083 2082 36 37 38 39 40 41 42 43 44 45 46 47 2081 0 1 2 3 4 5 6 7 8 9 10 2080 CS# SCLK Command SI 02 32 ADD Cycles A31 A30 A29 MSB A3 A2 A1 A0 Data Byte 1 Data Byte 256 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB P/N: PM1586 REV. 1.0, JUL. 01, 2010 51 MX25L25735E Figure 26. 4 x I/O Page Program (4PP) Sequence (Command 38) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCLK 526 527 Command 8 ADD cycles Data Byte 256 Data Data Byte 1 Byte 2 A28 A24 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 SO/SIO1 A29 A25 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 WP#/SIO2 A30 A26 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 HOLD#/SIO3 A31 A27 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 D7 D3 38 SI/SIO0 Figure 27. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) CS# 0 1 6 7 8 9 38 39 40 41 55 56 0 1 6 7 8 28 29 30 31 32 0 7 0 7 8 SCLK Command SI S0 AD (hex) 32-bit address data in Byte 0, Byte1 Valid Command (Note 1) high impedance data in Byte n-1, Byte n 04 (hex) 05 (hex) status (Note 2) Note: 1. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). 2. Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS# goes high will return the SO pin to tri-state. 3. To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP mode is ended. P/N: PM1586 REV. 1.0, JUL. 01, 2010 52 MX25L25735E Figure 28. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Stand-by Mode Deep Power-down Mode Figure 29. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI tRES2 24 Dummy Cycles 23 22 21 AB ... 3 2 1 0 MSB Electronic Signature Out High-Z SO D7 D6 D5 D4 D3 D2 D1 D0 MSB Deep Power-down Mode Stand-by Mode Figure 30. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI SO AB High-Z Deep Power-down Mode P/N: PM1586 Stand-by Mode REV. 1.0, JUL. 01, 2010 53 MX25L25735E Figure 31. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI SO 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 2 Dummy Bytes 15 14 13 90 ADD (1) 3 2 1 0 7 6 5 4 3 2 1 0 Manufacturer ID High-Z Device ID D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB MSB MSB Notes: 1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A31 is don't care. 2. Instruction is either 90(hex) or EF(hex) or DF(hex). Figure 32. Write Protection Selection (WPSEL) Sequence (Command 68) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 68 P/N: PM1586 REV. 1.0, JUL. 01, 2010 54 MX25L25735E Figure 33. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) CS# 0 1 2 3 4 5 6 7 8 9 37 38 39 SCLK 32 ADD Cycles Command SI 36/39 A31 A30 A2 A1 A0 MSB Figure 34. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command SI 3C 32 ADD Cycles A31 A30 A29 A3 A2 A1 A0 MSB SO Block Protection Lock status out High-Z D7 D6 D5 D4 D3 D2 D1 D0 MSB Figure 35. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 7E/98 P/N: PM1586 REV. 1.0, JUL. 01, 2010 55 MX25L25735E Figure 36. Power-up Timing VCC VCC(max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed VCC(min) tVSL Reset State of the Flash Read Command is allowed Device is fully accessible VWI tPUW time Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Table 9. Power-Up Timing Symbol tVSL(1) tPUW(1) vWI(1) Parameter VCC(min) to CS# low Time delay to write instruction Write inhibit voltage Min. 300 1 1.5 Max. 10 2.5 Unit us ms V Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1586 REV. 1.0, JUL. 01, 2010 56 MX25L25735E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in Figure 37 and Figure 38 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 37. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. 20 Max. 500000 Unit us/V Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1586 REV. 1.0, JUL. 01, 2010 57 MX25L25735E Figure 38. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1586 REV. 1.0, JUL. 01, 2010 58 MX25L25735E ERASE AND PROGRAMMING PERFORMANCE PARAMETER TYP. (1) Max. (2) UNIT Write Status Register Cycle Time 40 100 ms Sector Erase Time (4KB) 60 300 ms Block Erase Time (64KB) 0.7 2 s Block Erase Time (32KB) 0.5 2 s Chip Erase Time 160 400 s 9 300 us 1.4 5 ms Byte Program Time (via page program command) Page Program Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25C, 3.3V, and checker board pattern. 2. Under worst conditions of 85C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. DATA RETENTION PARAMETER Condition Min. Data retention 55C 20 Max. UNIT years LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1586 MIN. -1.0V -1.0V -100mA MAX. 2 VCCmax VCC + 1.0V +100mA REV. 1.0, JUL. 01, 2010 59 MX25L25735E ORDERING INFORMATION CLOCK (MHz) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (uA) TEMPERATURE MX25L25735EMI-12G 80 45 200 -40C~85C MX25L25735EZNI-12G 80 45 200 -40C~85C PART NO. P/N: PM1586 PACKAGE 16-SOP (300mil) 8-WSON (8x6mm) Remark Pb-free Pb-free REV. 1.0, JUL. 01, 2010 60 MX25L25735E PART NAME DESCRIPTION MX 25 L 25735E M I 12 G OPTION: G: Pb-free SPEED: 12: 80MHz TEMPERATURE RANGE: I: Industrial (-40 C to 85 C) PACKAGE: M: 300mil 16-SOP ZN: 8x6mm 8-WSON DENSITY & MODE: 25735E: 256Mb Quad I/O with 4-bytes address TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1586 REV. 1.0, JUL. 01, 2010 61 MX25L25735E PACKAGE INFORMATION P/N: PM1586 REV. 1.0, JUL. 01, 2010 62 MX25L25735E P/N: PM1586 REV. 1.0, JUL. 01, 2010 63 MX25L25735E REVISION HISTORY Revision No. Description 1.0 1. Removed DMC sequence description & content table 2. Removed command WREN in WPSEL and WRSCUR flows 3. Removed "Preliminary" P/N: PM1586 Page P6,13,16 P30,31,33 P5 Date JUL/01/2010 REV. 1.0, JUL. 01, 2010 64 MX25L25735E Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. Copyright(c) Macronix International Co., Ltd. 2010. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo, MXSMIO, are trademarks or registered trademarks of Macronix International Co., Ltd.. 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