EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRD98L59
CCD Image Digitizers with
CDS, PGA and 10-Bit A/D
January 2001-2
FEATURES
•10-bit Resolution ADC
•20MHz Sampling Rate
•Programmable Gain: 6dB to 38dB PGA
(2x to 80x)
•Improved Digitally Controlled Offset-Calibration
with Pixel Averager and Hot Pixel Clipper
•DNS Filter Removes Black Level Digital Noise
•Widest Black Level Calibration Range at
Maximum Gain
•Manual Control of Offset DAC via Serial Port for
Use with High Speed Scanners
•2ns/step Programmable Aperture Delay on SPIX
and SBLK
•Single 2.7V to 3.6V Power Supply
•Low Power for Battery Operation:120mW @ VDD=3V
APPLICATIONS
•Digital Still Cameras
•Digital Camcorders
•PC Video Cameras
•CCTV/Security Cameras
•Industrial/Medical Cameras
•2D Bar Code Readers
•High Speed Scanners
•Digital Copiers
GENERAL DESCRIPTION
The XRD98L59 is a complete low power CCD Image
Digitizer for digital, motion and still cameras. The
product includes a high bandwidth differential Corre-
lated Double Sampler (CDS), 8-bit digitally Program-
mable Gain Amplifier (PGA), 10-bit Analog-to-Digital
Converter (ADC) and improved digitally controlled
black level auto-calibration circuitry with pixel averager
hot pixel clipper, and a DNS filter.
The Correlated Double Sampler (CDS) subtracts the
CCD output signal black level from the video level.
Common mode signal and power supply noise are
rejected by the differential CDS input stage.
The PGA is digitally controlled with 8-bit resolution on
a linear dB scale, resulting in a gain range of 6dB to
38dB with 0.125dB per LSB of the gain code.
The auto calibration circuit compensates for any inter-
nal offset of the XRD98L59 as well as black level offset
from the CCD.
The PGA and black level auto-calibration are con-
trolled through a simple 3-wire serial interface. The
timing circuitry is designed to enable users to select a
wide variety of available CCD and image sensors for
their applications.
The XRD98L59 has direct access to the ADC input for
digitizing other analog signals. The XRD98L59 is
packaged in 28-lead surface mount TSSOP to reduce
space and weight, and is suitable for hand-held and
portable applications.
•5µA Typical Stand By Mode Current
•Three-State Digital Outputs
•2,000V ESD Protection
•28-pin TSSOP Package
Rev. 2.00
ORDERING INFORMATION
Operating Maximum
Part No. Package Temperature Range Power Supply Sampling Rate
XRD98L59AIG 28-Lead TSSOP -40°C to 85°C 3.0V 20 MSPS
XRD98L59
2
Rev. 2.00
Figure 1. XRD98L59 Block Diagram
CDS 10-bit ADC
Hot Pixel
Clipper
Pixel
Averager
+
-
+
Coarse
Accumulator Fine
Accumulator
Offset Calibration Logic
10
PGA1 Reg
Serial Interface
and Registers
Internal Clock
Generator
PGA2
Calibration Mode
Target Offset Code
Gain Code
Clock
Control
AVDD DVDD
AGND DGND
OVDD
OGND
DB[9:0]
CCDin
VRT VRB
REFin
SPIX
SBLK
CLAMP
CAL
SCLK
SDI
LOAD
PD
4-bit 10-bit
+
+
10
Power Down
400140 60 AGNDAVDD
Power
Down
Manual DAC
Control
Black Level
Offset Calibration Loop
ADCIN
CDAC FDAC
DNS
Filter
3
Rev. 2.00
XRD98L59
PIN CONFIGURATION
28-Lead TSSOP
PIN DESCRIPTION
XRD98L59
SPIX
CAL
CLAM
P
'
&
%
"
$
#
!
#
$
%
&
'
!
"
"
!
#
$
%
&
CCDin
REFin
AGND
VRB
DB7
DB8
DB9
OVDD
DB6
DB5
DVDD
VRT
SCLK
LOAD
SDI
PD
DGND
AVDD
SBLK
DB1
DB0
DB2
DB3
DB4
OGND
Pin # Symbol Descripti on
1OV
DD Digital Output Power Supp ly (< AVDD )
2 DB5 ADC Output
3 DB6 ADC Output
4 DB7 ADC Output
5 DB8 ADC Output
6 DB9 ADC Output, MSB
7DV
DD Digital Power Supply (Mu st = AVDD )
8 DGND Digital Groun d. Connect to AGND
9 SCLK Shift Clock. Latches SDI data on Serial Port
10 SDI Serial Data Input. Serial Port
11 LOAD Data Load. Serial Port
12 PD Power Down, Active High
13 VRT Top ADC Referenc e. Sets full scale of ADC
14 AVDD Analog VDD
15 CCDIN CDS inverting input. Connect through capacitor to CCD signal
16 REFIN Reference i nput (CDS non inverting input) . Connect through capa cit or
to CCD Gr ound
17 AGND Analog Ground
18 V RB Bottom A D C Refere n c e. Se ts ze ro fo r A DC .
19 CAL Optical Black (O B) Clamp
20 CLAMP CDS DC Restore Clamp
21 SPIX Sample Video Pixe l (CDS Clock)
22 SBLK Sample Black Reference (CDS Clock)
23 DB0 ADC Output, LSB
24 DB1 ADC Output
25 DB2 ADC Output
26 DB3 ADC Output
27 DB4 ADC Output
28 OGND D igital Output GND. Connect to AGND
XRD98L59
4
Rev. 2.00
DC ELECTRICAL CHARACTERISTICS – XRD98L59
Unless otherwise specified: OVDD = DVDD = AVDD = 3.0V, Pixel Rate = 20MSPS, TA = 25°C
Symbol Parameter Min. Typ. Max. Unit Conditions
CDS Performance
CDSVIN Input Range 800 mVPP Pixel (VBlack - VVideo), (See Figure 2)
VDARK Maximum Dark Voltage Offset 1 5 0 mV At any gain. (See Figure 2)
rON CLAMP On Resistance 120 Ω
PGA Parameters
AVMIN Minimum Gain 3.5 5 6.5 dB
AVMAX Maximum Gain 36 dB
PGA n Resolution 8 bits Transfer function is linear steps in dB
(1LSB = 0.125dB)
ADC Parameters (Measured in ADCIN Test Mode), SDI = 0100 0000 0101 b
ADC n Resolution 10 bits
fsMax Sample Rate 2 0 MSPS
DNL Differential Non-Linearity -1 +0.75 1.5 LSB
EZS Zero Scale Error +25 mV Measured relative to VRB
EFS Full Scale Error 1.5 % FS
VIN DC Input Range GND AVDD VAV
IN of the ADC can swing from AGND
to AVDD. Input range is limited by
the output swing of the PGA.
∆VREF ADC Reference Voltage 2 V
VRB Self Bias VRB 0.2 0.3 0.4 V
VRT Self Bias VRT 2.0 2.3 2.6 V
(
VRB = AVDD
10
)
(
VRB = AVDD
1.30
)
5
Rev. 2.00
XRD98L59
DC ELECTRICAL CHARACTERISTICS - XRD98L59 (CONT'D)
Unless otherwise specified: OVDD = DVDD = AV DD = 3.0V, Pixel Rate = 20MSPS, TA = 25°C
Symbol Parameter Min. Typ. Max. Unit Conditions
System Specifications
DNLSSystem DNL -1 +0.75 1.5 LSB No missing codes, monotonic
INLSMIN System INL @ Minimum Gain 2 LSB INL error is dominated by CDS/PGA
linearity
INLSMAX System INL @ Maximum Gain 2 LSB INL error is dominated by CDS/PGA
linearity
en MAXAV Input Referred Noise @ 0.2 mVrms Gain Code = FFh
Max Gain
en MINAV Input Referred Noise @ 0.7 mVrms Gain Code = 00h
Min Gain
Latency Pipeline Delay 4 cycles
Digital Inputs
VIH Digital Input High Voltage 2.1 V
VIL Digital Input Low Voltage 0.5 V
ILDC Leakage Current 5 µAV
IN = GND or VDD
CIN Input Capacitance 5 pF
Digital Outputs
VOH Digital Output High Voltage
OV
DD
-0.5
V While sourcing 2mA
VOL Digital Output Low Voltage 0.5 V While sinking 2mA
IOZ High–Z Leakage -10 10 µA OE = 0 or PD = 1
Output = OGND or ODVDD
XRD98L59
6
Rev. 2.00
DC ELECTRICAL CHARACTERISTICS - XRD98L59 (CONT'D)
Unless otherwise specified: OVDD = DVDD = AVDD = 3.0V, Pixel Rate = 20MSPS, TA = 25°C
Symbol Parameter Min. Typ. Max. Unit Conditions
Digital I/O Timing
tDL Data Valid Delay 2 8 35 ns
tPW1 Pulse Width of SPIX 10 n s
tPW2 Pulse Width of SBLK 1 0 n s
tPIX Pixel Period 50 ns
tBK Sample Black (SBLK), 3.5 n s SBLK Delay = 000
Aperture Delay
tVD Sample Video (SPIX), 2.7 ns SPIX Delay = 000
Aperture Delay
tSCLK Shift Clock Period 100 ns
tSET Shift Register Setup Time 1 0 n s
tHOLD Shift Register Hold Time 0 n s
tL1 Load Set-up Time 1 0 n s
tL2 Load Hold Time 1 0 ns
Power Supplies
AVDD Analog Supply Voltage 2.7 3.0 3.6 V
DVDD Digital Supply Voltage 2.7 3.0 3.6 V Set DVDD = AVDD
OVDD Digital Output Supply Voltage 2.7 3.0 3.6 V OVDD < AVDD
IDD Supply Current 40 55 mA OVDD = AVDD = DVDD =3.0V, Includes
Reference Current
IDDPD Power Down Supply Current 5 25 µA PD = 1, Clocked
7
Rev. 2.00
XRD98L59
CCD
Waveform
VBlack
VVideo CDS Vin
VDark
Figure 2. Definition of terms for VOut of the CCD waveform:
CDSVIN = (V Black - VVideo)
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3
VDD to GND..................................................... +7.0V
VRT & VRB ....................................VDD +0.5 to GND -0.5V
VIN ................................................... VDD +0.5 to GND -0.5V
All Inputs .............................. VDD +0.5 to GND -0.5V
All Outputs............................ VDD +0.5 to GND -0.5V
Storage Temperature ..........................-65°C to 150°C
Lead Temperature (Soldering 10 seconds) .....300°C
Maximum Junction Temperature ....................150°C
Package Power Dissipation Ratings (TA= +70°C)
TSSOP ....................................... GJA = 90°C/W
ESD........................................................ 2000V
Notes:
1Stresses above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode
clamps from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.
3VDD refers to AVDD, OVDD and DVDD. GND refers to AGND, OGND and DGND.
XRD98L59
8
Rev. 2.00
SERIAL INTERFACE
The XRD98L59 uses a three wire serial interface (LOAD,
SDI & SCLK) to access the programmable features and
controls of the chip.The serial interface uses a 12-bit shift
register. The first 4 bits shifted in are the address bits, the
next 8 bits are the data bits. The address bits select
which of the internal registers will receive the 8 data bits.
There is no checking or read back of the address bits to
ensure a valid register is written to. If the address bits
select an undefined register, the data will be discarded.
SCLK
SDI
LOAD
Time
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t1 t2 t12t11
…
t
L1
t
L2
t
SCLK
t
set
t
hold MSB LSB
SERIAL PORT PROCEDURES
1) Set LOAD pin low to enable shift register.
2) Shift in 4 address bits (msb first), followed by
8 data bits (msb first).
3) Set LOAD pin high to transfer data from the
shift register to the serial interface register
array.
For optimum image quality, do not run the serial port
during active video. Serial port clocking can couple into
the signal path and degrade accuracy. Also, do not
continuously run SCLK.
Reseting the XRD98L59 is recommended after initial
power-up. It is generally good practice to reset the
XRD98L59 because the serial data may be forced to an
unknown state during power supply cycling by the digital
ASIC.
Figure 3. Serial Interface Timing Diagram
9
Rev. 2.00
XRD98L59
Re
g
ister Arra
y
SDI
SCLK
LOAD
re
g
ister
select
data input
Address
Decoder
Address BitsData Bits
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3
MSBLSB
Figure 4. Serial Interface Timing Diagram
Address b its Data bits
Reg. Name A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Gain 0 0 0 0 Gain [7:0]
Target Offset 0 0 0 1 Offset [5:0]
Delay 0 0 1 0 SBLK delay [2:0] SPIX delay[2:0] Exar test
Clock 0 0 1 1 RST re
j
Exar te st Clam p opt SBLK pol SPI Xpol Cla m p pol CAL pol
Control 0 1 0 0 Dela
y
test ADCIN PD OE
Calibration 0 1 0 1 Cal Hold Spee d Up DNS 1 DNS 0 Man
DAC
F DA C (m s b) 0 1 1 0 F DA C [ 9:2]
FDAC (lsb) 0 1 1 1 FDAC [1:0]
CDAC 1 0 0 0 CDAC [3:0]
•
•
•Not Us ed
Reset 1 1 1 1 Reset
Table 1. Serial Interface Register Address Map
XRD98L59
10
Rev. 2.00
D7 D6 D5 D4 D3 D2 D1 D0
Gain[7:0]
0 0 0 0 0 0 0 0 minimum gain (6 dB) *
1 1 1 1 1 1 1 1 maximum gain (38 dB)
Table 2. Gain Register bit assignment (Address 0000)
D7 D6 D5 D4 D3 D2 D1 D0
not used not used Offset[5:0]
0 0 0 0 0 0 Do not use (00h)
0 0 0 0 0 1 Do not use (01h)
0 0 0 0 1 0 minimum offset (02h)
1 0 0 0 0 0 default offset (20h) *
1 1 1 1 1 1 maximum offset (3Fh)
Table 3. Target Offset Register bit assignment (Address 0001) for PGA
D7 D6 D5 D4 D3 D2 D1 D0
SBLK delay [2:0] SPIX delay[2:0] Exar test
0 0 0 min delay *0 0 0 min delay *0 0 defaul t
1 1 1 max delay 1 1 1 max delay 01, 10, 11 do not use
Table 4. Delay Register bit assignment (Address 0010)
D7 D6 D5 D4 D3 D2 D1 D0
not used RST rej Exar test CLAMP opt SBLK pol SPIX pol CLAMP pol CAL pol
0 switch ON *0 default 0 Cal only 0 activ e low*0 active low*0 active low*0 active low*
1 clocked 1 do not use 1 Clamp+Cal*1 act ive high 1 active high 1 active high 1 active high
Table 5. Clock Register bit assignment (Address 0011) for SPIX or SBLK
D7 D6 D5 D4 D3 D2 D1 D0
not used not used not used not used Delay test ADCIN PD OE
0 test off *0 test off *0 convert *0 outputs off
1 test on 1 test on 1 power down 1 outputs on *
Table 6. Control Register bit assignment (Address 0100)
Table 7. Calibration Register bit assignment (Address 0101)
D7 D6 D5 D4 D3 D2 D1 D0
not used not used not used Cal Hold Speed Up DNS1 DNS0 Man DAC
0 cal active* 0 Speed Up off 0 DNS off 0 = Wide* 0 automati c*
1 hold valu e 1 Speed Up on* 1 DNS on* 1 = Narrow 1 manual
Note: * Shading indicates default values after power up or reset. The XRD98L59 does not reset the registers to default
va
lue after PD.
11
Rev. 2.00
XRD98L59
Table 8. FDAC (MSB) Register bit assignment (Address 0110)
D7 D6 D5 D4 D3 D2 D1 D0
FDAC[9:2]
1 1 1 1 1 1 1 1 max pos offset
1 0 0 0 0 0 0 0 zero offset
0 0 0 0 0 0 0 0 max neg offset *
D7 D6 D5 D4 D3 D2 D1 D0
not used not used not used not used not used not used FDAC[1:0]
1 1 max pos offset
0 0 max neg of fset *
Table 9. FDAC (LSB) Register bit assignment (Address 0111)
D7 D6 D5 D4 D3 D2 D1 D0
not used not used not used not used CDAC[3:0]
1 1 1 1
1 0 1 1 max pos offset
zero offset +50 mV
0 0 0 0 max ne
g
offse t *-137.5 mV
Table 10. CDAC Register bit assignment (Address 1000)
D7 D6 D5 D4 D3 D2 D1 D0
not used not used not used not used not used not used not used Reset
0 normal *
1 reset chi p
Table 11. Reset Register bit assignment (Address 1111)
Note: * Shading indicates default values after power up or reset. The XRD98L59 does not reset the
registers to default value after PD.
XRD98L59
12
Rev. 2.00
CORRELATED DOUBLE SAMPLE/HOLD (CDS)
The function of the CDS block is to sense the voltage
difference between the black level and video level for
each pixel. The PGA then amplifies this difference to the
desired level for the ADC. The CDS and PGA are fully
differential. The PGA output is converted to a single
ended signal and fed to the ADC. The CCDin pin (CDS
inverting input) should be connected, via a capacitor, to
the CCD output signal. The REFin pin (CDS non-
inverting input) should be connected, via a capacitor, to
the CCD “Common” voltage. This is typically the CCD
Reference output or ground.
At the beginning (or end) of every video line, the DC
restore switch forces one side of the external capacitors
to an internal Vbias1 level (approximately 0.8V). The DC
restore switch is controlled by the combination of the
CLAMP signal ANDed with the φ2 clock. (See Figure 5).
During the black reference phase of each CCD pixel the
φ1 (Sample Black Reference) switches are turned on,
shorting the PGA1 inputs to a second bias level. The
Coarse Offset DAC adds an adjustment to the Vbias2
level to cancel offset in the CCD signal. When the φ1
switches turn off, the pixel black reference(VBLACK) is
sampled on the internal reference sample capacitors,
and the PGA is ready to gain up the CCD video signal.
During the video phase of each CCD pixel the difference
between the pixel black reference level and video level is
transmitted through the internal reference sample ca-
pacitors and converted to a fully differential signal by the
PGA1 amplifier. At this time the φ2 (Sample Pixel value)
switches turn on, and the internal video sample capaci-
tors track the amplified difference.
Figure 5. Block Diagram of CDS and PGAs
φ
1
CLAMP
Vbias1~0.8V
Vbias2
REFin
CCDin
PGA1 PGA2
CCD
Coarse
Offset
DAC
PGACDS
External
DC blockin
g
capacitors
Internal
black sample
capacitors
(
~5PF
)
Reset re
j
ect
switches
Internal
video sample
DC restore
switches
Fine
Offset
DAC
AGND
To ADC
XRD98L59
φ
2
φ
2
capacitors
(
~5PF
)
r
ON
120
Ω
13
Rev. 2.00
XRD98L59
PIXEL TIMING SBLK & SPIX
The timing required by the XRD98L59 to sample indi-
vidual pixel data from a CCD output is shown below in
Figure 6. The diagram shows the general relationship of
timing signals SBLK and SPIX to the CCD waveform.
Figure 6. CDS Timing Diagram - Proper Placement of Timing is
Critical to Image Quality, SDI=0011 0100 1100
*RST REJ is an internally generated signal.
Table 12. Event Table for CDS Timing (SDI=0011 0100 1100)
The XRD98L59 was designed to sample any analog CCD
waveform. In order to do this the timing signals need to
be referenced to the waveform itself, not to the CCD’s
timing generator.
Event Action
↑
RSTREJ Disconnects CDS Inputs from Reset Noise
↓
RSTREJ Connects CDS Inputs
SBLK High Sample Black Level
SPIX High Sample Video Level
SBLK/SPIX Low Hold Video and Black Level
1
2
3
4
5
SBLK
SPIX
CCD
IN
RST REJ*
pixel black level
sample point pixel video level
sample point
t
BK
t
VD
t
RST
Switch
Open
Reset
Pulse
Reset
Phase Black
Reference
Phase Video
Phase
122
3
4
3
455
1
Reset
Reject
Reset
Reject
Switch
Closed
Pixel N Pixel N + 1
N-3N-4
DB[9:0]
t
PIX
t
PW1
t
PW2
t
DL
t
DL
XRD98L59
14
Rev. 2.00
RSTREJ reduces CCD reset noise by disconnecting the
input of the XRD98L59 from the CCD during the CCD
reset pulse. RSTREJ is an internally generated signal.
RSTREJ disconnects the input after the SPIX and before
the SBLK sampling events to reject CCD reset noise.
The RSTREJ switch is always closed (the input is always
connected) if D6=0 in the clock register (address 0011)
of the serial port.
For the timing example shown in Figure 6, SBLK high
samples the pixel black level. The actual hold point of
the pixel black level occurs after a delay of tBK. tBK is
the aperture delay of the SBLK timing signal.
The polarities of the SBLK and SPIX signals are indepen-
dently programmable via the serial port.
For the timing example shown in Figure 6, SPIX high
samples the pixel video level. The actual hold point of
the pixel video level occurs after a delay of tVD. tVD is
the aperture delay of the SPIX timing signal. The
polarity of the SPIX signal is serial port programmable.
The function of the CDS block, shown in Figure 7, is to
sense the voltage difference between the black level and
video level for each pixel. The CDS and PGA are fully
differential to reject common mode noise. The PGA
output is converted to a single ended signal, and then fed
to the ADC.
REFIN (CDS non-inverting input) should be connected,
via a capacitor, to the CCD “Common” voltage. This is
typically CCD ground. CCDIN (CDS inverting input)
should be connected, via a capacitor, to the CCD output
signal. The external coupling capacitors on CCDIN and
REFIN should be of equal values to minimize gain errors
(typically 0.01µf +/-10%).
Figure 7. Block Diagram of the CDS, Reset Phase: RSTREJ Switch is Open
+
PGA1
-
Vbias1 ~0.8
External
Coupling
Capacitors
VBIAS2
CLAMP
φ
1
Gain
Register
to ADC
C
C
DGND
Vout C1
C2
C3
+
PGA2
-
+BUF
-
C4
φ
2
RSTREJ
15
Rev. 2.00
XRD98L59
During the video phase of each pixel the φ2 switches are
closed when SPIX is active. The difference between the
pixel black reference level and video level is transmitted
through capacitors C1 & C2. Differential amplifier PGA1
+
PGA1
-
Vbias1 ~0.8
External
Coupling
Capacitors
VBIAS2
CLAMP
In_Pos
In_Neg
Gain
Register
to ADC
C
C
DGND
Vout C1
C2
C3
+
PGA2
-
+
BUF
-
C4
φ
1
φ
2
RSTREJ
+
PGA1
-
Vbias1~0.8
External
Coupling
Capacitors
VBIAS2
CLAMP
Gain
Register
to ADC
C
C
DGND
Vout C1
C2
C3
+
PGA2
-
+BUF
-
C4
φ
1
φ
2
RSTREJ
Figure 9. CDS - Video Phase: φφ
φφ
φ1 Switches Open, φφ
φφ
φ2 and RSTREJ Switches Closed
During the black reference phase of each pixel the
RSTREJ switches are closed, allowing the difference
between the black reference level voltage and VBIAS2
to develop across capacitors C1 and C2 (see Figure 8).
φ1 is closed when SBLK is active.
Figure 8. CDS - Black Reference Phase: RSTREJ and φφ
φφ
φ1 Switch Closed
amplifies both CDS inputs from CCDIN and REFIN. The
inactive phase of SPIX turns off the φ2 switches, storing
the differential pixel value on capacitors C3 & C4 (see
Figure 9).
During the reset phase of each pixel the RSTREJ
switches are turned off, see Figure 7, opening the
XRD98L59 CDS input. This is done to limit reset pulse
transients seen by the front end of the XRD98L59.
XRD98L59
16
Rev. 2.00
Figure 10. Timing Diagram of the CDS Clocks and Internal Signals (RSTREJ, φφ
φφ
φ1, ,
, ,
, φφ
φφ
φ2, ADCCLK))
))
)
SDI = 0011 0100 1100
* Digital Output Data is Updated on the Falling Edge of φφ
φφ
φ2.
This Update Position is Affected by the Aperture Delay of φφ
φφ
φ2.
Note: Aperture Delay is not Shown
CCD
RSTREJ
SBLK
SPIX
φ
1
φ
2
(Internal Signals)
ADCLK
HOLD TRACK
Reset
Phase
Black
Reference
Phase Video
Phase
DB[9:0]*
17
Rev. 2.00
XRD98L59
D4 D3 D2 φφ
φφ
φ2 Aperture Delay
0 0 0 2.7ns (default)
0 0 1 4.7ns
0 1 0 6.7ns
0 1 1 8.7ns
1 0 0 10.7ns
1 0 1 12.7ns
1 1 0 14.7ns
1 1 1 16.7ns
Table 14. Programmable φφ
φφ
φ2 Delays
D7 D6 D5 φφ
φφ
φ1 Aperture Delay
0 0 0 3.5ns (default)
0 0 1 5.5ns
0 1 0 7.5ns
0 1 1 9.5ns
1 0 0 11.5ns
1 0 1 13.5ns
1 1 0 15.5ns
1 1 1 17.5ns
Table 13. Programmable
φφ
φφ
φ1 Delays
SBLK and SPIX Programmable Aperture Delay
(SDI Address = 0010)
The positioning of φ1 and φ2 from Figure 10, are opti-
mized by using a programmable aperture delay function.
φ1 and φ2 are delayed internally by the amount specified
in the serial port. SBLK delay (D7:D5) delays the φ1
clock and SPIX delay (D4:D2) delays the φ2 clock. The
delay is 2ns per lsb. The aperture delays tBK and tVD are
added to the programmable aperture delay to determine
final positioning. The tables below include the tBK and tVD
aperture delays.
The aperture delay of φ2 also delays the output data bus
DB[9:0]. Digital output data is updated on the falling
edge of φ2 as shown in Figure 10. Data is valid after tDL
plus the change in φ2 aperture delay. For example, if
D[4:2] equals 001b, then data is valid at tDL + 2ns. (tDL
is shown in Figure 6).
XRD98L59
18
Rev. 2.00
Figure 11. End of Line OB Pixels Used for
Line Calibration Mode on a Typical CCD Array
Active Pixels
End of LIne
OB
Calibration
Pixels
LINE CALIBRATION MODE
Line calibration mode calibrates during the OB pixel
output from the CCD at the end of every line. Figure 11,
shows the outline of a typical CCD area array. The
active (white) pixels are shown with the OB (shaded)
pixels around the edges. The OB pixels used in line
calibration are identified below in Figure 11 as the dark
shaded OB pixels on the right hand side of the array.
Line Timing: CLAMP and CAL
CLAMP & CAL Line Timing
(SDI address = 0011, D4 = 1)
The timing needed for Line Calibration Mode is shown in
Figure 12. The timing signal CAL gates the XRD98L59’s
auto-calibration logic. CAL is active during the end of
line OB pixels.
Most timing generators (TG’s) have signals that define
the start of line and end of line OB pixels on the CCD
array. CAL should always be active on start or the end
of line that defines the greatest number of OB pixels
possible. The more OB pixels that the XRD98L59 can
use for its auto-calibration, the faster it can achieve and
maintain calibration. CAL and CLAMP must never be
active at the same time. CLAMP is used to set the
input DC bias voltage. (See Figure 5).
19
Rev. 2.00
XRD98L59
Figure 12. Example of CLAMP & CAL Line Calibration Mode Timing
(CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 0001 0011
Line N Line N+1
* Note: OB = Optically Black or Shielded pixels.
Active Video
pixels OB* pixels Vertical Shift Dummy &
OB* pixels
CAL
CLAMP
CCD Signal
Active Video
pixels
(Horizontal Clocking
Off)
Min 1 Pixel
Min 1 Pixel
Line Timing: CAL Only
CAL Only Line Timing
(SDI address = 0011, D4 = 0)
The timing needed for "CAL Only" Line Calibration Mode
is shown in Figure 13. In "CAL Only" Line Calibration the
timing signal CAL has two functions, DC Clamping of the
CCDIN and REFin inputs and gating the auto-calibration
logic. Using "CAL Only" Line Timing enables the de-
signer to eliminate the requirement of providing a
CLAMP Timing signal to the XRD98L59.
XRD98L59
20
Rev. 2.00
Most timing generators (TG’s) define the start of line and
end of line OB pixels on the CCD array. The CAL timing
signal should always be active for the greatest number of
OB pixels possible, either during start or end of line. The
more OB pixels that the XRD98L59 can use for its auto-
calibration, the faster it can achieve and maintain calibra-
tion.
While in “CAL ONLY” Line Calibration Timing Mode,
CLAMP needs to be held inactive during the output of
active video and OB pixels from the CCD. Figure 13
shows the minimum timing requirements for the “CAL
ONLY” Line Calibration Timing Mode. The inactive
state for CLAMP depends on the CLAMP-Polarity
setting (Clock Reg bit D1).
End of Line N Start of Line N+1
Active Video
Pixels OB Pixels Vertical Shift
Dummy &
OB Pixels
CAL
Internal
DC Restore Time
CCD
Si
g
nal
Active Video Pixels
t
CAL
(min 5 Pixels)
4 Pixels
(D1 = 0)
CLAMP
Internal Black Level
Calibration Time
t
CAL
- 4 Pixels
Figure 13. Example of Minimum Timing Requirements for CAL Only Line Calibration Mode
(CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 0000 0000
Vertical Shift Reject
The CLAMP input can be used to implement a Vertical
Shift Reject function while in “CAL ONLY” Line Cali-
bration Timing Mode. The Vertical Shift Rejection,
also called preblanking, can be used to reject and any
large transients present in the CCD output during the
vertical clocking.
To implement the Vertical Shift Reject (Preblanking)
function on the XRD98L59 the CLAMP opt bit must be
low (Clock Reg D4=0) and the CLAMP input driven
with the preblanking timing signal. The preblanking
timing signal, commonly called PBLK, is generated by
the system timing generator and defines the vertical
shift of the CCD (see Figure 13a). The preblanking
pulse opens the Reset Reject Switches internal to the
XRD98L59, see Figure 5, thereby rejecting any
transients in the CCD output while the vertical shifting
is being done.
21
Rev. 2.00
XRD98L59
End of Line N Start of Line N+1
Active Video
Pixels OB Pixels Vertical Shift
Dummy &
OB Pixels
CAL
Internal
DC Restore Time
CCD
Si
g
nal
Active Video Pixels
t
CAL
(min 5 Pixels)
4 Pixels
(D1 = 0)
CLAMP
Internal Black Level
Calibration Time
t
CAL
- 4 Pixels
Figure 13a. Example of Vertical Shift Reject Timing using the CLAMP input while in “CAL ONLY”
Line Calibration Mode. (CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 000 0000
÷
ø
ö
ç
è
æ´+= 32
256
6][ Code
dBGain
PROGRAMMABLE GAIN AMPLIFIER (PGA)
PGA1 provides gains of 0dB, 8dB & 16dB (1x, 2.5x, and
6.25x). The gain transitions occur at PGA gain codes 64d
and 128d (40h & 80h). PGA2 provides gain from 6dB to
22dB (2x to 12.5x) with 0.125dB steps. The combined
PGA blocks provide a programmable gain range of 32dB.
The minimum gain (code 00h) is 6dB. The maximum gain
(code FFh) is 38dB. The following equation can be used
to compute PGA gain from the gain code:
where
Code
is the 8 bit value (0 to 255) programmed in
the serial interface Gain register. Due to device
mismatch the gain steps at codes 63 - 64 and 127 -
128 may not be monotonic.
ANALOG TO DIGITAL CONVERTER (ADC)
The analog-to-digital converter is based upon a two-step
sub-ranging flash converter architecture with a built in
track and hold input stage. The ADC conversion is
controlled by an internally generated signal, ADCLK (see
Figure 10). The ADC tracks the output of the PGA while
ADCLK is high and holds when ADCLK is low. This allows
maximum time for the PGA output to settle to its final
value before being sampled. The conversion is then
performed and the parallel output is updated, after a 2.5
cycle pipeline delay, on the edge of φ2. The pipeline delay
of the entire XRD98L59 is 4 clock cycles.
The ADC reference levels, VRT & VRB, are set by an
internal resistor divider between VDD and GND. The
divider provides VRB=VDD/10 and VRT=VDD/1.3. To
maximize the performance of the XRD98L59, VRT &
VRB should have high frequency by-pass capacitors to
AGND. The value of these by-pass capacitors will affect
the time required for the reference to charge up and settle
after power down mode. Using 0.01uF capacitors will
give about 40 µs settling time for full accuracy.
The ADC output bus is equipped with a high impedance
capability which is controlled by OE bit in the serial
interface control register. The outputs are enabled when
the OE bit is high, and go into high impedance mode when
the OE bit is low.
XRD98L59
22
Rev. 2.00
The ADC input node can be accesed for test purposes
using the ADCIN mode (SDI address 0100). Use the
following procedure to enable the ADCIN mode:
1) In the Serial interface Clock register, set the
Clamp Opt bit low (D4).
2) In the Serial interface Control register, set the
ADCIN bit high (D2).
3) Clock SBLK & SPIX to generate internal
ADC_CLK signal.
4) Apply ADC input signal to CCDin.
In this test mode the analog signal, Vin, applied to CCDin
pin will be converted by the ADC. The ADC output code
is related to Vin by the following rules:
1) For Vin < VRB, ADC output code = 0,
2) For Vin > VRT, ADC output code = 1023,
3 ) For VRB < Vin < VRT, ADC output code = 1024
x (Vin - VRB) / (VRT - VRB)
CONTROL & RESET REGISTERS
ADCIN Bit
This bit activates a switch that connects CCDin directly
to the ADC input. In this mode, the PGA output is
disabled. See the ADC section for details.
PD Bit (Power Down)
This bit is used to put the chip in the Power Down mode.
It has the same effect as the PD pin. When the PD bit
is high the chip will go into the power down mode, all
conversions stop. When the PD bit is low the chip is in
its normal active mode. In the Power Down mode the
digital output pins are forced to the high impedance mode
and the ADC reference is disconnected. The serial
interface pins remain active in the Power Down mode.
OE Bit (Output Enable)
The ADC digital output bus is equipped with a high
impedance capability. When the OE bit is high the digital
outputs are enabled (active). When the OE bit is low the
digital outputs are in the high impedance mode (not
active). The OE bit only controls the digital output
drivers, all other circuits on the chip will remain active.
RESET Bit
This bit is used to reset all internal registers to default
values. This includes all the serial interface registers as
well as the registers in the calibration logic. To reset the
chip write a “1” to the reset bit. The reset bit will clear itself
after an internal delay, so there is no need to write a “0”
to the reset bit. The chip also has a Power-On-Reset
function (POR) so it will always power up with default
values in all registers. It is recommended that the
XRD98L59 be reset after power is cycled to avoid loading
potentially incorrect serial port data from other ASICs in
the system.
23
Rev. 2.00
XRD98L59
BLACK LEVEL OFFSET CALIBRATION
CDS 10-bit ADC
Hot Pixel
Clipper
Pixel
Averager
+
Coarse
Accumulator Fine
Accumulator
Offset Calibration Logic
10
2/)
Reg
2/)
CalHold, SpeedUp
Target Offset Code
Gain Code
DB[9:0]
4-bit 10-bit
+10
Black Level
Offset Calibration
Loop
DNS
ManDAC
CDAC, FDAC
From Serial
Interface
Registers
CCD
Signal
CDAC FDAC
DNS
Filter
-
+
+
Figure 15. Black Level Offset Calibration Block Diagram
To get the maximum color resolution and dynamic range,
the XRD98L59 uses a digitally controlled feedback cir-
cuit to correct for offset in the CCD signal as well as offset
in the CDS, PGA & ADC signal path. This calibration is
done while the CCD outputs Optical Black (OB) pixels.
The CAL input signal is used to define when the CCD
output contains OB pixels. The calibration logic will take
into account the internal pipeline delay.
XRD98L59
24
Rev. 2.00
Hot Pixel Clipper
CCD’s occasionally have hot pixels. These are defective
pixels which always output a bright level. To ensure the
Black Level is not significantly affected by hot pixels in
the OB area, the Hot Pixel Clipper limits pixel data from
the ADC to a maximum value of 127 (7Fh). The Hot Pixel
Clipper is only active when CAL is active. This clipping
only affects the data used by the internal calibration
logic. Data on the digital output bus DB[9:0] is not
clipped.
Pixel Averager
After the clipper, the logic takes the average of the
Optical Black pixels defined by CAL. This averaging
function filters noise.
Offset Difference Using the Target Offset Register
The Target Offset register (Address 0001) value (6 lsb’s)
is subtracted from the OB pixel average. If the difference
is positive, the offset DACs are decremented to reduce
the effective ADC output code. If the difference is
negative, the offset DACs are adjusted to increase the
effective ADC output code. The amount of adjustment is
shown in Figure 16.
Set the Target Offset Register value equal to the desired
black level output code. For example: Set Target Offset
Register to code 32 and black CCD outputs are nominally
output as 32. Default is code 32 decimal.
Coarse & Fine Accumulators
The Coarse and Fine Accumulators are the registers
which hold the digital codes for the Coarse and Fine
Offset DACs. The Offset DAC adjustments are made by
adding or subtracting to the value in the Fine Accumula-
tor. If there is an overflow or underflow in the Fine
Accumulator, the Fine Accumulator is reset to it’s mid-
scale value, and the Coarse Accumulator is incremented
or decremented accordingly.
CALIBRATION OPTIONS
Speed Up Mode
The purpose of this option is to reduce the amount of time
required for initial convergence of the calibration feed-
back system. The feedback system is designed to have
a slow response time to avoid introducing image arti-
facts. The slow response time is achieved by limiting the
Fine accumulator changes to ± 1 count at a time. The
Speed Up option maintains this slow response while the
difference between the averaged ADC data and the
Target Offset Code is small. But when the difference is
larger than ± 32 lsb’s the Fine accumulator takes large
steps. The actual step size depends on the Gain code,
and is set such that the step will cause no more than a
32 LSB change in the ADC output.
To activate the Speed Up mode write a 1 to the SpeedUp
bit in the Calibration register (bit D3 of Serial Interface
Register #5). By default the SpeedUp mode is active.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 64 128 192 256
PGA Co d e
ADC LSB
s
VDD = 3. 0V
Figure 16. XRD98L59 Offset DAC Step Size in
ADC Output LSBs
25
Rev. 2.00
XRD98L59
Digital Noise Supression (DNS Filter)
To activate the DNS mode, a "1" is written to DNS1 bit in
the Calibration register (bit D2 of Serial Interface Register
#5). By default the DNS mode is active.
In DNS mode, the user has the option to select narrow
band or wide band Noise Suppression Filters by setting
DNS0 bit to a "1" (narrow) or "0" (wide) respectively. Best
performance is achieved by setting DNS1 = "1" and
DNS0 = "0".
Hold Mode
The purpose of this mode is to prevent any changes in the
Fine or Coarse accumulators. The idea is to first run the
calibration normaly so the Fine and Coarse accumulators
converge on the programmed Target Offset Code. Then,
just before acquiring the final image data, activate the
Hold mode. This will ensure the black level offset of the
CDS/PGA does not change while the final image is being
transferred out of the CCD. Once the image has been
acquired from the CCD, turn off the Hold mode so the chip
can continue to compensate for any changes in offset
due to temperature drift or other effects.
To activate the Hold mode write a 1 to the CAL Hold bit
in the Calibration register (bit D4 of Serial Interface
Register #5). By default the Hold mode is not active.
Manual Mode
The purpose of this mode is to disable the automatic
calibration feature. In the Manual mode, the Coarse
accumulator is programmed by writing to the CDAC
register, the Fine accumulator is programmed by writing
to the FDAC register. The Fine accumulator is a 10 bit
register, but the Serial interface registers are only 8 bits
wide. As shown in the Serial Interface Register Address
Map, two serial interface registers are concatenated to
provide 10 bits to the Fine accumulator.
To activate the Manual mode write a 1 to the ManDAC bit
in the Calibration register (bit D0 of Serial Interface
Register #5). By default the Manual mode is not active.
XRD98L59
26
Rev. 2.00
AV
DD
4-6 3
3
Timing
Generator
V
Driver
CCD
5-10Ω
0.01µF
0.01µF
0.1µF
0.1µF
12V
CLOB
CLDM
SHD
SHP
Serial Ports
ASIC/DSP
10-Bit Digital
Video Input
XRD98L59
SPIX
CAL
CLAMP
12
11
10
9
8
7
4
6
5
15
16
18
19
20
21
22
23
24
14
25
28
CCDin
REFin
AGND
VRB
DB7
DB8
DB9
OVDD
DB6
DB5
DVDD
VRT
SCLK
LOAD
SDI
PD
DGND
AVDD
SBLK
DB1
DB0
DB2
DB3
DB4
OGND
27
26
17
13
1
2
3
AV
DD
AV
DD
Figure 17. Application Diagram; ASIC with External Timing Generator
27
Rev. 2.00
XRD98L59
AVDD
AVDD
4-6 3
V
Driver
CCD 5-10Ω0.01µF
0.01µF
0.1µF
0.1µF
12V
Serial Port
ASIC/DSP
10-Bit Digital
Video Input
XRD98L59
SPIX
CAL
CLAMP
1
12
11
10
9
8
7
4
6
5
15
16
18
19
20
21
22
23
24
14
25
28
CCDin
REFin
AGND
VRB
DB7
DB8
DB9
OVDD
DB6
DB5
DVDD
VRT
SCLK
LOAD
SDI
PD
DGND
AVDD
SBLK
DB1
DB0
DB2
DB3
DB4
OGND
27
26
17
13
Intenal Timing
Generator
3
2
AVDD
Figure 18. Application Diagram; ASIC with Internal Timing Generator
XRD98L59
28
Rev. 2.00
Figure 19. PGA Gain vs. Gain Code
Gain Code
PGA Gain (dB)
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
40 20 40 60 80 100 120 160 180 200 220 240 255140
29
Rev. 2.00
XRD98L59
30
32
34
36
38
40
42
44
46
0 2 4 6 8 10121416182022242628
Sampling Frequency (MHz)
IDD (AVDD + DVDD) (mA)
VDD = 3.0V
Figure 20. IDD vs Sample Rate
XRD98L59
30
Rev. 2.00
30
35
40
45
50
55
60
65
70
0 63 64 127 128 255
Gain C ode
SNR (dB
)
Figure 21. Typical SNR vs Gain at 20MHz Sample Rate
SNR = 20 log (Full scale voltage/rms noise)
31
Rev. 2.00
XRD98L59
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1024
CODE
LSB
Figure 22. ADC Only DNL
XRD98L59
32
Rev. 2.00
Figure 23. XRD98L59 1.45 Mpixel Camera Reference Schematic (Sheet 1)
33
Rev. 2.00
XRD98L59
Figure 24. XRD98L59 1.45 Mpixel Camera Reference Schematic (Sheet 2)
XRD98L59
34
Rev. 2.00
Figure 25. XRD98L59 2.31 Mpixel Camera Reference Schematic (Sheet 1)
35
Rev. 2.00
XRD98L59
Figure 26. XRD98L59 2.31 Mpixel Camera Reference Schematic (Sheet 2)
XRD98L59
36
Rev. 2.00
28 LEAD THIN SHRINK SMALL OUTLINE
(4.4mm TSSOP)
Rev. 2.00
e
D
E H
BA
1
Seating
Plane
28 15
14
1
A
L
C
α
SYMBOL MIN MAX MIN MAX
A 0.033 0.047 0.85 1.20
A1 0.002 0.006 0.05 0.15
A2 0.031 0.041 0.80 1.05
B 0.007 0.012 0.19 0.30
C 0.004 0.008 0.09 0.20
D 0.378 0.386 9.60 9.80
E 0.169 0.177 4.30 4.50
e 0.0256 BSC 0.65 BSC
H 0.248 0.256 6.30 6.50
L 0.018 0.030 0.45 0.75
α0°8°0°8°
MILLIMETERSINCHES
Note:
The control dimension is in millimeter column
A
2
37
Rev. 2.00
XRD98L59
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a
user’s specific application. While the information in this publication has been carefully checked; no responsibility,
however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect
its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives,
in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes
all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2001 EXAR Corporation
Datasheet January 2001
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
