©2011 Silicon Storage Technology, Inc. DS25034A 09/11
8
4 Mbit (x16) Multi-Purpose Flash
SST39WF400B
Data Sheet
Microchip Technology Company
Write Operation Status Detection
To optimize the system write cycle time, the SST39WF400B provides two software means to detect the
completion of a Program or Erase write cycle. The software detection includes two status bits—Data#
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge
of WE#, which initiates the internal Program or Erase operation.
The completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may occur simultaneously with the completion of the Write cycle. If this
occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7
or DQ6. To prevent spurious rejection in the event of an erroneous result, the software routine must
include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then
the device has completed the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39WF400B is in the internal Program operation, any attempt to read DQ7will produce
the complement of the true data. Once the Program operation is complete, DQ7will produce true data.
Although DQ7may have valid data immediately following the completion of an internal Write operation,
the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subse-
quent successive Read cycles after an interval of 1 µs.During an internal Erase operation, any attempt
to read DQ7will produce a ‘0’. Once the internal Erase operation is complete, DQ7will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 8 for Data# Polling timing diagram and Figure 19 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce
alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’.
When the Program or Erase operation is complete, the DQ6bit will stop toggling and the device is
ready for the next operation.
The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse.
See Figure 9 for Toggle Bit timing diagram and Figure 19 for a flowchart.
Data Protection
The SST39WF400B provides both hardware and software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.