PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you e valuate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 20380 Rev: BAmendment/0
Issue Date: April 1997
5.0 V-only Flash
Am29F400AT/Am29F400AB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
■
5.0 V
±
10% for read and write operations
— Minimizes system level power requirements
■
Compatible with JEDEC-standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■
Package options
— 44-pin SO
— 48-pin TSOP
■
Minimum 100,000 write/erase c ycles guaranteed
■
High performance
— 60 ns maximum access time
■
Sector erase architecture
— One 16 Kbyte, tw o 8 Kb ytes , one 32 Kbyte, and
seven 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
■
Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
■
Embedded Erase
Algorithms
— Automatically preprograms and erases the chip
or any sector
■
Embedded Program
Algorithms
— Automatically programs and verifies data at
specified address
■
Data P olling and T oggle Bit feature f or detection
of program or erase cycle completion
■
Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
■
Erase Suspend/Resume
— Supports reading data from a sector not being
erased
■
Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
■
Enhanced power management for standby
mode
—1
µ
A typical standby current
■
Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
■
Hardware RESET pin
— Resets internal state machine to the read mode
GENERAL DESCRIPTION
The Am29F400A is a 4 Mbit, 5.0 V olt-only Flash memory
organized as 512 Kbytes of 8 bits each or 256 Kwords
of 16 bits each. The 4 Mbits of data is divided into 11
sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte,
and seven 64 Kbytes, for flexible erase capability. The
8 bits of data will appear on DQ0–DQ7 or 16 bits on
DQ0–DQ15. The Am29F400A is offered in 44-pin SO
and 48-pin TSOP packages. This device is designed
to be programmed in-system with the standard system
5.0 Volt V
CC
supply. 12.0 Volt V
PP
is not required for
program or erase operations. The de vice can also be re-
programmed in standard EPROM programmers.
The standard Am29F400A offers access times of
60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has sepa-
rate chip enab le (CE), write enable (WE) and output
enable (OE) controls.
The Am29F400A is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine
which controls the erase and programming circuitry.
2 Am29F400AT/Am29F400AB
PRELIMINARY
Write cycles also inter nally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.
The Am29F400A is programmed by ex ecuting the pro-
gram command sequence . This will in vok e the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase, the de vice automat-
ically times the erase pulse widths and verifies proper
cell margin.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F400A is erased when
shipped from the factory.
The Am29F400A de vice also f eatures hardw are sector
protection. This feature will disable both program and
erase operations in any combination of eleven sectors
of memory.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from a sector that was not being
erased. Thus, true backg round erase can be achie ved.
The device features single 5.0 Volt power supply oper-
ation for both read and write functions. Internally gen-
erated and regulated voltages are provided for the
program and erase operations. A low V
CC
detector au-
tomatically inhibits write operations during power tran-
sitions. The end of program or er ase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the de vice automatically resets to the
read mode.
The Am29F400A also has a hardware RESET pin.
When this pin is driven low, execution of any Embed-
ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29F400A memory electrically erases all
bits within a sector simultaneously via
F owler-Nordhiem tunneling. The bytes/words are pro-
grammed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
Flexible Sector-Erase Architecture
■
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbyte sectors
■
Individual-sector or multiple-sector erase capability
■
Sector protection is user definable
Am29F400AT Sector Architecture
Am29F400AB Sector Architecture
16 Kbyte
8 Kbyte
8 Kbyte
32 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
20380B-1
7FFFFh 3FFFFh
7BFFFh 3DFFFh
79FFFh 3CFFFh
77FFFh 3BFFFh
6FFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
00000h 00000h
(x8) (x16)
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
20380B-2
7FFFFh 3FFFFh
6BFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
07FFFh 03FFFh
05FFFh 02FFFh
03FFFh 01FFFh
00000h 00000h
(x8) (x16)
Am29F400AT/Am29F400AB 3
PRELIMINARY
5.0 V-only Flash
PRODUCT SELECTOR GUIDE
BLOCK DIAGRAM
Family Part No: Am29F400A
Ordering Part No:V
CC
= 5.0 V
±
5
%
-65
V
CC
= 5.0 V
±
10%
-70 -90 -120 -150
Max Access Time (ns) 60 70 90 120 150
CE (E) Access (ns) 60 70 90 120 150
OE (G) Access (ns) 30 30 35 50 55
Erase Voltage
Generator Input/Output
Buffers
Data
Latch
Y-Gating
Cell MatrixX-Decoder
Y-Decoder
Address Latch
Chip Enable
Output Enable
Logic
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
WE
CE
OE
A0-A17
STB
STB
DQ0–DQ15
RY/BY
Buffer RY/BY
BYTE
RESET
A-1
VCC
VSS
20380B-3
4 Am29F400AT/Am29F400AB
PRELIMINARY
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO
20380B-4
NC
RY/BY
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Am29F400AT/Am29F400AB 5
PRELIMINARY
5.0 V-only Flash
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A1
A17
A7
A6
A5
A4
A3
A2
Standard TSOP 20380B-5
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A16
DQ2
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A1
A17
A7
A6
A5
A4
A3
A2
Reverse TSOP 20380B-6
6 Am29F400AT/Am29F400AB
PRELIMINARY
PIN CONFIGURATION
A1, A0–A17 = 18 Addresses
BYTE = Selects 8-bit or 16-bit mode
CE = Chip Enable
DQ0–DQ15 = 16 Data Inputs/Outputs
NC = Pin Not Connected Internally
OE = Output Enable
RESET = Hardware Reset Pin, Active Low
RY/BY = Ready/Busy Output
V
SS
= +5.0 Volt Single-P o wer Supply
(
±
10% for -90, -120, -150) or (
±
5% for -75)
V
SS
= Device Ground
WE = Write Enable
LOGIC SYMBOL
18
16 or 8
DQ0–DQ15
A0–A17
CE (E)
OE (G)
WE (W)
A-1
RY/BY
RESET
BYTE
20380B-7
Am29F400AT/Am29F400AB 7
PRELIMINARY
5.0 V-only Flash
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific v alid combinations and
to check on newly released combinations.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
DEVICE NUMBER/DESCRIPTION
Am29F400A
4 Megabit (512K x 8-Bit/256K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
AM29F400A -65 E C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
B
SPEED OPTION
See Product Selector Guide and
Valid Combinations
T
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
Valid Combinations
AM29F400AT/B-65 EC, EI, FC, FI, SC, SI
AM29F400AT/B-70
EC, EI, EE, EEB,
FC, FI, FE, FEB,
SC, SI, SE, SEB
AM29F400AT/B-90
AM29F400AT/B-120
AM29F400AT/B-150
8 Am29F400AT/Am29F400AB
PRELIMINARY
Table 1. Am29F400A User Bus Operations (BYTE = V
IH
)
Table 2. Am29F400A User Bus Operations (BYTE = V
IL
)
Legend:
L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels.
Notes:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
2. Refer to the section on Sector Protection.
Read Mode
The Am29F400A has two control functions which must
be satisfied in order to obtain data at the outputs. CE is
the power control and should be used for device selec-
tion. OE is the output control and should be used to
gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses
and stable CE to valid data at the output pins.
The output enable access time is the delay from the
falling edge of OE to valid data at the output pins (as-
suming the addresses have been stable for at least
t
ACC
-t
OE
time).
Standby Mode
There are two wa ys to implement the standb y mode on
the Am29F400A device, both using the CE pin.
A CMOS standby mode is achieved with the CE input
held at V
CC
±
0.5 V. Under this condition the current is
typically reduced to less than 5
µ
A. A TTL standby
mode is achieved with the CE pin held at V
IH
. Under
this condition the current is typically reduced to 1 mA.
In the standby mode the outputs are in the high imped-
ance state, independent of the OE input.
Operation CE OE WE A0 A1 A6 A9 DQ0–DQ15 RESET
Autoselect, AMD Manuf. Code (Note 1) L L H L L L V
ID
Code H
Autoselect Device Code (Note 1) L L H H L L V
ID
Code H
Read L L H A0 A1 A6 A9 D
OUT
H
Standby H XXXXXXHIGH Z H
Output Disable L H H XXXXHIGH Z H
Write L H L A0 A1 A6 A9 D
IN
H
Verify Sector Protect (Note 2) L LHLHLV
ID
Code H
Temporary Sector Unprotect XXXXXXX X V
ID
Hardware Reset XXXXXXXHIGH Z L
Operation CE OE WE A0 A1 A6 A9 DQ0–DQ7 DQ8–DQ15 RESET
Autoselect, AMD Manuf. Code
(Note 1) LLHLLLV
ID
Code HIGH Z H
Autoselect Device Code (Note 1) L L H H L L V
ID
Code HIGH Z H
Read L L H A0 A1 A6 A9 DOUT HIGH Z H
Standby H XXXXXXHIGH Z HIGH Z H
Output Disable L H H XXXXHIGH Z HIGH Z H
Write L H L A0 A1 A6 A9 DIN HIGH Z H
Verify Sector Protect (Note 2) L LHLHLV
ID Code HIGH Z H
Temporary Sector Unprotect XXXXXXX X HIGH Z VID
Hardware Reset XXXXXXXHIGH Z HIGH Z L
Am29F400AT/Am29F400AB 9
PRELIMINARY
5.0 V-only Flash
Output Disable
With the OE input at a logic high level (VIH), output from
the de vice is disabled. This will cause the output pins to
be in a high impedance state.
Autoselect
The autoselect mode allows the reading of a binary
code from the device and will identify its manufacturer
and type. This mode is intended for use by program-
ming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.
To activate this mode, the programming equipment
must force VID (11.5 V to 12.5 V) on address pin A9.
Two identifier bytes may then be sequenced from the
device outputs by toggling address A0 from VIL to VIH.
All addresses are don’t cares except A0, A1, and A6
(see Table 3).
The manufacturer and device codes may also be read
via the command register, for instances when the
Am29F400A is erased or programmed in a system
without access to high voltage on the A9 pin. The com-
mand sequence is illustrated in Table 4 (see A utoselect
Command Sequence).
Byte 0 (A0 = VIL) represents the manufacturer’s code
(AMD=01H) and byte 1 (A0 = VIH) the device identifier
code (Am29F400AT = 23H and Am29F400AB = ABH
f or x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode). These two bytes/words are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as
the parity bit. In order to read the proper device codes
when executing the Autoselect, A1 must be VIL
(see Tables 3 and 4).
The autoselect mode also facilitates the deter mination
of sector protection in the system. By perf orming a read
operation at the address location XX02H with the
higher order address bits A12–A17 set to the desired
sector address, the device will return 01H for a pro-
tected sector and 00H for a non-protected sector.
Table 3. Am29F400A Sector Protection Verify Autoselect Codes
*Outputs 01H at protected sector addresses
Table 4. Expanded Autoselect Code Table
B) - Byte mode
(W) - Word mode
Type A12-A17 A6 A1 A0 Code (HEX)
Manufacturer Code-AMD X VIL VIL VIL 01H
Am29F400A Device
Am29F400AT Byte XV
IL VIL VIH 23H
Word 2223H
Am29F400AB Byte XV
IL VIL VIH ABH
Word 22ABH
Sector Protection Sector
Address VIL VIH VIL 01H*
Type Code DQ
15 DQ
14 DQ
13 DQ
12 DQ
11 DQ
10 DQ
9DQ
8DQ
7DQ
6DQ
5DQ
4DQ
3DQ
2DQ
1DQ
0
Manufacturer Code-AMD 01H 0000000000000001
Am29F400A
Device
Am29F400AT(B)
(W) 23H
2223H A-1
0HI-Z
0HI-Z
1HI-Z
0HI-Z
0HI-Z
0HI-Z
1HI-Z
00
00
01
10
00
00
01
11
1
Am29F400AB(B)
(W) ABH
22ABH A-1
0HI-Z
0HI-Z
1HI-Z
0HI-Z
0HI-Z
0HI-Z
1HI-Z
01
10
01
10
01
10
01
11
1
Sector Protection 01H 0000000000000001
10 Am29F400AT/Am29F400AB
PRELIMINARY
Table 5. Sector Address Tables (Am29F400AT)
Table 6. Sector Address Tables (Am29F400AB)
Write
Device erasure and programming are accomplished via
the command register . The contents of the register serve
as inputs to the internal state machine. The state ma-
chine outputs dictate the function of the de vice .
The command register itself does not occupy any ad-
dressable memory location. The register is a latch used
to store the commands, along with the address and data
information needed to execute the command. The com-
mand register is written to by bringing WE to VIL, while
CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later;
while data is latched on the rising edge of WE or CE,
whiche ver happens first. Standard microprocessor write
timings are used.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Wa veforms for specific timing parameters.
Sector Protection
The Am29F400A features hardware sector protection.
This feature will disable both program and erase opera-
tions in any combination of ten sectors of memor y. The
sector protect feature is enabled using programming
equipment at the user’s site. The device is shipped with
all sectors unprotected. Alternatively, AMD may program
and protect sectors in the factory prior to shipping the
de vice (AMD’s ExpressFlash Service).
A17 A16 A15 A14 A13 A12 (x8) Address
Range (x16) Address
Range
SA0 0 0 0 X X X 00000h-0FFFFh 00000h-07FFFh
SA1 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh
SA2 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh
SA3 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh
SA4 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh
SA5 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh
SA6 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh
SA71110XX70000h-77FFFh 38000h-3BFFFh
SA811110078000h-79FFFh 3C000h-3CFFFh
SA91111017A000h-7BFFFh 3D000h-3DFFFh
SA10 11111X7C000h-7FFFFh 3E000h-3FFFFh
A17 A16 A15 A14 A13 A12 (x8) Address
Range (x16) Address
Range
SA000000X00000h-03FFFh 00000h-01FFFh
SA100001004000h-05FFFh 02000h-02FFFh
SA200001106000h-07FFFh 03000h-03FFFh
SA30001XX08000h-0FFFFh 04000h-07FFFh
SA4 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh
SA5 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh
SA6 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh
SA7 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh
SA8 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh
SA9 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh
SA10 1 1 1 X X X 70000h-7FFFFh 38000h-3FFFFh
Am29F400AT/Am29F400AB 11
PRELIMINARY
5.0 V-only Flash
It is possible to determine if a sector is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where
the higher order address bits A12–A17 is the desired
sector address, will produce a logical “1” at DQ0 for a
protected sector. See Table 3 for Autoselect codes.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors of the Am29F400A device in
order to change data in-system. The Sector Unprotect
mode is activated b y setting the RESET pin to high volt-
age (12 V). During this mode, formerly protected sec-
tors can be programmed or erased by selecting the
sector addresses. Once the 12 V is taken away from
the RESET pin, all the pre viously protected sectors will
be protected again. Refer to Figures 16 and 17.
Command Definitions
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values
or writing them in the improper sequence will reset
the device to the read mode . Table 7 defines the v alid
register command sequences. Note that the
Erase Suspend (B0H) and Erase Resume (30H) com-
mands are valid only while the Sector Erase operation
is in progress. Moreover, both Reset/Read commands
are functionally equivalent, resetting the device to the
read mode.
12 Am29F400AT/Am29F400AB
PRELIMINARY
Table 7. Am29F400A Command Definitions (Notes 1–7)
Notes:
1. Bus operations are defined in Tables 1 and 2.
2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A17–A12 will uniquely select any sector.
3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
4. Reading from non-erasing sectors is allowed in the Erase Suspend mode.
5. Address bits A17–A15 are don’t care for unlock and command cycles.
6. The system should generate the following address patterns:
Word Mode: 5555H or 2AAAH to addresses A0–A14
Byte Mode: AAAAH or 5555H to addresses A-1–A14.
Read/Reset Command
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
Command
Sequence
Read/Reset
Bus
Write
Cycles
Req’d
First Bus
Write Cycle Second Bus
Write Cycle Thir d Bus
Write Cycle Fourth Bus
Read/Write Cycle Fifth Bus
Write Cycle Sixth Bus
Write Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset/Read 1 XXXXH F0H
Reset/
Read Word 35555H AAH 2AAAH 55H 5555H F0H RA RD
Byte AAAAH 5555H AAAAH
Autoselect
Word 3 5555H AAH 2AAAH 55H 5555H 90H 01H 2223H
(T De vice ID)
22ABH
(B Device ID)
Byte AAAAH 5555H AAAAH 23H
(T De vice ID)
ABH
(B Device ID)
Word
/Byte 00H 01H (T/B
Manuf . ID)
Program Word 4 5555H AAH 2AAAH 55H 5555H A0H PA PD
Byte AAAAH 5555H AAAAH
Chip Erase Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Byte AAAAH 5555H AAAAH AAAAH 5555H AAAAH
Sector
Erase Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H
Byte AAAAH 5555H AAAAH AAAAH 5555H
Erase Suspend 1 XXXXH B0H
Erase Resume 1 XXXXH 30H
Am29F400AT/Am29F400AB 13
PRELIMINARY
5.0 V-only Flash
Autoselect Command
Flash memories are intended for use in applications
where the local CPU can alter memory contents. As
such, manufacture and device codes must
be accessible while the device resides in the target
system. PROM programmers typically access the sig-
nature codes by r aising A9 to a high voltage. Howe v er ,
multiplexing high v oltage onto the address lines is not
generally a desirable system design practice.
The de vice contains an autoselect command operation
to supplement traditional PR OM programming method-
ology. The operation is initiated by writing the autose-
lect command sequence into the command register.
Following the command write, a read cycle from ad-
dress XX00H retriev es the manuf acture code of 01H. A
read cycle from address XX01H returns the device
code (Am29F400AT = 23H and Am29F400AB = ABH
f or x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode) (see Tables 3 and 4).
All manufacturer and de vice codes will exhibit odd par-
ity with DQ7 defined as the parity bit.
Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector addresses
(A17, A16, A15, A14, A13, and A12) while (A6, A1, A0)
= (0, 1, 0) will produce a logical “1” at device output
DQ0 for a protected sector.
To ter minate the operation, it is necessar y to write the
read/reset command sequence into the register.
Byte/Word Programming
The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These
are followed by the program setup command and data
write cycles. Addresses are latched on the falling edge
of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichev er hap-
pens first. The rising edge of CE or WE (whiche ver hap-
pens first) begins programming using the Embedded
Program Algorithm. Upon executing the algorithm, the
system is
not
required to provide further controls or tim-
ings. The de vice will automatically provide adequate in-
ternally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is completed
when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time
the de vice returns to the read mode and addresses are
no longer latched (see Table 8, Write Operation Sta-
tus). Therefore , the device requires that a v alid address
to the de vice be supplied by the system at this particu-
lar instance of time for Data Polling operations. Data
Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during the Embed-
ded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the
data at that particular location will be corrupted.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success according
to the data polling algorithm but a read from reset/read
mode will show that the data is still “013”. Only erase
operations can convert “0”s to “1”s.
Figure 1 illustrates the Embedded Progr amming Algo-
rithm using typical command strings and
bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the chip erase command.
Chip erase does
not
require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and v erify the entire memory f or
an all zero data pattern prior to electrical erase. The
erase is performed sequentially on all sectors at the
same time (see Table “Erase and Prog r amming Perfor-
mance”). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi-
nates when the data on DQ7 is “1” (see Write Operation
Status section) at which time the de vice returns to read
the mode.
Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Sector Erase
Sector erase is a six b us cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then f ollowed by the sector erase command. The sector
address (any address location within the
desired sector) is latched on the falling edge of WE,
while the command (30H) is latched on the rising edge
of WE. After a time-out of 100 µs from the r ising edge
of the last sector erase command, the sector erase op-
eration will begin.
Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
sequentially erased. The time between writes must be
less than 100 µs otherwise that command will not be
14 Am29F400AT/Am29F400AB
PRELIMINARY
accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command
is written. A time-out of 100 µs from the rising edge of
the last WE will initiate the execution of the Sector
Erase command(s). If another falling edge of the WE
occurs within the 100 µs time-out window the timer is
reset. (Monitor DQ3 to determine if the sector erase
timer window is still open, see section DQ3, Sector
Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this period will reset the de-
vice to the read mode, ignoring the pre vious command
string. In that case, restart the erase on those sectors
and allow them to complete.
(Refer to the Write Operation Status section for DQ3,
Sector Erase Timer operation.) Loading the sector
erase buffer may be done in any sequence and with
any number of sectors (0 to10).
Sector erase does
not
require the user to program the
device prior to erase. The device automatically pro-
grams all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not af-
fected. The system is
not
required to provide any con-
trols or timings during these operations.
The automatic sector erase begins after the 100 µs
time out from the rising edge of the WE pulse for the
last sector erase command pulse and terminates when
the data on DQ7, Data Polling, is “1” (see Write Opera-
tion Status section) at which time the device returns to
the read mode. Data Polling must be performed at an
address within any of the sectors being erased.
Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to inter-
rupt a Sector Erase operation and then perform data
reads from a sector not being erased. This command is
applicable ONLY during the Sector Erase operation
which includes the time-out period for sector erase . The
Erase Suspend command will be ignored if written dur-
ing the Chip Erase operation or Embedded
Program Algorithm. Writing the Erase Suspend com-
mand during the Sector Erase time-out results in imme-
diate termination of the time-out period and suspension
of the erase operation.
Any other command written during the Erase Suspend
mode will be ignored except the Erase
Resume command. Writing the Erase Resume com-
mand resumes the erase operation. The addresses are
“don’t-cares” when writing the Erase Suspend or Erase
Resume command.
When the Erase Suspend command is written during
the Sector Erase operation, the device will tak e a max-
imum of 15 µs to suspend the erase operation. When
the device has entered the erase-suspended mode,
DQ6 will stop toggling. The user must use the address
of a sector being erased for reading DQ6 to determine
if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the
device defaults to the erase-suspend-read mode.
Reading data in this mode is the same as reading from
the standard read mode except that the data must be
read from sectors that have not been
erase-suspended.
To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. An-
other Erase Suspend command can be written after the
chip has resumed erasing.
Write Operation Status Table 8. Write Operation Status
Notes:
1. D8–D15 = Don’t Care for x16 mode.
2. DQ4 for AMD internal use only.
Status DQ7 DQ6 DQ5 DQ3
In Progress Auto-Programming DQ7 Toggle 0 0
Program/Erase in Auto-Erase 0 Toggle 0 1
Exceeded
Time Limits Auto-Programming DQ7 Toggle 1 0
Program/Erase in Auto-Erase 0 Toggle 1 1
Am29F400AT/Am29F400AB 15
PRELIMINARY
5.0 V-only Flash
DQ7
Data Polling
The Am29F400A device features Data Polling as a
method to indicate to the host that the embedded algo-
rithms are in progress or completed. During
the Embedded Program Algorithm an attempt to read
the de vice will produce the complement of the data last
written to DQ7. Upon completion of the Embedded Pro-
gram Algorithm, an attempt to read the device will pro-
duce the true data last written to DQ7. During the
Embedded Erase Algorithm, an attempt to read
the device will produce a “0” at the DQ7 output.
Upon completion of the Embedded Erase Algorithm an
attempt to read the de vice will produce a “1” at the DQ7
output. The flowchart for Data Polling (DQ7) is shown
in Figure 2.
For chip erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse se-
quence. For sector er ase , the Data Polling is valid after
the last rising edge of the sector erase WE pulse . Data
Polling must be performed at sector addresses within
any of the sectors being erased and not a protected
sector. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm
operations DQ7 may change asynchronously while
the output enable (OE) is asserted low. This means
that the de vice is driving status information on DQ7 at
one instant of time and then that byte’s valid data at
the next instant of time. Depending on when the sys-
tem samples the DQ7 output, it ma y read the status or
valid data. Even if the device has completed the Em-
bedded Algorithm operations and DQ7 has a valid
data, the data outputs on DQ0–DQ6 may be still in-
valid. The valid data on DQ0–DQ7 will be read on the
successive read attempts.
The Data Polling feature is only active during the Em-
bedded Programming Algorithm, Embedded Erase Al-
gorithm, or sector erase time-out (see Table 7).
See Figure 10 f or the Data Polling timing specifications
and diagrams.
DQ6
Toggle Bit
The Am29F400A also features the “Toggle Bit” as a
method to indicate to the host system that the embed-
ded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cy-
cle, successive attempts to read (OE toggling) data
from the device at any address will result in DQ6 tog-
gling between one and zero. Once the Embedded Pro-
gram or Erase Algorithm cycle is completed, DQ6 will
stop toggling and valid data will be read on
the next
successive attempt. During programming, the Toggle
Bit is valid after the rising edge of the four th WE pulse
in the four write pulse sequence. For chip erase, the
Toggle Bit is valid after the rising edge of the sixth WE
pulse in the six write pulse sequence. F or Sector erase,
the Toggle Bit is valid after the last rising edge of the
sector erase WE pulse. The Toggle Bit is active during
the sector time-out.
Either CE or OE toggling will cause DQ6 to toggle. In
addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See Figure 11 for the Toggle Bit
timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a “1”. This is
a failure condition which indicates that the program or
erase cycle was not successfully completed. Data Poll-
ing is the only operating function of the device under
this condition. The CE circuit will partially power down
the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output dis-
able functions as described in Table 1.
The DQ5 f ailure condition will also appear if a user tries
to program a 1 to a location that is previously pro-
grammed to 0. In this case the device locks out and
never completes the Embedded Program Algorithm.
Hence, the system ne ver reads a v alid data on DQ7 bit
and DQ6 ne ver stops toggling. Once the de vice has e x-
ceeded timing limits, the DQ5 bit will indicate a “1.”
Please note that this is not a device failure condition
since the device was incorrectly used. If this occurs,
reset the device.
DQ3
Sector Erase Timer
After the completion of the initial sector erase com-
mand sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete . Data
Polling and Toggle Bit are valid after the initial sector
erase command sequence.
If Data P olling or the Toggle Bit indicates the device has
been written with a valid erase command, DQ3 ma y be
used to determine if the sector erase timer window is
still open. If DQ3 is high (“1”) the inter nally controlled
erase cycle has begun; attempts to write subsequent
commands (other than Erase Suspend) to the device
will be ignored until the erase operation is completed as
indicated by Data Polling or Toggle Bit. If DQ3 is low
(“0”), the device will accept additional sector erase
commands. To insure the command has been ac-
cepted, the system software should chec k the status of
DQ3 prior to and following each subsequent sector
erase command. If DQ3 were high on the second sta-
tus check, the command may not ha v e been accepted.
Refer to Table 8: Write Operation Status.
16 Am29F400AT/Am29F400AB
PRELIMINARY
RY/BY
Ready/Busy
The Am29F400A provides a RY/BY open-drain output
pin as a wa y to indicate to the host system that the Em-
bedded Algorithms are either in progress or hav e been
completed. If the output is low, the device is busy with
either a program or erase operation. If the output is
high, the device is ready to accept any read/write or
erase operation. When the R Y/BY pin is lo w, the device
will not accept any additional program or erase com-
mands with the exception of the Erase Suspend com-
mand. If the Am29F400A is placed in an Erase
Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after
the rising edge of the fourth WE pulse . During an erase
operation, the RY/BY pin is driven low after the rising
edge of the sixth WE pulse. The RY/BY pin should be
ignored while RESET is at VIL. Refer to Figure 12 for a
detailed timing diagram.
Since this is an open-drain output, sev er al RY/BYpins
can be tied together in parallel with a pull-up resistor
to VCC.
RESET
Hardware Reset
The Am29F400A device may be reset by driving the
RESET pin to VIL. The RESET pin must be kept low
(VIL) for at least 500 ns. Any operation in progress will
be terminated and the internal state machine will be
reset to the read mode 20 µs after the RESET pin is
driven low. Furthermore, once the RESET pin goes
high, the device requires an additional 50 ns before it
will allow read access . When the RESET pin is low, the
device will be in the standby mode for the duration of
the pulse and all the data output pins will be tri-stated.
If a hardware reset occurs during a program or erase
operation, the data at that particular location will
be indeterminate.
The RESET pin may be tied to the system reset input.
Therefore, if a system reset occurs during the Embed-
ded Program or Er ase Algorithm, the device will be au-
tomatically reset to read mode and this will enable the
system’s microprocessor to read the boot-up firmware
from the Flash memory.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word
(16 bit) mode for the Am29F400A device. When this
pin is driven high, the de vice operates in the word (16
bit) mode. The data is read and programmed
at DQ0–DQ15. When this pin is driven low, the de-
vice operates in byte (8 bit) mode. Under this mode,
the DQ15/A-1 pin becomes the lowest address bit
and DQ8–DQ14 bits are tri-stated. However, the
command bus cycle is always an 8-bit operation and
hence commands are written at DQ0–DQ7 and the
DQ8–DQ15 bits are ignored. Refer to Figures 14 and
15 for the timing diagram.
Data Protection
The Am29F400A is designed to offer protection against
accidental erasure or programming caused by spurious
system le vel signals that ma y e xist during power transi-
tions. During power up the device automatically resets
the internal state machine in the Read mode. Also , with
its control register architecture, alteration of the mem-
ory contents only occurs after successful completion of
specific multi-bus cycle command sequences.
The device also incorporates several features to pre-
vent inadvertent write cycles resulting from VCC
power-up and po wer-do wn transitions or system noise .
Low VCC Write Inhibit
To avoid initiation of a write cycle during V CC pow er-up
and power-down, the Am29F400A locks out write cy-
cles for VCC < VLK O (see DC Characteristics section f or
voltages). When VCC < VLKO, the command register is
disabled, all internal program/erase circuits
are disabled, and the device resets to the read mode.
The Am29F400A ignores all writes until VCC > VLKO.
The user must ensure that the control pins are in the
correct logic state when VCC > VLKO to prevent unin-
tentional writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL,CE
= VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE =
VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.
Am29F400AT/Am29F400AB 17
PRELIMINARY
5.0 V-only Flash
EMBEDDED ALGORITHMS
Figure 1. Embedded Programming Algorithm
Start
Programming Completed
Last Address
?
Write Program Command Sequence
(see below)
Data Poll Device
Increment Address
Yes
No
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Program Command Sequence (Address/Command):
20380B-8
18 Am29F400AT/Am29F400AB
PRELIMINARY
EMBEDDED ALGORITHMS
Note:
To insure the command has been accepted, the system software should chec k the status of DQ3 prior to and follo wing each sub-
sequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted.
Figure 2. Embedded Erase Algorithm
Start
Erasure Completed
Write Erase Command Sequence
(see below)
Data Polling or Toggle Bit
Successfully Completed
5555H/AAH
2AAAH/55H
5555H/80H
Chip Erase Command Sequence
(Address/Command):
5555H/AAH
2AAAH/55H
5555H/10H
5555H/AAH
2AAAH/55H
5555H/80H
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
5555H/AAH
Sector Address/30H
Sector Address/30H
Sector Address/30H
2AAAH/55H
Additional sector
erase commands
are optional
20380B-9
Am29F400AT/Am29F400AB 19
PRELIMINARY
5.0 V-only Flash
Figure 3. Data Polling Algorithm
Start
Fail
No
DQ7=Data
?
No Pass
Yes
No
Yes
Note:
DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
DQ7=Data
?
DQ5=1
?
Yes
Read Byte
(DQ0-DQ7)
Addr=VA
Read Byte
(DQ0-DQ7)
Addr=VA
VA=Byte address for programming
=any of the sector addresses within the
sector being erased during sector erase
operation
=Valid address equals any non-protected
sector group address during chip erase
20380B-10
20 Am29F400AT/Am29F400AB
PRELIMINARY
Figure 4. Toggle Bit Algorithm
Figure 5. Maximum Negative Overshoot Waveform
Figure 6. Maximum Positive Overshoot Waveform
Start
Fail
No
DQ6=Toggle
?
No
Pass
Yes
No
Yes
Note:
DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
DQ6=Toggle
?
DQ5=1
?
Yes
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
20380B-11
20 ns
20 ns
+0.8 V
-0.5 V
20 ns
-2.0 V
20380B-12
20 ns
VCC + 0.5 V
2.0 V
20 ns 20 ns
VCC + 2.0 V
20380B-13
Am29F400AT/Am29F400AB 21
PRELIMINARY
5.0 V-only Flash
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . -65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . -55°C to +125°C
Voltage with Respect to Ground
All pins except A9, OE and RESET
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V
A9, OE, and RESET (Note 2). . . . . . -2.0 V to +13.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC v oltage on input or I/O pins is -0.5 V. During
voltage tr ansitions , input or I/O pins may undershoot V
SS
to -2.0 V f or periods of up to 20 ns. Maximum DC voltage
on input or I/O pins is
V
CC
+0.5 V. During voltage
transitions, input or I/O pins ma y o v ershoot to V
CC
+2.0 V
for periods up to 20 ns. See Figure 7 and Figure 8.
2. Minimum DC input v oltage on pins A9, OE , and RESET is
-0.5 V. During voltage transitions, A9, OE, and RESET
may undershoot V
SS
to -2.0 V for periods of up to 20 ns.
Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns. See
Figure 7 and Figure 8.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this data sheet is
not implied. Exposure of the de vice to absolute maximum
rating conditions for extended periods may affect device
reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA). . . . . . . . . . . .0˚C to +70˚C
Industrial (I) Devices
Ambient Temperature (TA). . . . . . . . . . -40˚C to +85˚C
Extended (E) Devices
Ambient Temperature (TA). . . . . . . . . -55˚C to +125˚C
VCC Supply Voltages
VCC for Am29F400T/B-65, . . . . . . +4.75 V to +5.25 V
VCC for Am29F400T/B-70, -90,
-120, -150 . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
22 Am29F400AT/Am29F400AB
PRELIMINARY
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at V
IH
.
2. I
CC
active while Embedded Program or Erase Algorithm is in progress.
3. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9, OE, RESET Input Load Current VCC = V CC Max, A9, OE , RESET = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1 VCC Active Read Current (Note 1) CE = VIL, OE = VIH Byte 40 mA
Word 50
ICC2 VCC Active Program/Erase Current
(Notes 2, 3) CE = VIL, OE = VIH 60 mA
ICC3 VCC Standby Current VCC = VCC Max, CE = VIH, OE = VIH 1.0 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
VOH Output High Voltage IOH = -2.5 mA, VCC = VCC Min 2.4 V
VLKO Low V CC Lock-Out Voltage 3.2 4.2 V
Am29F400AT/Am29F400AB 23
PRELIMINARY
5.0 V-only Flash
DC CHARACTERISTICS (continued)
CMOS Compatible
Notes:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at V
IH
.
2. I
CC
active while Embedded Program or Erase Algorithm is in progress.
3. Not 100% tested.
4. I
CC3
= 20
µ
A max at extended temperatures (> +85°C).
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9, OE, RESET Input Load
Current VCC = VCC Max, A9, OE,
RESET = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1 VCC Active Read Current (Note 1) CE = VIL, OE = VIH Byte 20 40 mA
Word 28 50
ICC2 VCC Active Program/Erase
Current (Notes 2, 3) CE = VIL, OE = VIH 30 50 mA
ICC3 VCC Standby Current (Note 4) VCC = VCC Max, CE = VIH,
OE = VIH 15µA
V
IL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 0.7 x
VCC
VCC +
0.3 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
VOH1 Output Low Voltage IOH = –2.5 mA, VCC = VCC Min 0.85
VCC V
VOH2 IOH = –100 µA, VCC = VCC Min VCC -0.4 V
VLKO Low V CC Lock-Out Voltage 3.2 4.2 V
24 Am29F400AT/Am29F400AB
PRELIMINARY
AC CHARACTERISTICS
Read-Only Operations Characteristics
Notes:
Parameter
Symbols Speed Option (Notes 1 and 2)
JEDEC Standard Description Test Setup -65 -70 -90 -120 -150 Unit
tAVAV tRC Read Cycle Time (Note 4) Min 60 70 90 120 150 ns
tAVQV tACC Address to Output Delay CE = VIL
OE = VIL Max 60 70 90 120 150 ns
tELQV tCE Chip Enable to Output Delay OE = VIL Max 60 70 90 120 150 ns
tGLQV tOE Output Enable to Output
Delay Max 30 30 35 50 55 ns
tEHQZ tDF Chip Enable to Output High Z
(Notes 3, 4) Max 20 20 20 30 35 ns
tGHQZ tDF Output Enable to Output
High Z (Notes 3, 4) Max 20 20 20 30 35 ns
tAXQX tOH
Output Hold Time From
Addresses, CE or OE,
Whichever Occurs First Min00000ns
t
Ready RESET Pin Low to Read
Mode (Note 4) Max 20 20 20 20 20 µs
tELFL
tELFH
CE to BYTE Switching Low
or High Max55555ns
1. Test Conditions (for -65 only)
Output Load: 1 TTL gate and 30 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels:0.0 V to 3.0 V
Timing Measurement Reference Level: 1.5 V input
and output
2. Test Conditions (for -70, -90, -120, -150)
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2.0 V
input and output
3. Output Driver Disable Time
4. Not 100% tested.
2.7 kΩ
IN3064 or Equivalent
CL6.2 kΩ
5.0 V
IN3064
or Equivalent
Device
Under
Test
IN3064 or Equivalent
IN3064 or Equivalent
Notes:
For -65: C
L
= 30 pF including jig capacitance
For all others: C
L
= 100 pF including jig capacitance
20380B-14
Figure 7. Test Conditions
Am29F400AT/Am29F400AB 25
PRELIMINARY
5.0 V-only Flash
AC CHARACTERISTICS
Write (Erase/Program) Operations
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
3. These timings are for Temporary Sector Unprotect operation.
4. Output Driver Disable Time.
Parameter Symbols
Description
Speed Option (Notes 1 and 2)
JEDEC Standard -65 -70 -90 -120 -150 Unit
tAVAV tWC Write Cycle Time Min 60 70 90 120 150 ns
tAVWL tAS Address Setup Time Min 00000ns
t
WLAX tAH Address Hold Time Min 45 45 45 50 150 ns
tDVWH tDS Data Setup Time Min 30 30 45 50 50 ns
tWHDX tDH Data Hold Time Min 00000ns
t
OEH
Output
Enable
Hold Time
Read (Note 2) Min 00000ns
Toggle and Data Polling
(Note 2) Min 10 10 10 10 10 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE High to WE Low) Min00000ns
t
ELWL tCS CE Setup Time Min 00000ns
t
WHEH tCH CE Hold Time Min 00000ns
t
WLWH tWP Write Pulse Width Min 35 35 45 50 50 ns
tWHDL tWPH Write Pulse Width High Min 20 20 20 20 20 ns
tWHWH1 tWHWH1 Programming Operation Byte Typ 77777µs
Word Typ1414141414µs
t
WHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ 1.0 1.0 1.0 1.0 1.0 sec
Max88888sec
t
VCS VCC Setup Time (Note 2) Min 50 50 50 50 50 µs
tVIDR Rise Time to VID (Notes 2, 3) Min 500 500 500 500 500 ns
tOESP OE Setup Time to WE Active
(Notes 2, 3) Min44444µs
t
RP RESET Pulse Width Min 500 500 500 500 500 ns
tFLQZ BYTE Switching Low to Output High Z
(Notes 3, 4) Max 20 20 30 30 30 ns
tBUSY Program/Erase Valid to RY/BY Delay
(Note 2) Min 30 30 35 50 55 ns
tRESSP RESET Setup Time to WE Active Min 44444µs
26 Am29F400AT/Am29F400AB
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
SWITCHING W A VEFORMS
Figure 8. AC Waveforms for Read Operations
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
KS000010
Addresses
CE
OE
WE
Outputs
Addresses Stable
High Z High Z
(tDF)
(tOH)
Output V alid
20380B-15
tACC
tOEH
tOE
(tCE)
tRC
Am29F400AT/Am29F400AB 27
PRELIMINARY
5.0 V-only Flash
SWITCHING W A VEFORMS
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D
OUT
is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 9. Program Operation Timings
Notes:
1. SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase.
2. These waveforms are for the x16 mode.
Figure 10. AC Waveforms Chip/Sector Erase Operations
DOUT
PD
tAH
Data Polling
tDF
tOH
tOE
tDS
tCS tWPH
tDH
tWP
tGHWL
Addresses
CE
OE
WE
Data
5.0 V
DQ7
5555H PA
A0H
PA
3rd Bus Cycle
20380B-16
tWC tRC
tAS
tWHWH1
tCE
tAS
tWP
tCS tDH
5555H 2AAAH SA
CE
OE
WE
Data
VCC
AAH 55H
Addresses 2AAAH
tVCS
tDS
5555H 5555H
tWPH
tGHWL
tAH
AAH 55H80H 10H/30H
20380B-17
28 Am29F400AT/Am29F400AB
PRELIMINARY
SWITCHING W A VEFORMS
Note:
*DQ7=Valid Data (The device has completed the Embedded operation).
Figure 11. AC Waveforms for Data Polling During Embedded Algorithm Operations
Note:
*DQ6 stops toggling (The device has completed the Embedded operation).
Figure 12. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
DQ0-DQ6
Valid Data
tOE
DQ7=
Valid Data
High Z
CE
OE
WE
DQ7 DQ7
DQ0-DQ6 DQ0-DQ6=Invalid
*
20380B-18
tOEH
tCE
tCH
tDF
tOH
tWHWH 1 or 2
CE
tOEH
WE
OE
DQ6=
Stop Toggling DQ0-DQ7
Valid
DQ6=Toggle
DQ6=Toggle
Data
(DQ0-DQ7)
*
tOE 20380B-19
Am29F400AT/Am29F400AB 29
PRELIMINARY
5.0 V-only Flash
SWITCHING W A VEFORMS
Figure 13. RY/BY Timing Diagram During Program/Erase Operations
Figure 14. RESET Timing Diagram
CE
WE
RY/BY tBUSY
Entire programming
or erase operations
The rising edge of the last WE signal
20380B-20
RESET
20380B-21
tReady
tRP
30 Am29F400AT/Am29F400AB
PRELIMINARY
SWITCHING W A VEFORMS
Figure 15. BYTE Timing Diagram for Read Operation
Figure 16. BYTE Timing Diagram for Write Operations
CE
OE
BYTE
tELFL
tELFH
DQ0-DQ14 Data Output
(DQ0-DQ14) Data Output
(DQ0-DQ7)
DQ15/A-1 DQ15
Output Address
Input
20380B-22
tFLQZ
CE
WE
BYTE
The falling edge of the last WE signal
tHOLD (tAH)
tSET
(tAS)
20380B-23
Am29F400AT/Am29F400AB 31
PRELIMINARY
5.0 V-only Flash
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 17. Temporary Sector Unprotect Algorithm
Figure 18. Temporary Sector Unprotect Timing Diagram
Start
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotect Completed
(Note 2)
RESET = VID
(Note 1)
20380B-24
RY/BY Program or Erase Command Sequence
20380B-25
RESET
CE
WE
5 V
12 V
tVIDR
32 Am29F400AT/Am29F400AB
PRELIMINARY
AC CHARACTERISTICS
Write/Erase/Program Operations
Alternate CE Controlled Writes
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
Parameter Symbols
Description
Speed Option (Notes 1 and 2)
UnitJEDEC Standard -65 -70 -90 -120 -150
tAVAV tWC Write Cycle Time (Note 2) Min 60 70 90 120 150 ns
tAVEL tAS Address Setup Time Min 00000ns
t
ELAX tAH Address Hold Time Min 45 45 45 50 50 ns
tDVEH tDS Data Setup Time Min 30 30 45 50 50 ns
tEHDX tDH Data Hold Time Min 00000ns
t
OES Output Enable Setup Time Min 00000ns
t
OEH Output Enable
Hold Time
Read (Note 2) Min 00000ns
Toggle and Data
Polling (Note 2) Min 10 10 10 10 10 ns
tGHEL tGHEL Read Recover Time Before Write Min 00000ns
t
WLEL tWS WE Setup Time Min 00000ns
t
EHWH tWH WE Hold Time Min 00000ns
t
ELEH tCP CE Pulse Width Min 35 35 45 50 50 ns
tEHEL tCPH CE Pulse Width High Min 20 20 20 20 20 ns
tWHWH1 tWHWH1 Programming Operation Byte Typ 77777µs
Word Typ1414141414µs
t
WHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ 1.0 1.0 1.0 1.0 1.0 sec
Max88888sec
t
FLQZ BYTE Switching Low to Output High Z
(Note 2) Max 20 20 30 30 30 ns
Am29F400AT/Am29F400AB 33
PRELIMINARY
5.0 V-only Flash
SWITCHING W A VEFORMS
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. D
OUT
is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 19. Alternate CE Controlled Program Operation Timings
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. 25
°
C , 5.0 V V
CC
, 100,000 cycles.
2. Although Embedded Algorithms allow f or longer chip progr am and erase time , the actual time will be consider ab ly less since
bytes program or erase significantly faster than the worst case byte.
3. Under worst case condition of 90
°
C , 4.5 V V
CC
, 100,000 cycles.
4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each
byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.
5. The Embedded Algorithms allow f or 2.5 ms byte program time . DQ5 = “1” only after a byte tak es the theoretical maximum time
to program. A minimal number of bytes ma y require significantly more progr amming pulses than the typical byte. The majority
of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming Times
listed above.
Parameter
Limits
Unit CommentsTyp (Note 1) Max
Sector Erase Time 1.0 8 sec Excludes 00H programming prior to erasure
Chip Erase Time 11 88 sec Excludes 00H programming prior to erasure
Byte Programming Time 7 300 (Note 3) µs Excludes system-level overhead (Note 4)
Word Programming Time 14 600 µs Excludes system-level overhead (Note 4)
Chip Programming Time 3.6 10.8 (Notes 3, 5) sec Excludes system-level overhead (Note 4)
DOUT
PD
tAH
Data Polling
tDS
tWS tCPH
tDH
tCP
tGHEL
Addresses
WE
OE
CE
Data
5.0 Volt
DQ7
5555H PA
A0H
PA
20380B-26
tWC tAS
tWHWH1
34 Am29F400AT/Am29F400AB
PRELIMINARY
LATCHUP CHARACTERISTICS
Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25
°
C, f = 1.0 MHz.
SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25
°
C, f = 1.0 MHz.
DATA RETENTION
Min Max
Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 8 10 pF
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VPP = 0 8 10 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C 10 Years
125°C 20 Years
Am29F400AT/Am29F400AB 35
PRELIMINARY
5.0 V-only Flash
REVISION SUMMARY
Distinctive Characteristics:
High Performance:
The fastest speed option available
is now 60 ns.
Enhanced power management for standby mode:
Changed typical standby current to 1µA.
General Description:
First paragraph, first sentence should read, “...orga-
nized as 512 Kb ytes of 8 bits each or 256
Kwords
of 16
bits each.” Added 60 ns speed option.
Product Selector Guide:
Added -65 column (60 ns, ±5% VCC). Added -70 (70 ns ,
±10% VCC) and deleted -75 speed option.
Ordering Information, Standard Products:
The -65 speed option is now listed in the example.
Valid Combinations:
Added -65 and -70, and deleted -
75 speed options.
Tables 1 and 2, User Bus Operations:
Corrected WE for read operations; was don’t care (X),
is now H.
Standby Mode:
Corrected standby mode current; was 100 µA, is now
5 µA.
Table 5, Sector Address Tables (Am29F400AB):
Corrected x16 star ting address for SA5; was 1C000h,
is now 28000h.
Erase Suspend:
Third paragr aph, third sentence: Deleted the word “NOT.”
Operating Ranges:
V
CC
Supply Voltages:
Added -65 and deleted -75 speed
options in the list. Changed A9 maximum to +13.0 V.
DC Characteristics:
CMOS Compatible:
Revised ICC specifications. Added
Note 4 (refers to ICC3).
AC Characteristics:
Read Only Operations Characteristics:
Added the -65
column and test conditions.
Replaced -75 column with -70 column.
Test Conditions, Figure 7:
Changed speed option in first CL statement from -75
to -65.
AC Characteristics:
Write/Erase/Program Operations, Alternate CE Con-
trolled Writes:
Added the -65 column. Replaced -75
column with -70 column. Revised sector erase and
programming specifications.
Erase and Programming Performance:
Re vised specifications in table. Clarified table and notes .
Table 7, Command Definitions
Re vised Note 5 to cov er all upper address bits that are
don’t care.
Deleted Note 6.
