2
PIN NAMES
DEVICE OPERATION
The UT8R512K8 has four control inputs called Enable 1 (E1),
Enable 2 (E2), Write Enable (W), and Output Enable (G); 19
address inputs, A(18:0); and eigh t bidirectional data lines,
DQ(7:0). E1 and E2 device enables control device selection,
active, and standby modes. Asserting E1 and E2 enables the
device, causes I
DD
to rise to its active value, and decodes the 19
address inputs to select one of 524,288 words in the memory . W
controls read and write operations. During a read cycle, G must
be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W and E2 greater than VIH (min) and E1 less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs
remain active throughout the entire cycle. As long as device
enable and output enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by E1 and E2 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified tETQV is satisfied, the
eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is tGLQV unless tAVQV or tETQV have not been
satisfied.
A(18:0) Address W WriteEnable
DQ(7:0) Data Input/Output G Output Enable
E1 Enable VDD1 Power (1.8V)
E2 Enable VDD2 Power (3.3V)
VSS Ground
136
235
334
433
532
631
730
829
928
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19
Figure 2. 15ns SRAM Pinout (36)
E2
A18
A17
A16
A15
G
DQ7
DQ6
V
SS
V
DD1
DQ5
DQ4
A14
A13
A12
A11
A10
V
DD2
A0
A1
A2
A3
A4
E1
DQ0
DQ1
V
DD1
V
SS
DQ2
DQ3
W
A5
A6
A7
A8
A9
G W E2 E1 I/O Mode Mode
XXX13-stateStandby
X X 0 X 3-state Standby
X 0 1 0 Data in Write
11103-state
Read2
0110Data outRead