1
MEMORY
ARRAY
COLUMN
I/O
INPUT
DRIVERS
INPUT
DRIVERS
ROW
DECODER
OUTPUT ENABLE
E2
W
G
E1
CHIP ENABLE OUTPUT
DRIVERS
DATA
WRITE
CIRCUIT
DATA
READ
CIRCUIT
COLUMN
DECODER
WRITE ENABLE
INPUT
DRIVERS
INPUT
DRIVERS
TOP/BOTTOM
DECODER
BLOCK
DECODER
INPUT
DRIVERS
A(18:0)
INPUT
DRIVER
DQ(7:0)
Figure 1. UT8R512K8 SRAM Block Diagram
FEATURES
15ns maximum access time
Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
Radiation performance
- Intrinsic total-dose: 300K rad(Si)
- SEL Immune >100 MeV-cm2/mg
- LETth (0.25): 53.0 MeV-cm2/mg
- Memory Cell Saturated Cross Section 1.67E-7cm2/bit
- Neutron Fluence: 3.0E14n/cm2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
Packaging options:
- 36-lead ceramic flatpack (3.762 grams)
Standard Microcircuit Drawing 5962-03235
- QML compliant part
INTRODUCTION
The UT8R512K8 is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by taking chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW . Data on the eight I/O pins (DQ0 through DQ7)
is then written into the location specified on the address pins
(A0 through A18). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed in a
high impedance state when the device is deselected (E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation (E1 LOW, E2 HIGH and W LOW).
Standard Products
UT8R512K8 512K x 8 SRAM
Data Sheet
April 2005
www.aeroflex.com/4MSRAM
2
PIN NAMES
DEVICE OPERATION
The UT8R512K8 has four control inputs called Enable 1 (E1),
Enable 2 (E2), Write Enable (W), and Output Enable (G); 19
address inputs, A(18:0); and eigh t bidirectional data lines,
DQ(7:0). E1 and E2 device enables control device selection,
active, and standby modes. Asserting E1 and E2 enables the
device, causes I
DD
to rise to its active value, and decodes the 19
address inputs to select one of 524,288 words in the memory . W
controls read and write operations. During a read cycle, G must
be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W and E2 greater than VIH (min) and E1 less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs
remain active throughout the entire cycle. As long as device
enable and output enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by E1 and E2 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified tETQV is satisfied, the
eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is tGLQV unless tAVQV or tETQV have not been
satisfied.
A(18:0) Address W WriteEnable
DQ(7:0) Data Input/Output G Output Enable
E1 Enable VDD1 Power (1.8V)
E2 Enable VDD2 Power (3.3V)
VSS Ground
136
235
334
433
532
631
730
829
928
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19
Figure 2. 15ns SRAM Pinout (36)
E2
A18
A17
A16
A15
G
DQ7
DQ6
V
SS
V
DD1
DQ5
DQ4
A14
A13
A12
A11
A10
V
DD2
A0
A1
A2
A3
A4
E1
DQ0
DQ1
V
DD1
V
SS
DQ2
DQ3
W
A5
A6
A7
A8
A9
G W E2 E1 I/O Mode Mode
XXX13-stateStandby
X X 0 X 3-state Standby
X 0 1 0 Data in Write
11103-state
Read2
0110Data outRead
3
WRITE CYCLE
A combination of W and E1 less than VIL(max) and E2 greater
than VIH(min) defines a write cycle. The state of G is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either G is greater than VIH(min), or
when W is less than VIL(max).
Write Cycle 1, the Write Enable-controlled Access in Figure
4a, is defined by a write terminated by W going high, with E1
and E2 still active. The write pulse width is defined by tWLWH
when the write is initiated by W, and by tETWH when the write
is initiated by E1 or E2. Unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait tWLQZ before applying data to the nine bidirectional
pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure
4b, is defined by a write terminated by the latter of E1 or E2
going inactive. The write pulse width is defined by tWLEF when
the write is initiated by W, and by tETEF when the write is
initiated by either E1or E2 going active. For th e W initiated
write, unless the outputs have been previously placed in the
high-impedance state by G, the user must wait tWLQZ before
applying data to the eight bidirectional pins DQ(7:0) to avoid
bus contention.
RADIATION HARDNESS
The UT8R512K8 SRAM incorporates special design and
layout features which allows operation in a limit ed radiation
environment.
Table 2. Radiati o n Hardness
Design Specification s1
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm
2
/mg.
2. 10% worst case particle environment, Geosynchrono us orbit, 100 mils of
Aluminum.
Supply Sequencing
No supply voltage sequencing is required between VDD1 and
VDD2.
Total Dose 300K rad(Si)
Heavy Ion
Error Rate28.9x10-10 Errors/Bit-Day
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD1 DC supply voltage -0.3 to 2.0V
VDD2 DC supply voltage -0.3 to 3.8V
VI/O Voltage on any pin -0.3 to 3.8V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissip ation 1.2W
TJMaximum junction tem perat ure2+150°C
ΘJC Thermal resistance, junction-to-case35°C/W
IIDC input current
±
5 mA
SYMBOL PARAMETER LIMITS
VDD1 Positive supply voltage 1.7 to 1.9V
VDD2 Positive supply voltage 3.0 to 3.6V
TCCase temperature range (C) Screening: -55 to +125°C
(W) Screening: -40 to +125°C
VIN DC input voltage 0V to VDD2
5
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(-55°C to +125°C for (C) scr eening and -40°C to 125°C fo r (W) screening)
Notes:
* Post-radiation pe rfo rm ance guaranteed at 25°C per MIL-STD-883 Method 1019 at 3.0E5 rad(Si).
1. Measured only for initial qualification and after process or design changes that could af fect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. V
IH
= V
DD2
(max), V
IL
= 0V.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage .7*VDD2 V
VIL Low-level input voltage .3*VDD2 V
VOL1 Low-level output voltage IOL = 8mA,VDD2 =VDD2 (min) .2*VDD2 V
VOH1 High-level output voltage IOH = -4mA,VDD2 =VDD2 (min) .8*VDD2 V
CIN1Input capacitance ƒ = 1MHz @ 0V 12 pF
CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 12 pF
IIN Input leakage current VIN = VDD2 and VSS -2 2 µA
IOZ Three-state output leakage
current VO = VDD2 and VSS, VDD2 = VDD2 (max)
G = VDD2 (max)
-2 2 µA
IOS2, 3 Short-circuit output current VDD2 = VDD2 (max), VO = VDD2
VDD2 = VDD2 (max), VO = VSS
-100 +100 mA
IDD1(OP1) Supply current operating
@ 1MHz Inputs : VIL = VSS + 0.2V
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
12 mA
IDD1(OP2) Supply current operating
@66MHz Inputs : VIL = VSS + 0.2V,
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
30 mA
IDD2(OP1) Supply current operating
@ 1MHz Inputs : VIL = VSS + 0.2V
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
.2 mA
IDD2(OP2) Supply current operating
@66MHz Inputs : VIL = VSS + 0.2V,
VIH = VDD2 - 0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
4mA
IDD1(SB)4
IDD2(SB)4
Supply current standby @
0Hz CMOS inputs , IOUT = 0
E1 = VDD2 -0.2, E2 = GND
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
11
100
mΑ
µA
IDD1(SB)4
IDD2(SB)4
Supply current standby
A(18:0) @ 66MHz CMOS inputs , IOUT = 0
E1 = VDD2 - 0.2, E2 = GND,
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
11
100
mΑ
µA
6
AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)*
(-55°C to +125°C for (C) screening and -40°C to +125°C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min))
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Guaranteed, but not tested.
2. Three-state is defined as a 200mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the latter falling edge of E1 or rising edge of E2. SEU immunit y does not affect the read parameter s.
4. The EF (enable false) notation refers to the latter rising edge of E1 or falling edge of E2. SEU immunity does not affect the read parameters.
SYMBOL PARAMETER 8R512-155
MIN MAX
UNIT
tAVAV1Read cycle time 15 ns
tAVQV Read access time 15 ns
tAXQX2Output hold tim e 3 ns
tGLQX1,2 G-controlled output enable time 0 ns
tGLQV G-controlled output enable time 7 ns
tGHQZ2G-controlled output three-state time 7 ns
tETQX2,3 E-controlled output enable time 5 ns
tETQV3E-controlled access time 15 ns
tEFQZ4E-controlled output three-state time27ns
7
Assumptions:
1. E1 and G < V
IL
(max) and EZ and W > V
IH
(min)
A(18:0)
DQ(7:0)
Figure 3a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data Valid Data
Assumptions:
1. G < V
IL
(max) and W > V
IH
(min)
A(18:0)
Figure 3b. SRAM Read Cycle 2: Chip Enable Access
E1 low or
E2 high
DATA VALID
tEFQZ
tETQV tETQX
DQ(7:0)
Figure 3c. SRAM Read Cycle 3: Output Enable Access
A(18:0)
DQ(7:0)
G
tGHQZ
Assumptions:
1. E1 < V
IL
(max) , E2 > an d W > V
IH
(min)
tGLQV
tGLQX
tAVQV
DATA VALID
8
AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)*
(-55°C to +125°C for (C) screening and -40°C to +125°C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min))
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Test with G high.
2. Three-state is defined as 200mV change from steady-state output voltage.
SYMBOL PARAMETER 8R512-15
MIN MAX
UNIT
tAVAV1Write cycle time 15 ns
tETWH Device enable to end of write 12 ns
tAVET Address setup time for write (E1/E2- controlled) 0 ns
tAVWL Address setup time for write (W - controlled) 1 n s
tWLWH Write pulse width 12 ns
tWHAX Address hold time for write (W - controlled) 2 ns
tEFAX Address hold time for device enable (E1/E2- controlled) 0 ns
tWLQZ2W - controlled three-state time 5 ns
tWHQX2W - controlled output enable time 4 ns
tETEF Device enable pulse width (E1/E2 - controlled) 12 ns
tDVWH Data setup time 7 ns
tWHDX Data hold time 2 ns
tWLEF Device enable controlled write pulse width 12 ns
tDVEF Data setup time 7 ns
tEFDX Data hold time 0 ns
tAVWH Address valid to end of write 12 ns
tWHWL1Write disable time 3 ns
9
Assumptions:
1. G < V
IL
(max). If (G > V
IH
(min) then Q(8:0) will be
in three-state for the entire cycle).
W
tAVWL
Figure 4a. SRAM Write Cycle 1: W - Controlled Access
A(18:0)
Q(7:0)
E1
tAVAV
D(7:0) APPLIED DATA
tDVWH tWHDX
tETWH
tWLWH tWHAX
tWHQX
tWLQZ
tAVWH
tWHWL
E2
10
tEFDX
Assumptions & Notes:
1. G < V
IL
(max). (If G > V
IH
(min) then Q(7:0) will be in three-state for the entire cycle).
2. Either E1 scenario above can occur.
A(18:0)
Figure 4b. SRAM Write Cycle 2: Enable - Controlled Access
W
E1
D(7:0) APPLIED DATA
E1
Q(7:0) tWLQZ
tETEF
tWLEF
tDVEF
tAVAV
tAVET
tAVET
tETEF
tEFAX
tEFAX
or
E2
E2
11
DATA RETENTION CHARACTERISTICS (Pre-Radiation)* (VDD2 = VDD2 (min), 1 Sec DR Pulse)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. E1 =
V
DD2
or E2 = V
SS
all other inputs = V
DD2
or V
SS
2. V
DD2
= 0 volts to V
DD2
(max)
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
VDR VDD1 for data retention 1.0 -- V
IDDR 1
Device Type 1
Data retention current -- 600
600
12
µA
µA
mA
IDDR 1
Device Type 2
Data retention current -- 600
600
12
µA
µA
mA
tEFR1,2 Chip deselect to data retention time 0ns
tR1,2 Operation recovery time tAVAV ns
VDD1
DATA RETENTION MODE
tR
1.7V
VDR > 1.0V
Figure 5. Low VDD Data Retention Waveform
tEFR
E1 VDD2
V
IN
<0.3V
DD2
CMOS
E2 VSS
V
IN
>0.7V
DD2
CMOS
1.7V
Notes:
1. 50pF including scope probe and test socket.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = V
DD2
/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 2ns < 2ns
1.4V
188 ohms
50pF
CMOS
0.0V
V
DD2
-0.05V
12
PACKAGING
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance to MIL-PRF-38535.
4. Dimension sybology is in accordance with MIL-PRF-38535.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor option: no alphanumerics. One or both ID methods ma y be used
for Pin 1 ID.
7. Equivalent to MIL-STD-1853A F-19 configuration A (glass field) using a configuration B
(multi-layer) ceramiic body style.
Figure 7. 36-pin Ceramic FLATPACK
13
ORDERING INFORMATION
512K x 8 SRAM:
UT **** * - * * * * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening:
(C) = Military Temperature Range flow
(-55°C to +125°C)
(P) = Prototype flow
(W) = Extended industrial temperature range flow
(-40°C to +125°C)
Package Type:
(U) = 36-lead FP
Access Time:
(15) = 15ns access time
Device Type:
(8R512K8) = 512K x 8 SRAM
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per UTMC Manufacturing Flo ws Document. Tested at 25°C only . Lead finish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.
Radiation neither tested nor guaranteed.
14
512K x 8 SRAM: SMD
5962 - ******* ** Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(U) = 36-lead ceramic flatpack
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type
(01) = 15ns access time, CMOS I/O, 36-lead flatpack package, dual chip enable
(-55°C to +125°C)
(02) = 15ns access time, CMOS I/O, 36-lead flatpack package, dual chip enable
(-40°C to +125°C)
(02TBD)=15ns access time, CMOS I/O, 40-lead flatpack package, dual chip enable (not available)
Drawing Number: 03235
Total Dose:
(R) = 100K rad(Si)
(F) = 300K rad(Si)
Federal Stock Class Designator: No options
** *
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
15
NOTES
16
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