RM25C64C-LSNI-B - Adesto Technologies

DS-RM25C64C-L–097A–3/2016

Features

Memory array: 64 Kbit EEPROM-compatible non-volatile serial memory

Single supply voltage: 1.65V - 3.6V

Serial peripheral interface (SPI) compatible

-Supports SPI modes 0 and 3

1.6 MHz maximum clock rate for normal read

10 MHz maximum clock rate for fast read

Flexible Programming

- Byte/Page Program (1 to 32 Bytes)

- Page size: 32 Bytes

Low Energy Byte Write

-Byte Write consuming 50 nJ

Low power consumption

-0.25 mA active Read current (Typical)

-1 mA active Write current (Typical)

-2.2 µA power down current (Typical)

Fast Page Write

-Page Write in 1 ms (32 byte page)

-Byte Write within 25 µs

Self-timed erase and write cycles

Page or chip erase capability

8-lead SOIC and TSSOP packages

RoHS-compliant and halogen-free packaging

Data Retention: 10 years

Based on Adesto's proprietary CBRAM® technology

Endurance: 10,000 Write Cycles

Unlimited Read Cycles

Description

The Mavriq™ RM25C64C-L is a 64 Kbit serial memory device that utilizes Adesto's

CBRAM® resistive technology. The memory devices use a single low-voltage supply

ranging from 1.65V to 3.6V.

The Mavriq RM25C-Series family is accessed through a 4-wire SPI interface

consisting of a Serial Data Input (SDI), Serial Data Output (SDO), Serial Clock (SCK),

and Chip Select (CS). The maximum clock (SCK) frequency in normal read mode is

1.6MHz. In fast read mode the maximum clock frequency is 10MHz. Writing into the

device can be done from 1 to 32 bytes at a time. All writing is internally self-timed. The

device also features an Erase which can be performed on 32-byte pages or on the

whole chip.

RM25C64C-L

64 Kbit 1.65V Minimum

Non-volatile Serial Memory

SPI Bus

Preliminary Datasheet

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The device has both Byte Write and Page Write capability. Page Write is 32 bytes. The Byte Write operation of Mavriq

memory consumes only 10% of the energy consumed by a Byte Write operation of EEPROM devices of similar size.

The Page Write operation of Mavriq memory is 4-6 times faster than the Page Write operation of similar EEPROM

devices. Both random and sequential reads are available. Sequential reads are capable of reading the entire memory in

one operation.

1. Block Diagram

Figure 1-1. Block Diagram

SPI

Interface

SDO

GND

SCK

SDI

HOLD

Status

Registers

Control

Logic

I/O Buffers and Data

Latches

Y-Decoder

X-Decoder

Address

Latch

Counter

VCC

Page Buffer

32 Kb - 512 Kb

CBRAM

Memory

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2. Absolute Maximum Ratings

Table 2-1. Absolute Maximum Ratings(1)

1. CAUTION: Stresses greater than Absolute Maximum Ratings may cause permanent damage to the devices. These

are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in other

sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods

may reduce device reliability

Parameter Specification

Operating ambient temp range -40°C to +85°C

Storage temperature range -65°C to +150°C

Input supply voltage, VCC to GND - 0.3V to 3.6V

Voltage on any pin with respect to GND -0.5V to (VCC + 0.5V)

ESD protection on all pins (Human Body Model) >2kV

Junction temperature 125°C

DC output current 5mA

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3. Electrical Characteristics

3.1 DC Operating Characteristics

Applicable over recommended operating range: TA = -40°C to +85° C, VCC = 1.65V to 3.6V

Symbol Parameter Condition Min Typ Max Units

TA = -40°C to +85° C,

VCC = 1.65V to 3.6V

VCC Supply Range 1.65 3.6 V

VVccI VCC Inhibit 1.55 V

ICC1 Supply current, Fast

Read

VCC= 3.3V SCK at 10 MHz

1.0 3mA

SDO = Open, Read

ICC2

Supply Current,

Read Operation

VCC= 3.3V SCK at 1.0 MHz

SDO = Open, Read 0.25 0.5 mA

ICC3

Supply Current,

Program or Erase VCC= 3.3V, CS = VCC 1 3 mA

ICC4

Supply Current,

Standby, LPSE=0

VCC= 3.3V, CS = VCC

@25°C80 90

µA

@85°C100 120

Supply Current,

Standby, LPSE=1

@25°C45 55

@85°C65 75

Supply Current, Standby,

Auto Power Down

enabled

@25°C2.2 3

@85°C11 17

ICC5

Supply Current,

Power Down VCC= 3.3V Power Down

@25°C2.2 3

µA

@85°C11 17

ICC6

Supply Current,

Ultra Deep Power Down

Vcc = 3.3V,

Ultra Deep Power Down

@25°C1.6 2.5

µA

@85°C11 17

IOL Output Leakage SDO , CS = VCC

VIN=0V to VCC

1µA

IIL Input Leakage SCK, SDI, CS, HOLD, WP

VIN=0V to VCC

1µA

VIL Input Low Voltage SCK, SDI, CS, HOLD, WP -0.3 VCC x 0.3 V

VIH Input High Voltage SCK, SDI, CS, HOLD, WP VCC x 0.7 VCC + 0.3 V

VOL Output Low Voltage IOL = 3.0mA 0.4 V

VOH Output High Voltage IOH = -100µA VCC - 0.2 V

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3.2 AC Operating Characteristics

Applicable over recommended operating range: TA = -40°C to +85° C, VCC = 1.65V to 3.6V

CL = 1 TTL Gate plus 10pF (unless otherwise noted)

Symbol Parameter Min Typ Max Units

fSCKF SCK Clock Frequency for Fast Read Mode 010 MHz

fSCK SCK Clock Frequency for Normal Read Mode 01.6 MHz

fAPD SCK Clock Frequency for Auto Power Down Mode 01.0 MHz

tRI SCK Input Rise Time 1µs

tFL SCK Input Fall Time 1µs

tSCKH SCK High Time 7.5 ns

tSCKL SCK Low Time 7.5 ns

tCS CS High Time 100 ns

tCSS CS Setup Time 10 ns

tCSH CS Hold Time 10 ns

tDS Data In Setup Time 4ns

tDH Data In Hold Time 4ns

tHS HOLD Setup Time 30 ns

tHD HOLD Hold Time 30 ns

tOV Output Valid 6.5 ns

tOH Output Hold Time Normal Mode 0ns

tLZ HOLD to output Low Z 0200 ns

tHZ HOLD to output High Z 200 ns

tDIS Output Disable Time 100 ns

tPW Page Write Cycle Time, 32 byte page 1 5 ms

tBP Byte Write Cycle Time 25 100 µs

tPUD Vcc Power-up Delay(1) 75 µs

tRPD Exit Power Down Time 50 µs

tCSLU

Minimum Chip Select Low to Exit

Ultra-Deep Power-Down 20 ns

tXUDPD Exit Ultra-Deep Power Down Time 70 µs

tRDPD Chip Select High to Standby Mode 8µs

CIN SCK, SDI, CS, HOLD, WP

VIN=0V 6pf

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Notes: 1. VCC must be within operating range.

2. Adesto memory products based on CBRAM technology are “Direct-Write” memories. Endurance cycle calculations follow

JEDEC specification JESD22-A117B.

3. Subject to expected 10-year data retention specification.

3.3 AC Test Conditions

4. Timing Diagrams

Figure 4-1. Synchronous Data Timing with HOLD high

COUT SDO VIN=0V 8pf

Endurance

10,000(2) Write

Cycles

Unlimited(3) Read

Cycles

Retention 10 Years

Symbol Parameter Min Typ Max Units

AC Waveform Timing Measurement

Reference Level

VLO = 0.2V

Input

Output

0.5 Vcc

VHI = 3.4V

CL = 30pF (for 1.6 MHz SCK)

CL = 10pF (for 10 MHz SCK)

SDI

SCK

VALID IN

CSS

SC KH

SC KL

SDO

HI-Z

CSH

HI-Z

DIS

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Figure 4-2. Hold Timing

Figure 4-3. Power-up Timing

HOLD

SCK

SDO

VCC

min

VCC

max

VCCI

Device in Reset

Program, Read, Erase and Write Commands Rejected

PUD

Device Fully

Accessible

TIME

VCC

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5. Pin Descriptions and Pin-out

Table 5-1. Pin Descriptions

Figure 5- 1. Pin Out

6. SPI Modes Description

Multiple Adesto SPI devices can be connected onto a Serial Peripheral Interface (SPI) serial bus controlled by an SPI

master, such as a microcontroller, as shown in Figure 6-1,

Mnemonic Pin Number Pin Name Description

CS 1Chip Select

Making CS low activates the internal circuitry for device operation.

Making CS high deselects the device and switches into standby

mode to reduce power. When the device is not selected (CS high),

data is not accepted via the Serial Data Input pin (SDI) and the

Serial Data Output pin (SDO) remains in a high-impedance state.

SDO 2Serial Data Out Sends read data or status on the falling edge of SCK.

WP 3Write Protect N/A

GND 4Ground

SDI 5Serial Data In Device data input; accepts commands, addresses, and data on the

rising edge of SCK.

SCK 6Serial Clock

Provides timing for the SPI interface. SPI commands, addresses,

and data are latched on the rising edge on the Serial Clock signal,

and output data is shifted out on the falling edge of the Serial Clock

signal.

HOLD 7Hold When pulled low, serial communication with the master device is

paused, without resetting the serial sequence.

Vcc 8Power Power supply pin.

SPI

SDO

GND

VCC

HOLD

SCK

SDI

Pin 1

Vcc

GND

SDI

SDO

SCK

SOIC, UDFN and TSSOP WLCSP (Bottom View)

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Figure 6-1. Connection Diagram, SPI Master and SPI Slaves

The Adesto RM25C family supports two SPI modes: Mode 0 (0, 0) and Mode 3 (1, 1). The difference between these two

modes is the clock polarity when the SPI master is in standby mode (CS high). In Mode 0, the Serial Clock (SCK) stays

at 0 during standby. In Mode 3, the SCK stays at 1 during standby. An example sequence for the two SPI modes is

shown in Figure 6-2. For both modes, input data (on SDI) is latched in on the rising edge of Serial Clock (SCK), and

output data (SDO) is available beginning with the falling edge of Serial Clock (SCK).

Figure 6-2. SPI Modes

SDO

SPI Memory

Device

SPI Interface with

Mode 0 or Mode 3

SDI

SCK

SPI Master

(i.e. Microcontroller)

CS1CS2CS3

SCK SDO SDI

SPI Memory

Device

SPI Memory

Device

SCK SDO SDI SCK SDO SDI

CS CS CS

SDI

Mode 3 (1,1) SCK

SDO

Mode 0 (0,0) SCK

MSB

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7. Registers

7.1 Instruction Register

The Adesto RM25C family uses a single 8-bit instruction register. The instructions and their operation codes are listed in

Table 7-1. All instructions, addresses, and data are transferred with the MSB first, and begin transferring with the first

low-to-high SCK transition after the CS pin goes low.

Table 7-1. Device Operating Instructions

7.2 Status Register

The Adesto RM25C family uses a single 8-bit Status Register. The Write In Progress (WIP) and Write Enable (WEL)

status of the device can be determined by reading this register.

The Status Register format is shown in Table 7-2 The Status Register bit definitions are shown in Table 7-3.

Table 7-2. Status Register Format

Instruction Description Operation

Code Address

Cycles Dummy

Cycles Data

Cycles

WRSR Write Status

WR Write 1 to 32 bytes 02H 2 0 1-32

READ Read data from

memory array 03H 2 0 1 to ∞

FREAD Fast Read data

from data memory 0BH 2 1 1 to ∞

WRDI Write Disable 04H 0 0 0

RDSR Read Status

WREN Write Enable 06H 0 0 0

PERS Page Erase

32 bytes 42H 2 0 0

CERS Chip Erase

60H 0 0 0

C7H 0 0 0

PD Power Down B9H 0 0 0

UDPD Ultra Deep Power

Down 79H 0 0 0

RES Resume from

Power Down ABH 0 0 0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SRWD APDE LPSE 0BP1 BP0 WEL WIP

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Table 7-3. Status Register Bit Definitions

8. Write Protection

The Adesto RM25CxxC family has two protection modes: hardware write protection, via the WP pin associated with the

SRWD bit in the Status Register, and software write protection in the form of the SRWD, WEL, BP0, and BP1 bits in the

Status Register.

8.1 Hardware Write Protection

There are three hardware write protection features:

• All write instructions must have the appropriate number of clock cycles before CS goes high or the write instruction

will be ignored.

• If the VCC is below the VCC Inhibit Voltage (VVccI, see DC Characteristics), all Read, Write, and Erase sequence

instructions will be ignored.

• The WP pin provides write protection for the Status Register. When WP is low, the Status Register is write

protected if the SRWD bit in the Status Register is High. When WP is high, the Status Register is writable independent of

the SRWD bit. See Table 8-1.

Bit Name Description R/W Non-Volatile Bit

0WIP

Write In Progress

“0” indicates the device is ready

“1” indicates that the program/erase cycle

is in progress and the device is busy

RNo

1WEL Write Enable Latch

“0” Indicates that the device is disabled

“1” indicates that the device is enabled

R/W No

2BP0 Block Protection Bits. "0" indicates the

specific blocks are not protected.

"1" indicates that the specific blocks are

protected.

R/W Yes

3BP1

4N/A Reserved. Read as “0” N/A No

5LPSE

Low Power Standby Enable.

"0" indicates that the device will not use

Low Power Standby Mode.

"1" indicates that the device will use Low

Power Standby Mode.

R/W Yes

6APDE

Auto Power Down Enable.

"0" indicates that the device will use

Standby Mode.

"1" indicates that the device will use Power

Down Mode instead of Standby Mode.

R/W Yes

7SRWD WP pin enable. See Table 8-1. R/W Yes

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Table 8-1. Hardware Write Protection on Status Register

8.2 Software Write Protection

There are two software write protection features:

• Before any program, erase, or write status register instruction, the Write Enable Latch (WEL) bit in the Status

program, erase, or write register instructions will be ignored.

• The Block Protection bits (BP0 and BP1) allow a part or the whole memory area to be write protected.

See Table 8-2.

Table 8-2. Block Write Protect Bits

8.3 Reducing Energy Consumption

In normal operation, when the device is idle, (CS is high, no Write or Erase operation in progress), the device is in

Standby Mode, waiting for the next command. To reduce device energy consumption, the Power Down or Ultra-Deep

Power Down modes may be used.

8.3.1 Power Down mode

Power Down mode allows the user to reduce the power of the device to its lowest power consumption state. The PD

command is used to instruct the device to enter Power Down mode.

All instructions given during the Power Down mode are ignored except the Resume From Power Down (RES) instruction.

Therefore this mode can be used as an additional software write protection feature.

SRWD WP Status

0Low Writable

1Low Protected

0High Writable

1High Writable

BP1 BP0 Protected

Region RM25C64C-L

Protected

Address

Protected

Area Size

0 0 None None 0

0 1 Top ¼ 3000-

3FFF

bytes

1 0 Top ½ 2000-

3FFF

bytes

1 1 All 0-

3FFF All

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8.3.2 Ultra-Deep Power Down mode

The Ultra-Deep Power Down mode allows the device to further reduce its energy consumption compared to the existing

Standby and Power Down modes by shutting down additional internal circuitry. The UDPD command is used to instruct

the device to enter Ultra-Deep Power Down mode.

When the device is in the Ultra-Deep Power Down mode, all commands including the Read Status Register and Resume

From Power Down commands will be ignored. Since all commands will be ignored, the mode can be used as an extra

protection mechanism against inadvertent or unintentional program and erase operations.

Only the Exit Ultra-Deep Power Down signal sequences described in section 8-13 will bring the device out of the Ultra-

Deep Power Down mode.

8.3.3 Auto Power Down Enable.

For frequencies lower than fAPD (see AC Operating Characteristics), the APDE bit in the Status Register may be enabled.

The device will then automatically enter Power Down mode instead of Standby mode when idle. (CS is high, no Write or

Erase operation in progress).

In this mode, the device will behave normally to all commands, and will leave Power Down mode once CS is pulled down.

If Auto Power Down is enabled, and the SCK Clock Frequency is increased to a speed higher than fAPD, the device may

not react as expected to the command. Before changing SCK frequency, the APDE bit in the Status Register must be

disabled.

Note that the PD or UDPD commands may still be used as additional software write protection features when Auto Power

Down is enabled. Note that if the PD command is issued while Auto Power Down is enabled, the device will enter Power

Down mode, and all instructions given will be ignored except the Resume From Power Down (RES) instruction. The

device will not wake up immediately after CS is pulled down.

8.3.4 Low Power Standby Enable.

For frequencies lower than fAPD (see AC Operating Characteristics), the LPSE bit in the Status Register may be enabled.

The device will then automatically enter Low Power Standby mode when idle. (CS is high, no Write or Erase operation in

progress).

In this mode, the device will behave normally to all commands, and will leave Low Power Standby mode once CS is

pulled down.

If Low Power Standby Mode is enabled, and the SCK Clock Frequency is increased to a speed higher than fAPD, the

device may not react as expected to the command. Before changing SCK frequency, the LPSE bit in the Status Register

must be disabled.

Note that the PD or UDPD commands may still be used as additional software write protection features when Low Power

Standby Mode is enabled. Note that if the PD command is issued while Low Power Standby Mode is enabled, the device

will enter Power Down mode, and all instructions given will be ignored except the Resume From Power Down (RES)

instruction. The device will not wake up immediately after CS is pulled down.

9. Command Descriptions

9.1 WREN (Write Enable):

The device powers up with the Write Enable Latch set to zero. This means that no write or erase instructions can be

executed until the Write Enable Latch is set using the Write Enable (WREN) instruction. The Write Enable Latch is also

set to zero automatically after any non-read instruction. Therefore, all page programming instructions and erase

instructions must be preceded by a Write Enable (WREN) instruction. The sequence for the Write Enable instruction is

shown in Figure 9-1.

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Figure 9-1. WREN Sequence (06h)

Table 9-1 is a list of actions that will automatically set the Write Enable Latch to zero when successfully executed. If an

instruction is not successfully executed, for example if the CS pin is brought high before an integer multiple of 8 bits is

clocked, the Write Enable Latch will not be reset.

Table 9-1. Write Enable Latch to Zero

9.2 WRDI (Write Disable):

To protect the device against inadvertent writes, the Write Disable instruction disables all write modes. Since the Write

Enable Latch is automatically reset after each successful write instruction, it is not necessary to issue a WRDI instruction

following a write instruction. The WRDI instruction is independent of the status of the WP pin. The WRDI sequence is

shown in Figure 9-2.

Figure 9-2. WRDI Sequenc e (0 4h )

9.3 RDSR (Read Status Register):

The Read Status Register instruction provides access to the Status Register and indication of write protection status of

the memory.

Instruction/Operation

Power-Up

WRDI (Write Disable)

WR (Write)

PERS (Page Erase)

CERS (Chip Erase)

PD (Power Down)

SDI

SCK

SDO

01234567

HI-Z

00000110

SDI

SCK

SDO

01234567

HI-Z

0000010 0

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Caution: The Write In Progress (WIP) and Write Enable Latch (WEL) indicate the status of the device. The RDSR sequence is

shown in Figure 9-3.

Figure 9-3. RDSR Sequenc e (0 5h )

9.4 WRSR (Write Status Register):

The Write Status Register (WRSR) instruction allows the user to select one of three levels of protection. The memory

array can be block protected (see Table 8-2) or have no protection at all. The SRWD bit (in conjunction with the WP pin)

sets the write status of the Status Register (see Table 8-1).

Only the BP0, BP1, APDE, LPSE and SRWD bits are writable and are nonvolatile cells. When the WP pin is low, and the

SRWD bit in the Status Register is a one, a zero cannot be written to SRWD to allow the part to be writable. To set the

SRWD bit to zero, the WP pin must be high. The WRSR sequence is shown in Figure 9-4.

Figure 9-4. WRSR Sequence (01h)

9.5 READ (Read Data):

Reading the Adesto RM25C family via the Serial Data Output (SDO) pin requires the following sequence: First the CS

line is pulled low to select the device; then the READ op-code is transmitted via the SDI line, followed by the address to

be read (A15-A0). Although not all 16 address bits are used, a full 2 bytes of address must be transmitted to the device.

For the 64 Kb device, only address A0 to A12 are used; the rest are don't cares and must be set to “0”.

Once the read instruction and address have been sent, any further data on the SDI line will be ignored. The data (D7-D0)

at the specified address is then shifted out onto the SDO line. If only one byte is to be read, the CS line should be driven

high after the byte of data comes out. This completes the reading of one byte of data.

The READ sequence can be automatically continued by keeping the CS low. At the end of the first data byte the byte

address is internally incremented and the next higher address data byte will be shifted out. When the highest address is

reached, the address counter will roll over to the lowest address (00000), thus allowing the entire memory to be read in

one continuous read cycle. The READ sequence is shown in Figure 9-5.

SDI

SCK

SDO

01234 56 7

HI-Z

89101112131415

765 432 10

00000101

WEL WIP

SDI

SCK

SDO

012 456

HI-Z

3 7 8 9 10 11 12 13 14 15

7653210

STATUSINSTRUCTION

00000001 4

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Figure 9-5. Single Byte READ Sequence (03h)

9.6 FREAD (Fast Read Data):

The Adesto RM25C family also includes the Fast Read Data command, which facilitates reading memory data at higher

clock rates, up to 10 MHz. After the CS line is pulled low to select the device, the FREAD op-code is transmitted via the

SDI line. This is followed by the 2-byte address to be read (A15-A0) and then a 1-byte dummy. For the 64 Kbit device,

only address A0 to A12 are used; the rest are don't cares and must be set to "0".

The next 8 bits transmitted on the SDI are dummy bits. The data (D7-D0) at the specified address is then shifted out onto

the SDO line. If only one byte is to be read, the CS line should be driven high after the data comes out. This completes

the reading of one byte of data.

The FREAD sequence can be automatically continued by keeping the CS low. At the end of the first data byte, the byte

address is internally incremented and the next higher address data byte is then shifted out. When the highest address is

reached, the address counter rolls over to the lowest address (00000), allowing the entire memory to be read in one

continuous read cycle. The FREAD sequence is shown in Figure 9-6.

Figure 9-6. Two Byte FREAD Sequence (0Bh)

SDI

SCK

01 2 4 56

HI-Z

3 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31

15 14 13 3210

76543210

2 BYTE ADDRESS

DATA OUT

INSTRUCTION

00000011

SDI

SCK

01 2 4 5 6

HI-Z

37891020 21 22

24 25 26 27 28 29 30 31

15 14 13 3210

76543210

2 BYTE ADDRESS

DATA BYTE 1 OUT

INSTRUCTION

00001011

SDO

65432107

DUMMY BYTE

32 33 34 35 36 37 38 39

7654 3210

DATA BYTE 2 OUT

40 41 42 43 44 45 46 47

SDI

SCK

SDO

HI-Z

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9.7 WRITE (WR):

The Write (WR) instruction allows bytes to be written to the memory. But first, the device must be write-enabled via the

WREN instruction. The CS pin must be brought high after completion of the WREN instruction; then the CS pin can be

brought back low to start the WR instruction. The CS pin going high at the end of the WR input sequence initiates the

internal write cycle. During the internal write cycle, all commands except the RDSR instruction are ignored.

A WR instruction requires the following sequence: After the CS line is pulled low to select the device, the WR op-code is

transmitted via the SDI line, followed by the byte address (A15-A0) and the data (D7-D0) to be written. For the 64 Kb

device, only address A0 to A12 are used; the rest are don't cares and must be set to “0”. The internal write cycle

sequence will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK

low-time immediately after clocking in the D0 (LSB) data bit.

The Write In Progress status of the device can be determined by initiating a Read Status Register (RDSR) instruction

and monitoring the WIP bit. If the WIP bit (Bit 0) is a “1”, the write cycle is still in progress. If the WIP bit is “0”, the write

cycle has ended. Only the RDSR instruction is enabled during the write cycle. The sequence of a one-byte WR is shown

in Figure 9-7.

Figure 9-7. One Byte Write Sequence (0Bh)

The Adesto RM25C family is capable of a 32-byte write operation.

For the RM25C64C-L: After each byte of data is received, the six low-order address bits (A5-A0) are internally

incremented by one; the high-order bits of the address will remain constant. All transmitted data that goes beyond the

end of the current page are written from the start address of the same page (from the address whose 6 least significant

bits [A5-A0] are all zero). If more than 32 bytes are sent to the device, previously latched data are discarded and the last

32 data bytes are ensured to be written correctly within the same page. If less than 32 data bytes are sent to the device,

they are correctly written at the requested addresses without having any effects on the other bytes of the same page.

The Adesto RM25C64C-L is automatically returned to the write disable state at the completion of a program cycle. The

sequence for a 32byte WR is shown in Figure 9-8. Note that the Multi-Byte Write operation is internally executed by

sequentially writing the words in the Page Buffer.

NOTE: If the device is not write enabled (WREN) previous to the Write instruction, the device will ignore the write instruction and

return to the standby state when CS is brought high. A new CS falling edge is required to re initiate the serial communication.

Product Density Page Size (bytes)

RM25C64C-L 64 Kbit 32

SDI

SCK

012 456

HI-Z

3 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31

15 14 13 321076543210

2 BYTE ADDRESS DATA ININSTRUCTION

00000010

SDO

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Figure 9-8. WRITE Sequence (02h)

9.8 PER (Page Erase 32 bytes):

Page Erase sets all bits inside the addressed 32-byte page to a 1. A Write Enable (WREN) instruction is required prior to

a Page Erase. After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch.

The Page Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code, then 2 address

bytes. Any address inside the page to be erased is valid. This means the bottom six bits (A5-A0) of the address are

ignored. Once the address is shifted in, the CS pin is brought high, which initiates the self-timed Page Erase function.

The WIP bit in the Status Register can be read, using the RDSR instruction, to determine when the Page Erase cycle is

complete.

The sequence for the PER is shown in Figure 9-9.

Figure 9-9. PERS Sequence (42h)

9.9 CERS (Chip Erase):

Chip Erase sets all bits inside the device to a 1. A Write Enable (WREN) instruction is required prior to a Chip Erase.

After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch.

The Chip Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code. There are two

different instruction codes for CER, 60h and C7h. Either instruction code will initiate the Chip Erase sequence. No

SDI

SCK

012 456

HI-Z

3 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31

15 14 13 321076543210

2 BYTE ADDRESS DATA BYTE 1INSTRUCTION

00000010

SDO

SDI

SCK

HI-Z

76543210

SDO

76543210

DATA BYTE 2

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

76543210

DATA BYTE 3 DATA BYTE N (N= 32,64)

SDI

SCK

SDO

012 456

HI-Z

3 7 8 9 10 11 20 21 22 23

15 14 13 3210

2 BYTE ADDRESSINSTRUCTION

01000010

RM25C64C-L

DS-RM25C64C-L–097A–3/2016

address bytes are needed. Once the instruction code is shifted in, the CS pin is brought high, which initiates the self-

timed Chip Erase function. The WIP bit in the Status Register can be read, using the RDSR instruction, to determine

when the Chip Erase cycle is complete.

The sequence for the 60h CER instruction is shown in Figure 9-10. The sequence for the C7h CER instruction is shown

in Figure 9-11.

Figure 9-10. CERS Sequence (60h)

Figure 9-11. CERS Sequence (C7h)

9.10 PD (Power Down):

Power Down mode allows the user to reduce the power of the device to its lowest power consumption state.

All instructions given during the Power Down mode are ignored except the Resume from Power down (RES) instruction.

Therefore this mode can be used as an additional software write protection feature.

The Power Down sequence is initiated by bringing the CS pin low; this is followed by the instruction code. Once the

instruction code is shifted in the CS pin is brought high, which initiates the PD mode. The sequence for PD is shown in

Figure 9-12.

Figure 9-12. PD Sequence

SDI

SCK

SDO

01234567

HI-Z

0110000 0

SDI

SCK

SDO

01234567

HI-Z

1100011 1

SDI

SCK

SDO

01234567

HI-Z

1011100 1

RM25C64C-L

DS-RM25C64C-L-097A–3/2016

9.11 RES (Resume from Power Down):

The Resume from Power Down mode is the only command that will wake the device up from the Power Down mode. All

other commands are ignored.

In the simple instruction command, after the CS pin is brought low, the RES instruction is shifted in. At the end of the

instruction, the CS pin is brought back high.

The rising edge of the SCK clock number 7 (8th rising edge) initiates the internal RES instruction. The device becomes

available for Read and Write instructions 75μS after the 8th rising edge of the SCK (tPUD, see AC Characteristics). The

sequence for simple RES instruction is shown in Figure 9-13.

Figure 9-13. Simple RES Sequence (ABh)

9.12 UDPD (Ultra-Deep Power Down):

The Ultra-Deep Power Down mode allows the device to further reduce its energy consumption compared to the existing

Standby and Power Down modes by shutting down additional internal circuitry. When the device is in the Ultra-Deep

Power Down mode, all commands including the Read Status Register and Resume from Deep Power Down commands

will be ignored. Since all commands will be ignored, the mode can be used as an extra protection mechanism against

inadvertent or unintentional program and erase operations. Entering the Ultra-Deep Power Down mode is accomplished

by simply asserting the CS pin, clocking in the opcode 79h, and then deasserting the CS pin. Any additional data clocked

into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Ultra-Deep

Power Down mode within the maximum time of tEUDPD.

The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device will abort the operation

and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode

after a power cycle. The Ultra-Deep Power Down command will be ignored if an internally self-timed operation such as a

program or erase cycle is in progress. The sequence for UDPD is shown in Figure 9-14.

SDI

SCK

SDO

012 456

HI-Z

INSTRUCTION

10101011

RPD

RM25C64C-L

DS-RM25C64C-L–097A–3/2016

Figure 9-14. Ultra-Deep Power Down (79h)

9.13 Exit Ultra-Deep Power Down

To exit from the Ultra-Deep Power Down mode, any one of three operations can be performed:

9.13.1 Chip Select Toggle

The CS pin must simply be pulsed by asserting the CS pin, waiting the minimum necessary tCSLU time, and then

deasserting the CS pin again. To facilitate simple software development, a dummy byte opcode can also be entered

while the CS pin is being pulsed; the dummy byte opcode is simply ignored by the device in this case. After the CS pin

has been deasserted, the device will exit from the Ultra-Deep Power Down mode and return to the standby mode within

a maximum time of tXUDPD If the CS pin is reasserted before the tXUDPD time has elapsed in an attempt to start a new

operation, then that operation will be ignored and nothing will be performed.

Figure 9-15. Exit Ultra-Deep Pow er Down (Chip Select Togg le)

9.13.2 Chip Select Low

By asserting the CS pin, waiting the minimum necessary tXUDPD time, and then clocking in the first bit of the next Opcode

command cycle. If the first bit of the next command is clocked in before the tXUDPD time has elapsed, the device will exit

Ultra Deep Power Down, however the intended operation will be ignored.

SCK

MSB

ICC

2310

6754

Opcode

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

Standby Mode Current

tEUDPD

1111001

ICC

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

Standby Mode Current

XUDPD

tCSLU

RM25C64C-L

DS-RM25C64C-L-097A–3/2016

Figure 9-16. Exit Ultra-Deep Pow er Down (Chip Select Low)

9.13.3 Power Cycling

The device can also exit the Ultra Deep Power Mode by power cycling the device. The system must wait for the device to

return to the standby mode before normal command operations can be resumed. Upon recovery from Ultra Deep Power

Down all internal registers will be at there Power-On default state.

10. Typical Characteristics

Figure 10-1. Icc4 , Auto Powerdown

ICC

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

XUDPD

Average Icc Standby (Icc4, Auto Powerdown, uA) vs Temperature (C), by Vcc

-40 023 55 85

Temperature

Voltage

3.60 3.30 2.70 1.65

Current

11.5

10.5

9.5

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

RM25C64C-L

DS-RM25C64C-L–097A–3/2016

Figure 10-2. Icc4, Mode 0

Figure 10-3. Icc4, Mode 1

Average Icc Standby (Icc4, Mode 0, uA) vs Temperature (C), by V cc

-40 023 55 85

3.60 3.30

2.70

1.65

Temperature

Voltage

110

105

100

Current

Average Icc Standby (Icc4, Mode 1, uA) vs Temperature (C), by Vcc

-40 023 55 85

Temperature

Voltage 3.60

3.30

2.70

1.65

110

105

100

Current

RM25C64C-L

DS-RM25C64C-L-097A–3/2016

Figure 10-4. Icc5

Figure 10-5. Icc6

Temperature

Average PD (Icc5) Current (uA) vs Temperature (C), Lines by Vcc

-40 023 55 85

Voltage

3.60 3.30 2.70 1.65

11.5

10.5

9.5

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

Current

A v erage UDPD (Icc6) Current (uA) vs Temperature (C), Lines by Vcc

-40 023 55 85

Temperature

Voltage

3.60 3.30 2.70 1.65

11.5

10.5

9.5

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

Current

RM25C64C-L

DS-RM25C64C-L–097A–3/2016

11. Ordering Information

11.1 Ordering Detail

11.2 Ordering Codes

RM25C64C-LSNI-T

Device Type

Shipping Carrier Option

RM25C = SPI serial access EEPROM B = Tube

T = Tape & Reel

Density Grade & Temperature

I = Green, NiPd Au lead finish,

Industrial temperature (-40-85°C)

Device/Die Revision

Package Option

SN = 8 lead 0.150” SOIC, Narrow

TA = 8 lead TSSOP

MA =8 pad 2 x 3 x 0.6mm UDFN

CS = Wafer Level Chip Scale

Operating Voltage

L = 1.65V to 3.6V

64 = 64Kbit

Ordering Code Package Density Operating

Voltage fSCK

Device

Grade Ship

Carrier Qty. Carrier

RM25C64C-LSNI-B

64 Kbit 1.65V to 3.6V 10 MHz

Commercial

(-40°C to

85°C)

Tube 100

RM25C64C-LSNI-T

Reel 4000

RM25C64C-LTAI-B

Tube 100

RM25C64C-LTAI-T

Reel 4000

RM25C64C-LMAI-T

MA Reel 5000

RM25C64C-LCSI-T (1)

CS6 Contact Factory

1. Contact Adesto for availability.

Package Type

SN 8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

TA 8-lead 3 x 4.4 mm, Thin Shrink Small Outline Package

MA 8-pad, 2 x 3 x 0.6mm, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN)

CS6 6-Ball Wafer Level Chip Scale Package

RM25C64C-L

DS-RM25C64C-L-097A–3/2016

12. Package Information

12.1 SN (JEDEC SOIC)

DRAWING NO. REV. TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.05

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

ØØ 0° – 8°

ØØ

TOP VIEWTOP VIEW

E1E1

END VIEW

A1A1

SIDE VIEWSIDE VIEW

Package Drawing Contact:

contact@adestotech.com

8S1 G

8/20/14

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

for proper dimensions, tolerances, datums, etc.

8S1, 8-lead (0.150” Wide Body), Plastic Gull

Wing Small Outline (JEDEC SOIC) SWB

RM25C64C-L

DS-RM25C64C-L–097A–3/2016

12.2 MA – 2 x 3 UDFN

TITLE DRAWING NO.GPC REV.

Package Drawing Contact:

contact@adestotech.com

8MA3YCQ GT

8MA3, 8-pad, 2 x 3 x 0.6 mm Body, 0.5 mm Pitch,

1.6 x 0.2 mm Exposed Pad, Saw Singulated

Thermally Enhanced Plastic Ultra Thin Dual

Flat No Lead Package (UDFN/USON)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX

A 0.45 0.60

A1 0.00 0.05

A3 0.150 REF

b 0.20 0.30

D 2.00 BSC

D2 1.50 1.60 1.70

E 3.00 BSC

E2 0.10 0.20 0.30

e 0.50 BSC

L 0.40 0.45 0.50

L1 0.00 0.10

L3 0.30 0.50

eee – – 0.08

8/26/14

Notes: 1. All dimensions are in mm. Angles in degrees.

2. Bilateral coplanarity zone applies to the exposed heat

sink slug as well as the terminals.

PIN 1 ID

678

eee

L3 L

Chamfer or half-circle

notch for Pin 1 indicator.

RM25C64C-L

DS-RM25C64C-L-097A–3/2016

12.3 TA-TSSOP

DRAWING NO. REV. TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A - - 1.20

A1 0.05 - 0.15

A2 0.80 1.00 1.05

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

C 0.09 - 0.20

Side View

End View

Top View

Pin 1 indicator

this corner

Notes: 1. This drawing is for general information only. Refer to JEDEC

Drawing MO-153, Variation AA, for proper dimensions,

tolerances, datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate

burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15mm (0.006in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions.

Inter-lead Flash and protrusions shall not exceed 0.25mm

(0.010in) per side.

4. Dimension b does not include Dambar protrusion. Allowable

Dambar protrusion shall be 0.08mm total in excess of the b

dimension at maximum material condition. Dambar cannot be

located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8X E

12/8/11

TA, 8-lead 4.4mm Body, Plastic Thin

Shrink Small Outline Package (TSSOP) TNR

Package Drawing Contact:

contact@adestotech.com

RM25C64C-L

DS-RM25C64C-L–097A–3/2016

12.4 CS6- 6-Ball WLCSP

DRAWING NO. REV. TITLE GPC

2/29/16

CS-6, 6-ball (3x3 Array) Wafer Level Chip Scale

Package, WLCSP GCL

Package Drawing Contact:

contact@adestotech.com

CS6-SP 0A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN TYP MAX NOTE

A 0.35

A1 0.08

A2 0.27

E 1.28

e 0.4

d 0.8

d2 0.4

D 1.47

TOP VIEW SIDE VIEW BALL SIDE

Pin Assignment Matrix

A B C

VCC

SDI

Øb

Pin 1

SCK

GND

ACB

0.015 C

4X 0.075 C

C0.015 C

0.05 CAB

* Dimensions are NOT to scale.

SDO

PCB Land Pad Diameter Recommendation:

Description Value

Non-soldermask defined (NSMD)

Soldermask defined (SMD)

225um

250um

RM25C64C-L

DS-RM25C64C-L-097A–3/2016

13. Revision History

Doc. Rev. Date Comments

RM25C64C-L-097A 3/2016 Initial document release. Document status changed to Preliminary.

Corporate Office

California | USA

Adesto Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: (+1) 408.400.0578

Email: contact@adestotech.com

Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms

and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications

detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the

Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.

For Release Only Under Non-Disclosure Agreement (NDA)

Adesto®, the Adesto logo, CBRAM®, Mavriq™ and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their

respective owners.