CY8C20XX6A/S
1.8 V Programmable CapSense® Controller
with SmartSense™ Auto-tuning
1–33 Buttons, 0–6 Sliders
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-54459 Rev. *Y Revised May 18, 2017
1.8 V Progra mmable CapS ense® Contro ller with SmartSense™ Auto-tun ing 1–33 Buttons, 0–6 Sliders
Features
■Low power CapSense® block with SmartSense Auto-tuning
❐Patented CSA_EMC, CSD sensing algorithms
❐SmartSense_EMC Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process Low
average power consumption – 28 µA/sensor in run time
(wake-up and scan once every 125 ms)
■Powerful Harvard-architecture processor
❐M8C CPU with a max speed of 24 MHz
■Operating Range: 1.71 V to 5.5 V
❐Standby Mode 1.1 μA (Typ)
❐Deep Sleep 0.1 μA (Typ)
■Operating Temperature range: –40 °C to +85 °C
■Flexible on-chip memory
❐8 KB flash, 1 KB SRAM
❐16 KB flash, 2 KB SRAM
❐32 KB flash, 2 KB SRAM
❐Read while Write with EEPROM emulation
❐50,000 flash erase/write cycles
❐In-system programming simplifies manufacturing process
■Four Clock Sources
❐Internal main oscillator (IMO): 6/12/24 MHz
❐Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐External 32 KHz Crystal Oscillator
❐External Clock Input
■Programmable pin configurations
❐Up to 36 general-purpose I/Os (GPIOs) configurable as
buttons or sliders
❐Dual mode GPIO (Analog inputs and Digital I/O supported)
❐High sink current of 25 mA per GPIO
• Max sink current 120 mA for all GPIOs
❐Source Current
• 5 mA on ports 0 and 1
• 1 mA on ports 2,3 and 4
❐Configurable internal pull-up, high-Z and open drain modes
❐Selectable, regulated digital I/O on port 1
❐Configurable input threshold on port 1
■Versatile Analog functions
❐Internal analog bus supports connection of multiple sensors
to form ganged proximity sensor
❐Internal Low-Dropout voltage regulator for high power supply
rejection ratio (PSRR)
■Full-Speed USB
❐12 Mbps USB 2.0 compliant
■Additional system resources
❐I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐Configurable up to 12 MHz SPI master and slave
❐Three 16-bit timers
❐Watchdog and sleep timers
❐Integrated supervisory circuit
❐10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
❐Two general-purpose high speed, low power analog
comparators
■Complete development tools
❐Free development tool (PSoC Designer™)
■Sensor and Package options
❐10 Sensors – QFN 16, 24
❐16 Sensors – QFN 24
❐22 / 25 Sensors – QFN 32
❐24 Sensors - WLCSP 30
❐31 Sensors – SSOP 48
❐33 Sensors – QFN 48
Errata: For information on silicon errata, see “Errata” on page 46. Details include trigger conditions, devices affected, and proposed workaround.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 2 of 53
Logic Block Diagram
CAPSENSE
SYSTEM
1K/2K
SRAM
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
Internal Low Speed Oscillator (ILO)
6/12/24 MHz Internal Main Oscillator
(IMO)
PSoC CORE
CPU Core (M8C)
Supervisory ROM (SROM) 8K/16K/32K Flash
Nonvolatile Memory
SYSTEM RESOURCES
SYSTEM BUS
Analog
Reference
SYSTEM BUS
Port 3 Port 2 Port 1 Port 0
CapSense
Module
Global Analog Interconnect
1.8/2.5/3V
LDO
Analog
Mux
Two
Comparators
I2C
Slave
SPI
Master/
Slave
POR
and
LVD
USB System
Resets
Internal
Voltage
References
Three 16-Bit
Programmable
Timers
PWRSYS
(Regulator)
Port 4
Digital
Clocks
[1]
Note
1. Internal voltage regulator for internal circuitry
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 3 of 53
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA92181, Resources Available for CapSense® Controllers. Following is an abbreviated list for CapSense devices:
■Overview: CapSense Portfolio, CapSense Roadmap
■Product Selectors: CapSense, CapSense Plus, CapSense
Express, PSoC3 with CapSense, PSoC5 with CapSense,
PSoC4. In addition, PSoC Designer offers a device selection
tool at the time of creating a new project.
■Application notes: Cypress offers CapSense application notes
covering a broad range of topics, from basic to advanced level.
Recommended application notes for getting started with
CapSense are:
❐AN64846: Getting Started With CapSense
❐AN73034: CY8C20xx6A/H/AS CapSense® Design Guide
❐AN2397: CapSense® Data Viewing Tools
■Technical Reference Manual (TRM):
❐PSoC® CY8C20xx6A/AS/L Family Technical Reference
Manual
■Development Kits:
❐CY3280-20x66 Universal CapSense Controller Kit features
a predefined control circuitry and plug-in hardware to make
prototyping and debugging easy. Programming and
I2C-to-USB Bridge hardware are included for tuning and data
acquisition.
❐CY3280-BMM Matrix Button Module Kit consists of eight
CapSense sensors organized in a 4x4 matrix format to form
16 physical buttons and eight LEDs. This module connects
to any CY3280 Universal CapSense Controller Board,
including CY3280-20x66 Universal CapSense Controller.
❐CY3280-BSM Simple Button Module Kit consists of ten
CapSense buttons and ten LEDs. This module connects to
any CY3280 Universal CapSense Controller Board, including
CY3280-20x66 Universal CapSense Controller.
The CY3217-MiniProg1 and CY8CKIT-002 PSoC® MiniProg3
device provides an interface for flash programming.
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of systems based on CapSense (see Figure 1). With PSoC Designer, you can:
1. Drag and drop User Modules to build your hardware system
design in the main design workspace
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Designer IDE C compiler
3. Configure User Module
4. Explore the library of user modules
5. Review user module datasheets
Figure 1. PSoC Designer Features
12
3
4
5
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 4 of 53
Contents
PSoC® Functional Overview ............................................5
PSoC Core .................................................................. 5
CapSense System ....................................................... 5
Additional System Resources ..................................... 6
Getting Started ..................................................................7
CapSense Design Guides ........................................... 7
Silicon Errata ...............................................................7
Development Kits ........................................................7
Training .......................................................................7
CYPros Consultants ....................................................7
Solutions Library ..........................................................7
Technical Support .......................................................7
Development Tools .......................................................... 8
PSoC Designer Software Subsystems ........................ 8
Designing with PSoC Designer .......................................9
Select User Modules ...................................................9
Configure User Modules ..............................................9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pinouts ............................................................................10
16-pin QFN (10 Sensing Inputs)[3, 4] ....................... 10
24-pin QFN (17 Sensing Inputs) [8] ...........................11
24-pin QFN (15 Sensing Inputs (With USB)) [13] ...... 12
30-ball WLCSP (24 Sensing Inputs) [18] ...................13
32-pin QFN (25 Sensing Inputs) [22] .........................14
32-pin QFN (22 Sensing Inputs (With USB)) [27] ...... 15
48-pin SSOP (31 Sensing Inputs) [32] ...................... 16
48-pin QFN (33 Sensing Inputs) [36] .........................17
48-pin QFN (33 Sensing Inputs (With USB)) [41] ...... 18
48-pin QFN (OCD) (33 Sensing Inputs) [46] .............19
Electrical Specifications ................................................20
Absolute Maximum Ratings ....................................... 20
Operating Temperature .............................................20
DC Chip-Level Specifications ....................................21
DC GPIO Specifications ............................................ 22
DC Analog Mux Bus Specifications ........................... 24
DC Low Power Comparator Specifications ...............24
Comparator User Module
Electrical Specifications ....................................................25
ADC Electrical Specifications ....................................25
DC POR and LVD Specifications .............................. 26
DC Programming Specifications ............................... 26
DC I2C Specifications ............................................... 27
DC Reference Buffer Specifications .......................... 27
DC IDAC Specifications ............................................ 27
AC Chip-Level Specifications .................................... 28
AC GPIO Specifications ............................................ 29
AC Comparator Specifications .................................. 30
AC External Clock Specifications .............................. 30
AC Programming Specifications ................................ 31
AC I2C Specifications ................................................ 32
Packaging Information ................................................... 35
Thermal Impedances ................................................. 38
Capacitance on Crystal Pins ..................................... 38
Solder Reflow Specifications ..................................... 38
Development Tool Selection ......................................... 39
Software .................................................................... 39
Development Kits ...................................................... 39
Evaluation Tools ........................................................ 39
Device Programmers ................................................. 39
Accessories (Emulation and Programming) .............. 40
Third Party Tools ....................................................... 40
Build a PSoC Emulator into Your Board .................... 40
Ordering Information ...................................................... 41
Ordering Code Definitions ......................................... 43
Acronyms ........................................................................ 44
Reference Documents .................................................... 44
Document Conventions ................................................. 44
Units of Measure ....................................................... 44
Numeric Naming ........................................................ 45
Glossary .......................................................................... 45
Errata ............................................................................... 46
Qualification Status ................................................... 46
Errata Summary ........................................................ 46
Document History Page ................................................. 49
Sales, Solutions, and Legal Information ...................... 53
Worldwide Sales and Design Support ....................... 53
Products .................................................................... 53
PSoC®Solutions ....................................................... 53
Cypress Developer Community ................................. 53
Technical Support ..................................................... 53
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 5 of 53
PSoC® Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
■The Core
■CapSense Analog System
■System Resources (including a full-speed USB port).
A common, versatile bus allows connection between I/O and the
analog system.
Each CY8C20XX6A/S PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 GPIO are also included. The GPIO
provides access to the MCU and analog mux.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit
Harvard-architecture microprocessor.
CapSense System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to
33 inputs [2]. Capacitive sensing is configurable on each GPIO
pin. Scanning of enabled CapSense pins are completed quickly
and easily across multiple ports.
SmartSense
SmartSense is an innovative solution from Cypress that removes
manual tuning of CapSense applications. This solution is easy to
use and provides a robust noise immunity. It is the only
auto-tuning solution that establishes, monitors, and maintains all
required tuning parameters. SmartSense allows engineers to go
from prototyping to mass production without re-tuning for
manufacturing variations in PCB and/or overlay material
properties.
SmartSense_EMC
In addition to the SmartSense auto tuning algorithm to remove
manual tuning of CapSense applications, SmartSense_EMC
user module incorporates a unique algorithm to improve
robustness of capacitive sensing algorithm/circuit against high
frequency conducted and radiated noise. Every electronic device
must comply with specific limits for radiated and conducted
external noise and these limits are specified by regulatory bodies
(for example, FCC, CE, U/L and so on). A very good PCB layout
design, power supply design and system design is a mandatory
for a product to pass the conducted and radiated noise tests. An
ideal PCB layout, power supply design or system design is not
often possible because of cost and form factor limitations of the
product. SmartSense_EMC with superior noise immunity is well
suited and handy for such applications to pass radiated and
conducted noise test.
Figure 2. CapSense System Block Diagram
IDAC
Reference
Buffer
Vr
Cinternal
Analog Global Bus
Cap Sense Counters
Comparator
Mux
Mux Refs
CapSense
Clock Select Oscillator
CSCLK
IMO
CS1
CS2
CSN
Cexternal (P0[1]
or P0[3])
Note
2. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulator capacitor.
CY8C20XX6A/S
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Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■Complex capacitive sensing interfaces, such as sliders and
touchpads.
■Chip-wide mux that allows analog input from any I/O pin.
■Crosspoint connection between any I/O pin combinations.
Additional System Resources
System resources provide additional capability, such as
configurable USB and I2C slave, SPI master/slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
These system resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. The merits of each system
resource are listed here:
■The I2C slave/SPI master-slave module provides
50/100/400 kHz communication over two wires. SPI
communication over three or four wires runs at speeds of
46.9 kHz to 3 MHz (lower for a slower system clock).
■Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced
power-on-reset (POR) circuit eliminates the need for a system
supervisor.
■An internal reference provides an absolute reference for
capacitive sensing.
■A register-controlled bypass mode allows the user to disable
the LDO regulator.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 7 of 53
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the
CY8C20XX6A/S PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
CapSense Design Guides
Design Guides are an excellent introduction to the wide variety
of possible CapSense designs. They are located at
www.cypress.com/go/CapSenseDesignGuides.
Refer Getting Started with CapSense design guide for
information on CapSense design and CY8C20XX6A/H/AS
CapSense® Design Guide for specific information on
CY8C20XX6A/AS CapSense controllers.
Silicon Errata
Errata documents known issues with silicon including errata
trigger conditions, scope of impact, available workarounds and
silicon revision applicability. Refer to Silicon Errata for the PSoC®
CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families
available at http://www.cypress.com/?rID=56239 for errata
information on CY8C20xx6A/AS/H family of device. Compare
errata document with datasheet for a complete functional
description of device.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 8 of 53
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■Extensive user module catalog
■Integrated source-code editor (C and assembly)
■Free C compiler with no size restrictions or time limits
■Built-in debugger
■In-circuit emulation
■Built-in support for communication interfaces:
❐Hardware and software I2C slaves and masters
❐Full-speed USB 2.0
❐Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC’s resources for an application.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
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Document Number: 001-54459 Rev. *Y Page 9 of 53
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
6. Select user modules.
7. Configure user modules.
8. Organize and connect.
9. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules”. User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All of the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information that you may need to
successfully implement your design.
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It lets you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
CY8C20XX6A/S
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Pinouts
The CY8C20XX6A/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are
not capable of Digital I/O.
16-pin QFN (10 Sensing Inputs)[3, 4]
Table 1. Pin Definitions – CY8C20236A, CY8C20246A, CY8C20246AS PSoC Device
Pin
No.
Type Name Description Figure 3. CY8C20236A, CY8C20246A, CY8C20246AS
Digital Analog
1I/O IP2[5] Crystal output (XOut)
2I/O IP2[3] Crystal input (XIn)
3IOHR IP1[7] I2C SCL, SPI SS
4IOHR IP1[5] I2C SDA, SPI MISO
5IOHR IP1[3] SPI CLK
6IOHR IP1[1] ISSP CLK[5], I2C SCL, SPI MOSI
7Power VSS Ground connection[7]
8IOHR IP1[0] ISSP DATA[5], I2C SDA, SPI CLK[6]
9IOHR IP1[2]
10 IOHR IP1[4] Optional external clock (EXTCLK)
11 Input XRES Active high external reset with
internal pull-down
12 IOH IP0[4]
13 Power VDD Supply voltage
14 IOH IP0[7]
15 IOH IP0[3] Integrating input
16 IOH IP0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
QFN
( Top View)
AI, XOut, P2[5]
AI , I2 C SCL, SPI SS, P1[7]
AI , I2 C SDA, SPI MISO, P1[5]
AI, SPI CL
K,P1[3]
1
2
3
4
11
10
9
16
15
14
13
P0[3], AI
P0[7], AI
Vdd
P0[4] , AI
AI, ISSP CLK, SPI MOSI, P1[1]
AI, ISSP DATA , I2C SDA, SPI CL
K,P1[0]
P1[2] , AI
AI, XIn, P2[3]
P1[4] , EXTCLK, AI
XRES
P0[1], AI
Vss
12
5
6
7
8
[5]
[5,6]
Notes
3. 13 GPIOs = 10 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
4. No Center Pad.
5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
6. Alternate SPI clock.
7. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 11 of 53
24-pin QFN (17 Sensing Inputs) [8]
Table 2. Pin Definitions – CY8C20336A, CY8C20346A, CY8C20346AS [9]
Pin
No.
Type Name Description Figure 4. CY8C20336A, CY8C20346A, CY8C20346AS
Digital Analog
1I/O IP2[5] Crystal output (XOut)
2I/O IP2[3] Crystal input (XIn)
3I/O IP2[1]
4 IOHR I P1[7] I2C SCL, SPI SS
5 IOHR I P1[5] I2C SDA, SPI MISO
6 IOHR I P1[3] SPI CLK
7 IOHR I P1[1] ISSP CLK[10], I2C SCL, SPI
MOSI
8NC No connection
9Power VSS Ground connection[12]
10 IOHR I P1[0] ISSP DATA[10], I2C SDA, SPI
CLK[11]
11 IOHR I P1[2]
12 IOHR I P1[4] Optional external clock input
(EXTCLK)
13 IOHR I P1[6]
14 Input XRES Active high external reset with
internal pull-down
15 I/O IP2[0]
16 IOH IP0[0]
17 IOH IP0[2]
18 IOH IP0[4]
19 IOH IP0[6]
20 Power VDD Supply voltage
21 IOH IP0[7]
22 IOH IP0[5]
23 IOH IP0[3] Integrating input
24 IOH IP0[1] Integrating input
CP Power VSS
Center pad must be
connected to ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI, ISSP DATA2, I2C SDA, SPI CLK, P1[0]
QFN
(Top View)
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[2], AI
P0[0], AI
24
23
22
21
20
19
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[4], AI
7
8
9
10
11
12
SPI MOSI, P1[1]
AI, P1[2]
AI, P2[1]
NC
P1[6], AI
AI, EXTCLK, P1[4]
XRES
P2[0], AI
P0[6], AI
AI, ISSP CLK2, I2C SCL
P0[1], AI
Vss
AI, XOut, P2[5]
AI, XIn, P2[3]
[10,
Notes
8. 20 GPIOs = 17 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
9. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
10. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
11. Alternate SPI clock.
12. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 12 of 53
24-pin QFN (15 Sensing Inputs (With USB)) [13]
Table 3. Pin Definitions – CY8C20396A [14]
Pin
No.
Type Name Description Figure 5. CY8C20396A
Digital Analog
1I/O IP2[5]
2I/O IP2[3]
3I/O IP2[1]
4 IOHR I P1[7] I2C SCL, SPI SS
5 IOHR I P1[5] I2C SDA, SPI MISO
6 IOHR I P1[3] SPI CLK
7 IOHR I P1[1] ISSP CLK[15], I2C SCL, SPI
MOSI
8PowerVSS Ground[17]
9I/O ID+ USB D+
10 I/O ID- USB D-
11 Power VDD Supply
12 IOHR I P1[0] ISSP DATA[15], I2C SDA, SPI
CLK[16]
13 IOHR I P1[2]
14 IOHR I P1[4] Optional external clock input
(EXTCLK)
15 IOHR I P1[6]
16 RESET INPUT XRES Active high external reset with
internal pull-down
17 IOH IP0[0]
18 IOH IP0[2]
19 IOH IP0[4]
20 IOH IP0[6]
21 IOH IP0[7]
22 IOH IP0[5]
23 IOH IP0[3] Integrating input
24 IOH IP0[1] Integrating input
CP Power VSS
Center pad must be connected
to Ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
P0[7], AI
AI, I2C SDA , SPI MISO, P1[5]
D-
QFN
(Top View)
AI, I 2 C SCL, SPI SS, P1[7]
AI, SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[0], AI
XRES
24
23
22
21
20
19
P0[3], AI
P0[5]
P0[6], AI
P0[2], AI
7
8
9
10
11
12
AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1]
VDD
P2[1] , A I
Vss
P1[2 ], AI
AI, ISSP DATA,I2C SDA, SPI CLK, P1[0]
P1[4] , AI, EXTCLK
P1[6], AI
P0[4], AI
P0[ 1], AI
D+
P2[5], AI
P2[3], AI
, AI
[15,
[1
Notes
13. 20 GPIOs = 15 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.
14. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
15. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
16. Alternate SPI clock.
17. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 13 of 53
30-ball WLCSP (24 Sensing Inputs) [18]
Table 4. Pin Definitions – CY8C20766A, CY8C20746A 30-ball WLCSP
Pin
No.
Type Name Description
Digital Analog
A1 IOH I P0[2] Figure 6. CY8C20766A 30-ball WLCSP
A2 IOH I P0[6] Bottom View
Top View
A3 Power VDD Supply voltage
A4 IOH I P0[1] Integrating Input
A5 I/O I P2[7]
B1 I/O I P2[6]
B2 IOH I P0[0]
B3 IOH I P0[4]
B4 IOH I P0[3] Integrating Input
B5 I/O I P2[5] Crystal Output (Xout)
C1 I/O I P2[2]
C2 I/O I P2[4]
C3 IOH I P0[7]
C4 IOH I P0[5]
C5 I/O I P2[3] Crystal Input (Xin)
D1 I/O I P2[0]
D2 I/O I P3[0]
D3 I/O I P3[1]
D4 I/O I P3[3]
D5 I/O I P2[1]
E1 Input XRES Active high external reset with
internal pull-down
E2 IOHR I P1[6]
E3 IOHR I P1[4] Optional external clock input
(EXT CLK)
E4 IOHR I P1[7] I2C SCL, SPI SS
E5 IOHR I P1[5] I2C SDA, SPI MISO
F1 IOHR I P1[2]
F2 IOHR I P1[0] ISSP DATA[19], I2C SDA, SPI
CLK[20]
F3 Power VSS Supply ground[21]
F4 IOHR I P1[1] ISSP CLK[19], I2C SCL, SPI
MOSI
F5 IOHR I P1[3] SPI CLK
54321
A
B
C
D
E
F
12345
B
C
D
E
F
A
Notes
18. 27 GPIOs = 24 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
19. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
20. Alternate SPI clock.
21. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 14 of 53
32-pin QFN (25 Sensing Inputs) [22]
Table 5. Pin Definitions – CY8C20436A, CY8C20446A, CY8C20446AS, CY8C20466A, CY8C20466AS[23]
Pin
No.
Type Name Description Figure 7. CY8C20436A, CY8C20446A, CY8C20446AS,
CY8C20466A, CY8C20466AS
Digital Analog
1IOH IP0[1] Integrating input
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O IP2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP3[3]
7I/O IP3[1]
8IOHR IP1[7] I2C SCL, SPI SS
9IOHR IP1[5] I2C SDA, SPI MISO
10 IOHR IP1[3] SPI CLK.
11 IOHR IP1[1] ISSP CLK[24], I2C SCL, SPI MOSI.
12 Power VSS Ground connection[26]
13 IOHR IP1[0] ISSP DATA[24], I2C SDA,
SPI CLK[25]
14 IOHR IP1[2]
15 IOHR IP1[4] Optional external clock input
(EXTCLK)
16 IOHR IP1[6]
17 Input XRES Active high external reset with
internal pull-down
18 I/O IP3[0]
19 I/O IP3[2]
20 I/O IP2[0]
21 I/O IP2[2]
22 I/O IP2[4]
23 I/O IP2[6]
24 IOH IP0[0]
25 IOH IP0[2]
26 IOH IP0[4]
27 IOH IP0[6]
28 Power VDD Supply voltage
29 IOH IP0[7]
30 IOH IP0[5]
31 IOH IP0[3] Integrating input
32 Power VSS Ground connection[26]
CP Power VSS Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI , P0[1]
AI , P2[7]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI , P2[1]
AI , P3[3]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0 [3], AI
P0 [7], AI
Vdd
P0 [6], AI
P0 [4], AI
P0 [2], AI
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
P0[0] , AI
P2[6] , AI
P3[0] , AI
XRES
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
Vss
AI, P 1[ 2]
AI, E XT CLK , P 1[ 4]
AI, P 1[ 6]
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P0 [5], AI
AI
, ISSP CLK , I2C SCL, SPI MOSI, P1[1]
AI,
ISSP DATA , I2C SDA, SPI CLK, P1[0]
[24]
[24]
Notes
22. 28 GPIOs = 25 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
23. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
24. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
25. Alternate SPI clock.
26. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 15 of 53
32-pin QFN (22 Sensing Inputs (With USB)) [27]
Table 6. Pin Definitions – CY8C20496A[28]
Pin
No.
Type Name Description Figure 8. CY8C20496A
Digital Analog
1IOH IP0[1] Integrating Input
2I/O I P2[5] XTAL Out
3I/O I P2[3] XTAL In
4I/O IP2[1]
5IOHR IP1[7] I2C SCL, SPI SS
6IOHR IP1[5]I
2C SDA, SPI MISO
7IOHR IP1[3] SPI CLK
8IOHR IP1[1] ISSP CLK[29], I2C SCL, SPI MOSI
9Power VSS Ground Pin[31]
10 I
I
D+ USB D+
11 D- USB D-
12 Power VDD Power pin
13 IOHR I P1[0] ISSP DATA[29], I2C SDA, SPI
CLKI[30]
14 IOHR IP1[2]
15 IOHR IP1[4] Optional external clock input
(EXTCLK)
16 IOHR IP1[6]
17 Input XRES Active high external reset with
internal pull-down
18 I/O IP3[0]
19 I/O IP3[2]
20 I/O IP2[0]
21 I/O IP2[2]
22 I/O IP2[4]
23 I/O IP2[6]
24 IOH IP0[0]
25 IOH IP0[2]
26 IOH IP0[4]
27 IOH IP0[6]
28 Power VDD Power Pin
29 IOH IP0[7]
30 IOH IP0[5]
31 IOH IP0[3] Integrating Input
32 Power VSS Ground Pin[31]
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI , P0[1]
XTAL OUT, P2[5]
XTAL IN , P2[3]
AI, P2[1]
I2C SCL, SPI SS, P1[7]
I2C SDA, SPI MISO, P1[5]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0 [3], AI
P0 [7], AI
Vdd
P0 [6], AI
P0 [4], AI
P0 [2], AI
SPI CLK , P1[3]
ISSP CLK, I2C SCL, SPI MOSI,P1[1]
P0[0] , AI
P2[6] , AI
P3[0] , AI
XRES
Vss
USB PHY, D+
Vd d
AI, P 1[ 2]
AI, E XT CLK , P 1[ 4]
AI, P 1[ 6]
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P0 [5], AI
USB D-
ISSP, DATA, I2C SDA, SPI CLK, P1[0]
[29, 30]
[29]
Notes
27. 27 GPIOs = 22 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.
28. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
29. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
30. Alternate SPI clock.
31. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 16 of 53
48-pin SSOP (31 Sensing Inputs) [32]
Table 7. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A[33]
Pin
No. Digital Analog Name Description Figure 9. CY8C20536A, CY8C20546A, and CY8C20566A
1IOH IP0[7]
2IOH IP0[5]
3IOH I P0[3] Integrating Input
4IOH I P0[1] Integrating Input
5I/O IP2[7]
6I/O IP2[5] XTAL Out
7I/O I P2[3] XTAL In
8I/O IP2[1]
9NC No connection
10 NC No connection
11 I/O IP4[3]
12 I/O IP4[1]
13 NC No connection
14 I/O IP3[7]
15 I/O IP3[5]
16 I/O IP3[3]
17 I/O IP3[1]
18 NC No connection
19 NC No connection
20 IOHR IP1[7] I2C SCL, SPI SS
21 IOHR IP1[5] I2C SDA, SPI MISO
22 IOHR IP1[3] SPI CLK
23 IOHR IP1[1] ISSP CLK[33], I2C SCL, SPI MOSI
24 VSS Ground Pin[35]
25 IOHR IP1[0] ISSP DATA[33], I2C SDA, SPI
CLK[34]
26 IOHR IP1[2]
27 IOHR IP1[4] Optional external clock input
(EXT CLK)
28 IOHR I P1[6]
29 NC No connection
30 NC No connection
31 NC No connection
32 NC No connection Pin
No. Digital Analog Name Description
33 NC No connection 41 I/O IP2[2]
34 NC No connection 42 I/O IP2[4]
35 XRES Active high external reset with
internal pull-down 43 I/O IP2[6]
36 I/O IP3[0] 44 IOH IP0[0]
37 I/O IP3[2] 45 IOH IP0[2]
38 I/O I P3[4] 46 IOH IP0[4] VREF
39 I/O I P3[6] 47 IOH IP0[6]
40 I/O IP2[0] 48 Power VDD Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
SSOP
AI , P0[7] VDD
AI , P0[5] P0[6] , AI
AI , P0[3] P0[4] , AI
AI P0[1] P0[2] , AI
AI , P2[7] P0[0] , AI
XTALOUT, P2[5] P2[6] , AI
XTALIN, P2[3] P2[4] , AI
AI , P2[1] P2[2] , AI
NC P2[0] , AI
NC P3[6] , AI
AI , P4[3] P3[4] , AI
AI , P4[1] P3[2] , AI
NC P3[0] , AI
AI , P3[7] XRES
AI , P3[5] NC
AI , P3[3] NC
AI , P3[1] NC
NC NC
NC NC
I2 C SCL, SPI SS, P1[7] NC
I2 C SDA, SPI MISO, P1[5 ] P1[6] , AI
SPI CLK, P1[3] P1[4] , EXT CLK
ISSP CLK, I2 C SCL, SPI MOSI, P1[1 ] P1[2] , AI
VSS P1[0] , ISSP DATA, I2C SDA, SPI CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
43
44
42
40
41
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25
[33, 34]
[33]
Notes
32. 34 GPIOs = 31 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
33. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
34. Alternate SPI clock.
35. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 17 of 53
48-pin QFN (33 Sensing Inputs) [36]
Table 8. Pin Definitions – CY8C20636A[37, 38]
Pin
No. Digital Analog Name Description Figure 10. CY8C20636A
1NC No connection
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O IP4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] ISSP CLK[37], I2C SCL, SPI
MOSI
18 Power VSS Ground connection[40]
19 DNU
20 DNU
21 Power VDD Supply voltage
22 IOHR IP1[0] ISSP DATA[37], I2C SDA, SPI
CLK[39]
23 IOHR IP1[2]
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
25 IOHR IP1[6]
26 Input XRES Active high external reset with
internal pull-down
27 I/O IP3[0]
28 I/O IP3[2]
29 I/O IP3[4] Pin
No. Digital Analog Name Description
30 I/O IP3[6] 40 IOH IP0[6]
31 I/O IP4[0] 41 Power VDD Supply voltage
32 I/O IP4[2] 42 NC No connection
33 I/O IP2[0] 43 NC No connection
34 I/O IP2[2] 44 IOH IP0[7]
35 I/O IP2[4] 45 IOH IP0[5]
36 I/O IP2[6] 46 IOH IP0[3] Integrating input
37 IOH IP0[0] 47 Power VSS Ground connection[40]
38 IOH IP0[2] 48 IOH IP0[1]
39 IOH IP0[4] CP Power VSS Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
10
11
12
AI , P2[7]
NC
AI , XOut, P2[5]
AI , XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI P3[1]
AI , I2 C SCL, SPI SS, P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0], AI
XRES
P1[6] , AI
P2[6] , AI
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, A I, P1[5]
NC
SPICLK,AI,P1[3]
AI,ISSP CLK, I2C SCL, SPI MOSI, P1[1]
Vss
DNU
DNU
Vdd
AI, ISSP DATA
1,I2CSDA,SPICL
K, P1[0]
AI, P 1[ 2 ]
AI, EXTCLK, P1[ 4]
NC
NC
NC
P0[4], AI
P0[1], AI
[37]
[37, 39]
Notes
36. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
37. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
38. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal
39. Alternate SPI clock.
40. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 18 of 53
48-pin QFN (33 Sensing Inputs (With USB)) [41]
Table 9. Pin Definitions – CY8C20646A, CY8C20646AS, CY8C20666A, CY8C20666AS [42, 43]
Pin
No. Digital Analog Name Description Figure 11. CY8C20646A, CY8C20646AS, CY8C20666A,
CY8C20666AS
1NC No connection
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O I P4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] ISSP CLK[42], I2C SCL, SPI MOSI
18 Power VSS Ground connection[45]
19 I/O D+ USB D+
20 I/O D- USB D-
21 Power VDD Supply voltage
22 IOHR IP1[0] ISSP DATA[42], I2C SDA, SPI
CLK[44]
23 IOHR IP1[2]
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
25 IOHR IP1[6]
26 Input XRES Active high external reset with
internal pull-down
27 I/O IP3[0]
28 I/O I P3[2]
29 I/O I P3[4] Pin
No. Digital Analog Name Description
30 I/O I P3[6] 40 IOH IP0[6]
31 I/O IP4[0] 41 Power VDD Supply voltage
32 I/O IP4[2] 42 NC No connection
33 I/O IP2[0] 43 NC No connection
34 I/O IP2[2] 44 IOH IP0[7]
35 I/O IP2[4] 45 IOH IP0[5]
36 I/O IP2[6] 46 IOH IP0[3] Integrating input
37 IOH IP0[0] 47 Power VSS Ground connection[45]
38 IOH IP0[2] 48 IOH IP0[1]
39 IOH IP0[4] CP Power VSS Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
AI , P2[7]
NC
AI, XOut, P2[5]
AI , XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
AI, I2 C SCL, SPI SS, P1[7]
35
34
33
32
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P2[6] , AI
1
2
3
4
5
NC
NC
P0[4], AI
P0[1], AI
(Top View)
10
11
12
31
30
29
28
27
26
25
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0], AI
XRES
P1[6] , AI
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, A I, P1[5]
NC
SPI CLK, AI, P1[3]
AI
,ISSP CLK,I2CSCL,SPIMOSI,P1[1]
Vss
D+
D-
Vdd
AI,ISSP DATA, I2C SDA, SPI CLK,P1[0]
AI, P 1 [ 2 ]
AI, EXTCLK, P1[4]
NC
[42, 44]
[42]
Notes
41. 38 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.
42. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
43. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
44. Alternate SPI clock.
45. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 19 of 53
48-pin QFN (OCD) (33 Sensing Inputs) [46]
The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD). Note that this part is only used for in-circuit debugging.
Table 10. Pin Definitions – CY8C20066A [47, 48]
Pin
No. Digital Analog Name Description Figure 12. CY8C20066A
1[49] OCDOE OCD mode direction pin
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O I P4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14[49] CCLK OCD CPU clock output
15[49] HCLK OCD high speed clock output
16 IOHR IP1[3] SPI CLK.
17 IOHR IP1[1] ISSP CLK[50], I2C SCL, SPI
MOSI
18 Power VSS Ground connection[52]
19 I/O D+ USB D+
20 I/O D- USB D-
21 Power VDD Supply voltage
22 IOHR IP1[0] ISSP DATA[50], I2C SDA, SPI
CLK[51]
23 IOHR IP1[2] Pin
No. Digital Analog Name Description
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
37 IOH IP0[0]
25 IOHR IP1[6] 38 IOH IP0[2]
26 Input XRES Active high external reset with
internal pull-down
39 IOH IP0[4]
27 I/O IP3[0] 40 IOH IP0[6]
28 I/O I P3[2] 41 Power VDD Supply voltage
29 I/O I P3[4] 42[49] OCDO OCD even data I/O
30 I/O I P3[6] 43[49] OCDE OCD odd data output
31 I/O IP4[0] 44 IOH IP0[7]
32 I/O IP4[2] 45 IOH IP0[5]
33 I/O IP2[0] 46 IOH IP0[3] Integrating input
34 I/O IP2[2] 47 Power VSS Ground connection[52]
35 I/O IP2[4] 48 IOH IP0[1]
36 I/O IP2[6] CP Power VSS Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
10
11
12
A
I, P2[7]
AI , XOut , P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0] , AI
XRES
P1[6] , AI
P2[6] , AI
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, AI, P1[5]
SPI CLK, AI, P1[3]
AI,ISSP CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
D-
Vdd
AI,ISSP DATA1, I2C SDA, SPI CLK, P1[0]
AI, P 1 [ 2]
AI, EXTCLK, P1[4]
P0[4], AI
P0[1], AI
OCDO
E
CCLK
HCLK
OCDE
OCDO
[50, 51]
[50]
Notes
46. 38 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.
47. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
48. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
49. This pin (associated with OCD part only) is required for connecting the device to ICE-Cube In-Circuit Emulator for firmware debugging purpose. To know more about
the usage of ICE-Cube, refer to CY3215-DK PSoC® IN-CIRCUIT EMULATOR KIT GUIDE.
50. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
51. Alternate SPI clock.
52. All VSS pins should be brought out to one common GND plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 20 of 53
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20XX6A/S PSoC devices. For the latest electrical specifi-
cations, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 13. Voltage versus CPU Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Operating Temperature
5.5V
750 kHz 24 MHz
CPU Frequency
Vdd Voltage
1.71V
3 MHz
Valid
Operating
Region
Table 11. Absolute Maximum Ratings
Symbol Description Conditions Min Typ Max Units
TSTG Storage temperature
Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55 +25 +125 °C
VDD Supply voltage relative to VSS ––0.5 –+6.0 V
VIO DC input voltage – VSS – 0.5 – VDD + 0.5 V
VIOZ[53] DC voltage applied to tristate – VSS – 0.5 – VDD + 0.5 V
IMIO Maximum current into any port pin – –25 –+50 mA
ESD Electrostatic discharge voltage Human body model ESD 2000 – – V
LU Latch-up current In accordance with JESD78 standard – – 200 mA
Note
53. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VDD.
Table 12. Operating Temperature
Symbol Description Conditions Min Typ Max Units
TAAmbient temperature – –40 –+85 °C
TCCommercial temperature range – 0–70 °C
TJOperational die temperature
The temperature rise from ambient to junction is package
specific. Refer the Thermal Impedances on page 38. The
user must limit the power consumption to comply with this
requirement.
–40 –+100 °C
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 21 of 53
DC Chip-Level Specifications
Table 1 3 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
VDD[54, 55, 56, 57] Supply voltage
No USB activity. Refer the table “DC
POR and LVD Specifications” on
page 26
1.71 –5.50 V
VDDUSB[54, 55, 56, 57] Operating voltage USB activity, USB regulator enabled 4.35 –5.25 V
USB activity, USB regulator bypassed 3.15 3.3 3.60 V
IDD24 Supply current, IMO = 24 MHz
Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 24 MHz. CapSense running at
12 MHz, no I/O sourcing current
–2.88 4.00 mA
IDD12 Supply current, IMO = 12 MHz
Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 12 MHz. CapSense running at
12 MHz, no I/O sourcing current
–1.71 2.60 mA
IDD6 Supply current, IMO = 6 MHz
Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 6 MHz. CapSense running at
6 MHz, no I/O sourcing current
–1.16 1.80 mA
IDDAVG10
Average supply current per
sensor One sensor scanned at 10 mS rate –250 –A
IDDAVG100
Average supply current per
sensor One sensor scanned at 100 mS rate –25 –A
IDDAVG500
Average supply current per
sensor One sensor scanned at 500 mS rate –7–A
ISB0[58, 59, 60, 61, 62, 63] Deep sleep current VDD 3.0 V, TA = 25 °C, I/O regulator
turned off –0.10 1.05 A
ISB1[58, 59, 60, 61, 62, 63] Standby current with POR,
LVD and sleep timer
VDD 3.0 V, TA = 25 °C, I/O regulator
turned off –1.07 1.50 A
ISBI2C[58, 59, 60, 61, 62, 63] Standby current with I2C
enabled
Conditions are VDD = 3.3 V, TA = 25 °C
and CPU = 24 MHz –1.64 –A
Notes
54. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
55. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a.Bring the device out of sleep before powering down.
b.Assure that VDD falls below 100 mV before powering back up.
c.Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d.Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
For the referenced registers, refer to the CY8C20X36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows
VDD brown out conditions to be detected for edge rates slower than 1V/ms.
56. For USB mode, the VDD supply for bus-powered application should be limited to 4.35 V–5.35 V. For self-powered application, VDD should be 3.15 V–3.45 V.
57. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can
be between 1.8 V and 5.5 V.
58. Errata: When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms (default), the device may
not come out of sleep when a sleep-ending input is received. For more information, see the “Errata” on page 46.
59. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is in or out of transition of sleep
mode. For more information, see the “Errata” on page 46.
60. Errata: When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is used to wake the device from
sleep, the interrupt service routine (ISR) may be executed twice. For more information, see the “Errata” on page 47.
61. Errata: When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may be missed, and the
corresponding GPIO ISR not run. For more information, see the “Errata” on page 47.
62. Errata: If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be missed. For more information,
see the “Errata” on page 48.
63. Errata: Device wakes up from sleep when an analog interrupt is trigger. For more information, see the “Errata” on page 48.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 22 of 53
DC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T
A 85 °C, 2.4 V to 3.0 V and –40 °C T
A 85 °C, or 1.71 V to 2.4 V and –40 °C T
A 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only.
Table 14. 3.0 V to 5.5 V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1 High output voltage
Port 2 or 3 or 4 pins
IOH < 10 A, maximum of 10 mA source
current in all I/Os VDD – 0.20 – – V
VOH2 High output voltage
Port 2 or 3 or 4 pins
IOH = 1 mA, maximum of 20 mA source
current in all I/Os VDD – 0.90 – – V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os VDD – 0.20 – – V
VOH4
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH = 5 mA, maximum of 20 mA source
current in all I/Os VDD – 0.90 – – V
VOH5
High output voltage
Port 1 Pins with LDO Regulator Enabled
for 3 V out
IOH < 10 A, VDD > 3.1 V, maximum of 4 I/Os
all sourcing 5 mA 2.85 3.00 3.30 V
VOH6
High output voltage
Port 1 pins with LDO regulator enabled for
3 V out
IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA
source current in all I/Os 2.20 – – V
VOH7 High output voltage
Port 1 pins with LDO enabled for 2.5 V out
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os 2.35 2.50 2.75 V
VOH8 High output voltage
Port 1 pins with LDO enabled for 2.5 V out
IOH = 2 mA, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os 1.90 – – V
VOH9 High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os 1.60 1.80 2.10 V
VOH10 High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH = 1 mA, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os 1.20 – – V
VOL Low output voltage
IOL = 25 mA, VDD > 3.3 V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
––0.75V
VIL Input low voltage – – – 0.80 V
VIH Input high voltage – 2.00 – – V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (Absolute Value) – –0.001 1A
CPIN Pin capacitance Package and pin dependent
Tem p = 25 ° C 0.50 1.70 7pF
VILLVT3.3 Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input 0.8 V – –
VIHLVT3.3 Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input 1.4 – – V
VILLVT5.5 Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input 0.8 V – –
VIHLVT5.5 Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input 1.7 – – V
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 23 of 53
Table 15. 2.4 V to 3.0 V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1
High output voltage
Port 2 or 3 or 4 pins
IOH < 10 A, maximum of 10 mA source
current in all I/Os VDD – 0.20 – – V
VOH2
High output voltage
Port 2 or 3 or 4 pins
IOH = 0.2 mA, maximum of 10 mA source
current in all I/Os VDD – 0.40 – – V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os VDD – 0.20 – – V
VOH4
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os VDD – 0.50 – – V
VOH5A
High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH < 10 A, VDD > 2.4 V, maximum of
20 mA source current in all I/Os 1.50 1.80 2.10 V
VOH6A
High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH = 1 mA, VDD > 2.4 V, maximum of 20 mA
source current in all I/Os 1.20 – – V
VOL Low output voltage
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink current on
odd port pins (for example, P0[3] and P1[5])
– – 0.75 V
VIL Input low voltage – – – 0.72 V
VIH Input high voltage – 1.40 – V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (absolute value) – – 1 1000 nA
CPIN Capacitive load on pins Package and pin dependent
Temp = 25 C0.50 1.70 7pF
VILLVT2.5
Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input 0.7 V –
VIHLVT2.5
Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input 1.2 – V
Table 16. 1.71 V to 2.4 V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1
High output voltage
Port 2 or 3 or 4 pins
IOH = 10 A, maximum of 10 mA
source current in all I/Os VDD – 0.20 – – V
VOH2
High output voltage
Port 2 or 3 or 4 pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os VDD – 0.50 – – V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 100 A, maximum of 10 mA
source current in all I/Os VDD – 0.20 – – V
VOH4
High output voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os VDD – 0.50 – – V
VOL Low output voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
– – 0.40 V
VIL Input low voltage – – – 0.30 × VDD V
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 24 of 53
DC Analog Mux Bus Specifications
Table 1 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Low Power Comparator Specifications
Table 1 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
VIH Input high voltage – 0.65 × VDD ––V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (absolute value) – – 1 1000 nA
CPIN Capacitive load on pins Package and pin dependent
temp = 25 °C 0.50 1.70 7pF
Table 16. 1.71 V to 2.4 V DC GPIO Specifications (continued)
Symbol Description Conditions Min Typ Max Units
Table 17. DC Characteristics – USB Interface
Symbol Description Conditions Min Typ Max Units
RUSBI USB D+ pull-up resistance With idle bus 900 – 1575
RUSBA USB D+ pull-up resistance While receiving traffic 1425 – 3090
VOHUSB Static output high – 2.8 –3.6V
VOLUSB Static output low – – –0.3V
VDI Differential input sensitivity – 0.2 –V
VCM Differential input common mode range – 0.8 –2.5V
VSE Single ended receiver threshold – 0.8 –2.0V
CIN Transceiver capacitance – – –50pF
IIO High Z state data line leakage On D+ or D- line –10 –+10A
RPS2 PS/2 pull-up resistance – 3000 5000 7000
REXT External USB series resistor In series with each USB pin 21.78 22.0 22.22
Table 18. DC Analog Mux Bus Specifications
Symbol Description Conditions Min Typ Max Units
RSW Switch resistance to common analog bus – – – 800
RGND Resistance of initialization switch to VSS – – – 800
The maximum pin voltage for measuring RSW and RGND is 1.8 V
Table 19. DC Comparator Specifications
Symbol Description Conditions Min Typ Max Units
VLPC
Low power comparator (LPC) common
mode Maximum voltage limited to VDD 0.0 – 1.8 V
ILPC LPC supply current – – 10 40 A
VOSLPC LPC voltage offset – – 3 30 mV
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 25 of 53
Comparator User Module Electrical Specifications
Table 2 0 lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire
device voltage and temperature operating range: –40 °C TA 85 °C, 1.71 V VDD 5.5 V.
ADC Electrical Specifications
Table 20. Comparator User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
tCOMP Comparator response time 50 mV overdrive –70 100 ns
Offset Valid from 0.2 V to VDD – 0.2 V –2.5 30 mV
Current Average DC current, 50 mV
overdrive –20 80 µA
PSRR Supply voltage > 2 V Power supply rejection ratio –80 –dB
Supply voltage < 2 V Power supply rejection ratio –40 –dB
Input range – 0 1.5 V
Table 21. ADC User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
Input
VIN Input voltage range – 0 – VREFADC V
CIIN Input capacitance –––5pF
RIN Input resistance
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution
1/(500fF ×
data clock)
1/(400fF ×
data clock)
1/(300fF ×
data clock)
Reference
VREFADC ADC reference voltage – 1.14–1.26V
Conversion Rate
FCLK Data clock
Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications for accuracy
2.25 – 6 MHz
S8 8-bit sample rate Data clock set to 6 MHz. sample rate
= 0.001/ (2^Resolution/Data Clock) – 23.43 – ksps
S10 10-bit sample rate Data clock set to 6 MHz. sample rate
= 0.001/ (2^resolution/data clock) – 5.85 – ksps
DC Accuracy
RES Resolution Can be set to 8-, 9-, or 10-bit 8 – 10 bits
DNL Differential nonlinearity – –1 – +2 LSB
INL Integral nonlinearity – –2 – +2 LSB
EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB
10-bit resolution 0 12.80 76.80 LSB
EGAIN Gain error For any resolution –5 – +5 %FSR
Power
IADC Operating current – – 2.10 2.60 mA
PSRR Power supply rejection ratio PSRR (VDD > 3.0 V) – 24 – dB
PSRR (VDD < 3.0 V) – 30 – dB
CY8C20XX6A/S
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DC POR and LVD Specifications
Table 2 2 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Programming Specifications
Table 2 3 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. DC POR and LVD Specifications
Symbol Description Conditions Min Typ Max Units
VPOR0 1.66 V selected in PSoC Designer VDD must be greater than or equal
to 1.71 V during startup, reset
from the XRES pin, or reset from
watchdog.
1.61 1.66 1.71 V
VPOR1 2.36 V selected in PSoC Designer – 2.36 2.41 V
VPOR2 2.60 V selected in PSoC Designer – 2.60 2.66 V
VPOR3 2.82 V selected in PSoC Designer – 2.82 2.95 V
VLVD0 2.45 V selected in PSoC Designer
–
2.40 2.45 2.51 V
VLVD1 2.71 V selected in PSoC Designer 2.64[64] 2.71 2.78 V
VLVD2 2.92 V selected in PSoC Designer 2.85[65] 2.92 2.99 V
VLVD3 3.02 V selected in PSoC Designer 2.95[66] 3.02 3.09 V
VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 V
VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 V
VLVD6 1.80 V selected in PSoC Designer 1.75[67] 1.80 1.84 V
VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83 V
Table 23. DC Programming Specifications
Symbol Description Conditions Min Typ Max Units
VDDIWRITE
Supply voltage for flash write
operations –1.71 –5.25 V
IDDP
Supply current during
programming or verify –– 5 25 mA
VILP
Input low voltage during
programming or verify
See the appropriate DC GPIO
Specifications on page 22 – – VIL V
VIHP
Input high voltage during
programming or verify
See the appropriate “DC GPIO
Specifications” on page 22 VIH – – V
IILP
Input current when Applying VILP
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor – – 0.2 mA
IIHP
Input current when applying VIHP
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor – – 1.5 mA
VOLP
Output low voltage during
programming or verify –– – VSS + 0.75 V
VOHP
Output high voltage during
programming or verify
See appropriate DC GPIO
Specifications on page 22. For
VDD > 3 V use VOH4 in Table 12 on
page 20.
VOH – VDD V
FlashENPB Flash write endurance Erase/write cycles per block 50,000 – – –
FlashDR Flash data retention Following maximum Flash write
cycles; ambient temperature of 55 °C 20 – – Years
Notes
64. Always greater than 50 mV above VPPOR1 voltage for falling supply.
65. Always greater than 50 mV above VPPOR2 voltage for falling supply.
66. Always greater than 50 mV above VPPOR3 voltage for falling supply.
67. Always greater than 50 mV above VPPOR0 voltage for falling supply.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 27 of 53
DC I2C Specifications
Table 2 4 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C
TA 85 °C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical parameters apply
to 5 V and 3.3 V at 25 °C and are for design guidance only.
DC Reference Buffer Specifications
Table 2 5 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C
TA 85 °C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical parameters apply
to 5 V and 3.3 V at 25 °C and are for design guidance only.
DC IDAC Specifications
Table 2 6 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 24. DC I2C Specifications
Symbol Description Conditions Min Typ Max Units
VILI2C Input low level
3.1 V ≤ VDD ≤ 5.5 V – – 0.25 × VDD V
2.5 V ≤ VDD ≤ 3.0 V – – 0.3 × VDD V
1.71 V ≤ VDD ≤ 2.4 V – – 0.3 × VDD V
VIHI2C Input high level 1.71 V ≤ VDD ≤ 5.5 V 0.65 × VDD ––V
Table 25. DC Reference Buffer Specifications
Symbol Description Conditions Min Typ Max Units
VRef Reference buffer output 1.7 V ≤ VDD ≤ 5.5 V 1 – 1.05 V
VRefHi Reference buffer output 1.7 V ≤ VDD ≤ 5.5 V 1.2 – 1.25 V
Table 26. DC IDAC Specifications
Symbol Description Min Typ Max Units Notes
IDAC_DNL Differential nonlinearity –4.5 – +4.5 LSB –
IDAC_INL Integral nonlinearity –5 – +5 LSB –
IDAC_Gain
(Source)
Range = 0.5x 6.64 – 22.46 µA DAC setting = 128 dec.
Not recommended for CapSense
applications.
Range = 1x 14.5 – 47.8 µA
Range = 2x 42.7 – 92.3 µA
Range = 4x 91.1 – 170 µA DAC setting = 128 dec
Range = 8x 184.5 – 426.9 µA DAC setting = 128 dec
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 28 of 53
AC Chip-Level Specifications
Table 2 7 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
FIMO24 IMO frequency at 24 MHz Setting –22.8 24 25.2 MHz
FIMO12 IMO frequency at 12 MHz setting –11.4 12 12.6 MHz
FIMO6 IMO frequency at 6 MHz setting –5.7 6.0 6.3 MHz
FCPU CPU frequency –0.75 –25.20 MHz
F32K1 ILO frequency –15 32 50 kHz
F32K_U ILO untrimmed frequency –13 32 82 kHz
DCIMO Duty cycle of IMO –40 50 60 %
DCILO ILO duty cycle –40 50 60 %
SRPOWER_UP Power supply slew rate VDD slew rate during power-up – – 250 V/ms
tXRST External reset pulse width at power-up After supply voltage is valid 1 – – ms
tXRST2
External reset pulse width after
power-up[68] Applies after part has booted 10 – – s
tOS Startup time of ECO ––1–s
tJIT_IMO[69] N=32
6 MHz IMO cycle-to-cycle jitter (RMS) – 0.7 6.7 ns
6 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS) – 4.3 29.3 ns
6 MHz IMO period jitter (RMS) – 0.7 3.3 ns
12 MHz IMO cycle-to-cycle jitter (RMS) – 0.5 5.2 ns
12 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS) –2.35.6ns
12 MHz IMO period jitter (RMS) – 0.4 2.6 ns
24 MHz IMO cycle-to-cycle jitter (RMS) – 1.0 8.7 ns
24 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS) –1.46.0ns
24 MHz IMO period jitter (RMS) – 0.6 4.0 ns
Notes
68. The minimum required XRES pulse length is longer when programming the device (see Table 33 on page 31).
69. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 29 of 53
AC GPIO Specifications
Table 2 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 14. GPIO Timing Diagram
Table 28. AC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
FGPIO GPIO operating frequency Normal strong mode Port 0, 1
0
0
–
–
6 MHz for
1.71 V <VDD < 2.40 V
12 MHz for
2.40 V < VDD< 5.50 V
MHz
MHz
tRISE23
Rise time, strong mode, Cload = 50 pF
Port 2 or 3 or 4 pins VDD = 3.0 to 3.6 V, 10% to 90% 15 – 80 ns
tRISE23L
Rise time, strong mode low supply,
Cload = 50 pF, Port 2 or 3 or 4 pins VDD = 1.71 to 3.0 V, 10% to 90% 15 – 80 ns
tRISE01
Rise time, strong mode, Cload = 50 pF
Ports 0 or 1
VDD = 3.0 to 3.6 V, 10% to 90%
LDO enabled or disabled 10 – 50 ns
tRISE01L
Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
VDD = 1.71 to 3.0 V, 10% to 90%
LDO enabled or disabled 10 – 80 ns
tFALL
Fall time, strong mode, Cload = 50 pF
all ports VDD = 3.0 to 3.6 V, 10% to 90% 10 – 50 ns
tFALLL
Fall time, strong mode low supply,
Cload = 50 pF, all ports VDD = 1.71 to 3.0 V, 10% to 90% 10 – 70 ns
tFALL
tRISE23
tRISE01
90%
10%
GPIO Pin
Output
Voltage
tRISE23L
tRISE01L
tFALLL
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 30 of 53
AC Comparator Specifications
Table 3 1 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
AC External Clock Specifications
Table 3 2 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC Characteristics – USB Data Timings
Symbol Description Conditions Min Typ Max Units
tDRATE Full speed data rate Average bit rate 12 – 0.25% 12 12 + 0.25% MHz
tJR1 Receiver jitter tolerance To next transition –18.5 – 18.5 ns
tJR2 Receiver jitter tolerance To pair transition –9.0 – 9 ns
tDJ1 FS Driver jitter To next transition –3.5 – 3.5 ns
tDJ2 FS Driver jitter To pair transition –4.0 – 4.0 ns
tFDEOP
Source jitter for differential
transition To SE0 transition –2.0 – 5 ns
tFEOPT Source SE0 interval of EOP – 160.0 – 175 ns
tFEOPR Receiver SE0 interval of EOP – 82.0 – – ns
tFST
Width of SE0 interval during
differential transition –––14ns
Table 30. AC Characteristics – USB Driver
Symbol Description Conditions Min Typ Max Units
tFR Transition rise time 50 pF 4 – 20 ns
tFF Transition fall time 50 pF 4 – 20 ns
tFRFM[70] Rise/fall time matching – 90 – 111 %
VCRS Output signal crossover voltage – 1.30 – 2.00 V
Table 31. AC Low Power Comparator Specifications
Symbol Description Conditions Min Typ Max Units
tLPC
Comparator response time,
50 mV overdrive
50 mV overdrive does not include
offset voltage ––100ns
Table 32. AC External Clock Specifications
Symbol Description Conditions Min Typ Max Units
FOSCEXT
Frequency (external oscillator
frequency) –0.75
– 25.20 MHz
High period – 20.60 –5300 ns
Low period – 20.60 ––ns
Power-up IMO to switch – 150 – – s
Note
70. TFRFM is not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3 V. This condition does not affect USB communications.
Signal integrity tests show an excellent eye diagram at 3.15 V.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 31 of 53
AC Programming Specifications
Figure 15. AC Waveform
Table 3 3 lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 33. AC Programming Specifications
Symbol Description Conditions Min Typ Max Units
tRSCLK Rise time of SCLK – 1 – 20 ns
tFSCLK Fall time of SCLK – 1 – 20 ns
tSSCLK Data setup time to falling edge of SCLK – 40 – – ns
tHSCLK Data hold time from falling edge of SCLK – 40 – – ns
FSCLK Frequency of SCLK – 0 – 8 MHz
tERASEB Flash erase time (block) – – – 18 ms
tWRITE Flash block write time – – – 25 ms
tDSCLK Data out delay from falling edge of SCLK 3.6 VDD – – 60 ns
tDSCLK3 Data out delay from falling edge of SCLK 3.0 VDD 3.6 – – 85 ns
tDSCLK2 Data out delay from falling edge of SCLK 1.71 VDD 3.0 – – 130 ns
tXRST3 External reset pulse width after power-up Required to enter programming
mode when coming out of sleep 300 – – s
tXRES XRES pulse length – 300 – – s
tVDDWAIT[71] VDD stable to wait-and-poll hold off – 0.1 – 1 ms
tVDDXRES[71] VDD stable to XRES assertion delay – 14.27 – – ms
tPOLL SDATA high pulse time – 0.01 –200 ms
tACQ[71] “Key window” time after a VDD ramp
acquire event, based on 256 ILO clocks. –3.20 –19.60 ms
tXRESINI[71] “Key window” time after an XRES event,
based on 8 ILO clocks –98 –615 s
SCLK (P1[1])
TRSCLK TFSCLK
SDATA (P1[0])
TSSCLK THSCLK TDSCLK
Note
71. Valid from 5 to 50 °C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67, CY8C20X47,
CY8C20X37, Programming Spec for more details.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 32 of 53
AC I2C Specifications
Table 3 4 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 34. AC Characteristics of the I2C SDA and SCL Pins
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tHD;STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated 4.0 –0.6–µs
tLOW LOW period of the SCL clock 4.7 –1.3–µs
tHIGH HIGH Period of the SCL clock 4.0 –0.6–µs
tSU;STA Setup time for a repeated START condition 4.7 –0.6–µs
tHD;DAT Data hold time 0 3.45 0 0.90 µs
tSU;DAT Data setup time 250 – 100[72] –ns
tSU;STO Setup time for STOP condition 4.0 –0.6–µs
tBUF Bus free time between a STOP and START condition 4.7 –1.3–µs
tSP Pulse width of spikes are suppressed by the input filter ––050ns
Note
72. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 33 of 53
Figure 17. SPI Master Mode 0 and 2
Figure 18. SPI Master Mode 1 and 3
Table 35. SPI Master AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency VDD 2.4 V
VDD < 2.4 V
–
–
–
–
6
3
MHz
MHz
DC SCLK duty cycle – – 50 – %
tSETUP MISO to SCLK setup time VDD 2.4 V
VDD < 2.4 V
60
100
–
–
–
–
ns
ns
tHOLD SCLK to MISO hold time – 40 – – ns
tOUT_VAL SCLK to MOSI valid time – – – 40 ns
tOUT_H MOSI high time – 40 – – ns
1/FSCLK
TLOW THIGH
TOUT_H
THOLD
TSETUP
TOUT_SU
MSB LSB
SPI Master, modes 0 and 2
SCLK
(mode 0)
SCLK
(mode 2)
MISO
(input)
MOSI
(output)
1/FSCLK
THIGH TLOW
TOUT_H
THOLD
TSETUP
SCLK
(mode 1)
SCLK
(mode 3)
MISO
(input)
MOSI
(output)
SPI Master, modes 1 and 3
TOUT_SU
MSB
MSB LSB
LSB
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 34 of 53
Figure 19. SPI Slave Mode 0 and 2
Figure 20. SPI Slave Mode 1 and 3
Table 36. SPI Slave AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency – – – 4 MHz
tLOW SCLK low time – 42 – – ns
tHIGH SCLK high time – 42 – – ns
tSETUP MOSI to SCLK setup time – 30 – – ns
tHOLD SCLK to MOSI hold time – 50 – – ns
tSS_MISO SS high to MISO valid – – – 153 ns
tSCLK_MISO SCLK to MISO valid – – – 125 ns
tSS_HIGH SS high time – 50 – – ns
tSS_CLK Time from SS low to first SCLK – 2/SCLK – – ns
tCLK_SS Time from last SCLK to SS high – 2/SCLK – – ns
TCLK_SS TSS_HIGH
1/FSCLK
TLOW THIGH
TOUT_H
THOLD
TSETUP
TSS_MISO
TSS_CLK
MSB LSB
SPI Slave, modes 0 and 2
/SS
SCLK
(mode 0)
SCLK
(mode 2)
MISO
(output)
MOSI
(input)
TCLK_SS
1/FSCLK
THIGH TLOW
TSCLK_MISO
TOUT_H
THOLD
TSETUP
TSS_CLK
/SS
SCLK
(mode 1)
SCLK
(mode 3)
MISO
(output)
MOSI
(input)
SPI Slave, modes 1 and 3
TSS_MISO
MSB
MSB LSB
LSB
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 35 of 53
Packaging Information
This section illustrates the packaging specifications for the CY8C20XX6A/S PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 21. 16-pin QFN (No E-Pad) (3 × 3 × 0.6 mm) LG16A (Sawn) Package Outline, 001-09116
Figure 22. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
001-09116 *J
001-13937 *F
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 36 of 53
Figure 23. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168
Figure 24. 48-pin SSOP (300 Mils) O483 Package Outline, 51-85061
001-42168 *E
51-85061 *F
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 37 of 53
Figure 25. 48-pin QFN (7 × 7 × 1.0 mm) LT48A 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191
Figure 26. 48-pin QFN (6 × 6 × 0.6 mm) LQ48A 4.6 × 4.6 E-Pad (Sawn) Package Outline, 001-57280
Important Notes
■For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■Pinned vias for thermal conduction are not required for the low power PSoC device.
001-13191 *H
001-57280 *E
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 38 of 53
Thermal Impedances
Capacitance on Crystal Pins
Solder Reflow Specifications
Table 3 9 shows the solder reflow temperature limits that must not be exceeded.
Table 37. Thermal Impedances per Package
Package Typical JA [73] Typical JC
16-pin QFN (No Center Pad) 33 C/W –
24-pin QFN [74] 21 C/W –
32-pin QFN [74] 20 C/W –
48-pin SSOP 69 C/W –
48-pin QFN (6 × 6 × 0.6 mm) [74] 25.20 C/W 3.04 C/W
48-pin QFN (7 × 7 × 1.0 mm) [74] 18 C/W –
30-ball WLCSP 54 C/W –
Table 38. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
32-pin QFN 3.2 pF
48-pin QFN 3.3 pF
Table 39. Solder Reflow Specifications
Package Maximum Peak Temperature (TC)Maximum Time above TC – 5 °C
16-pin QFN 260 C30 seconds
24-pin QFN 260 C30 seconds
32-pin QFN 260 C30 seconds
48-pin SSOP 260 C30 seconds
48-pin QFN (6 × 6 × 0.6 mm) 260 C30 seconds
48-pin QFN (7 × 7 × 1.0 mm) 260 C30 seconds
30-ball WLCSP 260 C30 seconds
Notes
73. TJ = TA + Power × JA.
74. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 39 of 53
Development Tool Selection
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for over half a
decade. PSoC Designer is available free of charge at
http://www.cypress.com.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC Programmer is available free of charge
at http://www.cypress.com.
Development Kits
All development kits are sold at the Cypress Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■PSoC Designer Software CD
■ICE-Cube In-Circuit Emulator
■ICE Flex-Pod for CY8C29X66A Family
■Cat-5 Adapter
■Mini-Eval Programming Board
■110 ~ 240 V Power Supply, Euro-Plug Adapter
■iMAGEcraft C Compiler (Registration Required)
■ISSP Cable
■USB 2.0 Cable and Blue Cat-5 Cable
■2 CY8C29466A-24PXI 28-PDIP Chip Samples
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■MiniProg Programming Unit
■MiniEval Socket Programming and Evaluation Board
■28-pin CY8C29466A-24PXI PDIP PSoC Device Sample
■28-pin CY8C27443A-24PXI PDIP PSoC Device Sample
■PSoC Designer Software CD
■Getting Started Guide
■USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of
breadboarding space to meet all of your evaluation needs. The
kit includes:
■Evaluation Board with LCD Module
■MiniProg Programming Unit
■28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2)
■PSoC Designer Software CD
■Getting Started Guide
■USB 2.0 Cable
CY3280-20X66 Universal CapSense Controller
The CY3280-20X66 CapSense Controller Kit is designed for
easy prototyping and debug of CY8C20XX6A CapSense Family
designs with pre-defined control circuitry and plug-in hardware.
Programming hardware and an I2C-to-USB bridge are included
for tuning and data acquisition.
The kit includes:
■CY3280-20X66 CapSense Controller Board
■CY3240-I2USB Bridge
■CY3210 MiniProg1 Programmer
■USB 2.0 Retractable Cable
■CY3280-20X66 Kit CD
Device Programmers
All device programmers are purchased from the Cypress Online
Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■Modular Programmer Base
■Three Programming Module Cards
■MiniProg Programming Unit
■PSoC Designer Software CD
■Getting Started Guide
■USB 2.0 Cable
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 40 of 53
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■CY3207 Programmer Unit
■PSoC ISSP Software CD
■110 ~ 240 V Power Supply, Euro-Plug Adapter
■USB 2.0 Cable
Accessories (Emulation and Programming)
Third Party Tools
Several tools have been specially designed by third-party vendors to accompany PSoC devices during development and production.
Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, refer Application Note Debugging - Build a PSoC Emulator into Your Board – AN2323.
Table 40. Emulation and Programming Accessories
Part Number Pin Package Flex-Pod Kit[75] Foot Kit[76] Adapter[77]
CY8C20236A-24LKXI 16-pin QFN (No E-Pad) CY3250-20246QFN CY3250-20246QFN-POD See note 74
CY8C20246A-24LKXI 16-pin QFN (No E-Pad) CY3250-20246QFN CY3250-20246QFN-POD See note 77
CY8C20246AS-24LKXI 16-pin QFN (No E-Pad) Not Supported
CY8C20336A-24LQXI 24-pin QFN CY3250-20346QFN CY3250-20346QFN-POD See note 74
CY8C20346A-24LQXI 24-pin QFN CY3250-20346QFN CY3250-20346QFN-POD See note 77
CY8C20396A-24LQXI 24-pin QFN Not Supported
CY8C20436A-24LQXI 32-pin QFN CY3250-20466QFN CY3250-20466QFN-POD See note 74
CY8C20446A-24LQXI 32-pin QFN CY3250-20466QFN CY3250-20466QFN-POD See note 77
CY8C20446AS-24LQXI 32-pin QFN Not Supported
CY8C20466A-24LQXI 32-pin QFN CY3250-20466QFN CY3250-20466QFN-POD See note 77
CY8C20466AS-24LQXI 32-pin QFN Not Supported
CY8C20496A-24LQXI 32-pin QFN Not Supported
CY8C20536A-24PVXI 48-pin SSOP CY3250-20566 CY3250-20566-POD See note 77
CY8C20546A-24PVXI 48-pin SSOP CY3250-20566 CY3250-20566-POD See note 77
CY8C20566A-24PVXI 48-pin SSOP CY3250-20566 CY3250-20566-POD See note 77
Notes
75. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
76. Foot kit includes surface mount feet that can be soldered to the target PCB.
77. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 41 of 53
Ordering Information
Table 4 1 lists the CY8C20XX6A/S PSoC devices' key package features and ordering codes.
Table 41. PSoC Device Key Features and Ordering Information
Package Ordering Code Flash
(Bytes)
SRAM
(Bytes)
CapSense
Blocks
Digital
I/O Pins
Analog
Inputs [78] XRES
Pin USB ADC
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) CY8C20236A-24LKXI 8K 1K 113 13 Yes No Ye s
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) (Tape and Reel) CY8C20236A-24LKXIT 8K 1K 113 13 Yes No Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) CY8C20246A-24LKXI 16K 2K 113 13 Yes No Ye s
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) CY8C20246AS-24LKXI 16K 2K 113 13 Yes No Ye s
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) (Tape and Reel) CY8C20246A-24LKXIT 16K 2K 113 13 Yes No Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) (Tape and Reel) CY8C20246AS-24LKXIT 16K 2K 113 13 Yes No Yes
24-pin (4 × 4 × 0.6 mm) QFN CY8C20336A-24LQXI 8K 1K 120 20 Yes No Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel) CY8C20336A-24LQXIT 8K 1K 120 20 Yes No Yes
24-pin (4 × 4 × 0.6 mm) QFN CY8C20346A-24LQXI 16K 2K 120 20 Yes No Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel) CY8C20346A-24LQXIT 16K 2K 120 20 Yes No Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel) CY8C20346AS-24LQXIT 16K 2K 120 20 Yes No Yes
24-pin (4 × 4 × 0.6 mm) QFN CY8C20396A-24LQXI 16K 2K 119 19 Yes Yes Ye s
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel) CY8C20396A-24LQXIT 16K 2K 119 19 Yes Yes Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20436A-24LQXI 8K 1K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20436A-24LQXIT 8K 1K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20446A-24LQXI 16K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20446AS-24LQXI 16K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20446A-24LQXIT 16K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20446AS-24LQXIT 16K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20466A-24LQXI 32K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20466AS-24LQXI 32K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20466A-24LQXIT 32K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20466AS-24LQXIT 32K 2K 128 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20496A-24LQXI 16K 2K 125 25 Yes Yes Ye s
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20496A-24LQXIT 16K 2K 125 25 Yes Yes Yes
Note
78. Dual-function Digital I/O Pins also connect to the common analog mux.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 42 of 53
48-pin SSOP [79] CY8C20536A-24PVXI [79] 8K 1K 134 34 Yes No Yes
48-pin SSOP (Tape and Reel) [79] CY8C20536A-24PVXIT [79] 8K 1K 134 34 Yes No Ye s
48-pin SSOP [79] CY8C20546A-24PVXI [79] 16K 2K 134 34 Yes No Yes
48-pin SSOP (Tape and Reel) [79] CY8C20546A-24PVXIT [79] 16K 2K 134 34 Yes No Ye s
48-pin SSOP [79] CY8C20566A-24PVXI [79] 32K 2K 134 34 Yes No Yes
48-pin SSOP (Tape and Reel) [79] CY8C20566A-24PVXIT [79] 32K 2K 134 34 Yes No Ye s
48-pin (6 × 6 × 0.6 mm) QFN CY8C20636A-24LQXI 8K 1K 136 36 Yes No Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel) CY8C20636A-24LQXIT 8K 1K 136 36 Yes No Yes
48-pin (7 × 7 × 1.0 mm) QFN [79] CY8C20636A-24LTXI [79] 8K 1K 136 36 Yes No Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [79] CY8C20636A-24LTXIT [79] 8K 1K 136 36 Yes No Yes
48-pin (6 × 6 × 0.6 mm) QFN CY8C20646A-24LQXI 16K 2K 136 36 Yes Yes Ye s
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel) CY8C20646A-24LQXIT 16K 2K 136 36 Yes Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [79] CY8C20646A-24LTXI [79] 16K 2K 136 36 Yes Yes Ye s
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [79] CY8C20646A-24LTXIT [79] 16K 2K 136 36 Yes Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN CY8C20666A-24LQXI 32K 2K 136 36 Yes Yes Ye s
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel) CY8C20666A-24LQXIT 32K 2K 136 36 Yes Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [79] CY8C20666A-24LTXI [79] 32K 2 K 136 36 Yes Yes Ye s
48-pin (7 × 7 × 1.0 mm) QFN [79] CY8C20666AS-24LTXI [79] 32K 2K 136 36 Yes Ye s Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [79] CY8C20666A-24LTXIT [79] 32K 2K 136 36 Yes Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [79] CY8C20666AS-24LTXIT [79] 32K 2K 136 36 Yes Ye s Yes
48-pin (7 × 7 × 1.0 mm) QFN
(OCD) [80] CY8C20066A-24LTXI [80] 32K 2K 136 36 Yes Yes Ye s
30-ball WLCSP CY8C20746A-24FDXC 16K 1K 127 27 Yes No Ye s
30-ball WLCSP (Tape and Reel) CY8C20746A-24FDXCT 16K 1K 127 27 Yes No Yes
30-ball WLCSP CY8C20766A-24FDXC 32K 2K 127 27 Yes No Ye s
30-ball WLCSP (Tape and Reel) CY8C20766A-24FDXCT 32K 2K 127 27 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20436AN-24LQXI 8K 1K 128 28 Yes No No
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20436AN-24LQXIT 8K 1K 128 28 Yes No No
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) CY8C20246AS-24LKXI 16K 2K 1 13 13 Yes No Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad, Tape and Reel) CY8C20246AS-24LKXIT 16K 2K 1 13 13 Yes No Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel) CY8C20346AS-24LQXIT 16K 2K 1 20 20 Yes No Yes
Table 41. PSoC Device Key Features and Ordering Information (continued)
Package Ordering Code Flash
(Bytes)
SRAM
(Bytes)
CapSense
Blocks
Digital
I/O Pins
Analog
Inputs [78] XRES
Pin USB ADC
Notes
79. Not Recommended for New Designs.
80. Dual-function Digital I/O Pins also connect to the common analog mux.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 43 of 53
Ordering Code Definitions
32-pin (5 × 5 × 0.6 mm) QFN CY8C20446AS-24LQXI 16K 2K 1 28 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20446AS-24LQXIT 16K 2K 1 28 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN CY8C20466AS-24LQXI 32K 2K 1 28 28 Yes No Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel) CY8C20466AS-24LQXIT 32K 2K 1 28 28 Yes No Yes
48-pin (6 × 6 × 0.6 mm) QFN CY8C20666AS-24LQXI 32K 2K 1 36 36 Yes Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel) CY8C20666AS-24LQXIT 32K 2K 1 36 36 Yes Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [81] CY8C20666AS-24LTXI [81] 32K 2K 1 36 36 Yes Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [81] CY8C20666AS-24LTXIT [81] 32K 2K 1 36 36 Yes Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN CY8C20646AS-24LQXI 16K 2K 1 36 36 Yes Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel) CY8C20646AS-24LQXIT 16K 2K 1 36 36 Yes Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [81] CY8C20646AS-24LTXI [81] 16K 2K 1 36 36 Yes Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [81] CY8C20646AS-24LTXIT [81] 16K 2K 1 36 36 Yes Yes Yes
Table 41. PSoC Device Key Features and Ordering Information (continued)
Package Ordering Code Flash
(Bytes)
SRAM
(Bytes)
CapSense
Blocks
Digital
I/O Pins
Analog
Inputs [78] XRES
Pin USB ADC
Tape and Reel
Temperature range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = LK or LQ or PV or LT or FD
LK = 16-pin QFN (no E-Pad)
LQ = 24-pin QFN, 32-pin QFN, 48-pin (6 × 6 × 0.6 mm) QFN
PV = 48-pin SSOP
LT = 48-pin (7 × 7 × 1.0 mm) QFN
FD = 30-ball WLCSP
Speed Grade: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
C 20 XX6AX - 24 XXX TCY 8 X
Note
81. Not Recommended for New Designs.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 44 of 53
Acronyms Reference Documents
■Technical Reference Manual for CY8C20xx6 devices
■In-system Serial Programming (ISSP) protocol for 20xx6
(AN2026C)
■Host Sourced Serial Programming for 20xx6 devices
(AN59389)
Document Conventions
Units of Measure
Table 42. Acronyms Used in this Document
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CMOS complementary metal oxide semiconductor
CPU central processing unit
DAC digital-to-analog converter
DC direct current
EOP end of packet
FSR full scale range
GPIO general purpose input/output
GUI graphical user interface
I2Cinter-integrated circuit
ICE in-circuit emulator
IDAC digital analog converter current
ILO internal low speed oscillator
IMO internal main oscillator
I/O input/output
ISSP in-system serial programming
LCD liquid crystal display
LDO low dropout (regulator)
LSB least-significant bit
LVD low voltage detect
MCU micro-controller unit
MIPS mega instructions per second
MISO master in slave out
MOSI master out slave in
MSB most-significant bit
OCD on-chip debugger
POR power on reset
PPOR precision power on reset
PSRR power supply rejection ratio
PWRSYS power system
PSoC®Programmable System-on-Chip
SLIMO slow internal main oscillator
SRAM static random access memory
SNR signal to noise ratio
QFN quad flat no-lead
SCL serial I2C clock
SDA serial I2C data
SDATA serial ISSP data
SPI serial peripheral interface
SS slave select
SSOP shrink small outline package
TC test controller
USB universal serial bus
USB D+ USB Data+
USB D– USB Data–
WLCSP wafer level chip scale package
XTAL crystal
Table 43. Units of Measure
Symbol Unit of Measure
°C degree Celsius
dB decibels
fF femtofarad
ggram
Hz hertz
KB 1024 bytes
Kbit 1024 bits
KHz kilohertz
Ksps kilo samples per second
kkilohm
MHz megahertz
Mmegaohm
Amicroampere
Fmicrofarad
Hmicrohenry
smicrosecond
Wmicrowatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
nF nanofarad
ns nanosecond
nV nanovolt
Wohm
pA picoampere
pF picofarad
pp peak-to-peak
ppm parts per million
ps picosecond
sps samples per second
ssigma: one standard deviation
Vvolt
Wwatt
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 45 of 53
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Glossary
Crosspoint connection Connection between any GPIO combination via analog multiplexer bus.
Differential non-linearity Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the worst case deviation from the
ideal 1 LSB step.
Hold time Hold time is the time following a clock event during which the data input to a latch or flip-flop
must remain stable in order to guarantee that the latched data is correct.
I2C It is a serial multi-master bus used to connect low speed peripherals to MCU.
Integral nonlinearity It is a term describing the maximum deviation between the ideal output of a DAC/ADC and
the actual output level.
Latch-up current Current at which the latch-up test is conducted according to JESD78 standard (at 125
degree Celsius)
Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding
change in output voltage of the device.
Scan The conversion of all sensor capacitances to digital values.
Setup time Period required to prepare a device, machine, process, or system for it to be ready to
function.
Signal-to-noise ratio The ratio between a capacitive finger signal and system noise.
SPI Serial peripheral interface is a synchronous serial data link standard.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 46 of 53
Errata
This section describes the errata for the PSoC® CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families. Details include errata
trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Repre-
sentative if you have questions.
Qualification Status
Product Status: Production released.
Errata Summary
The following Errata items apply to CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families.
1. Wakeup from sleep may intermittently fail
■Problem Definition
When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms
(default), the device may not come out of sleep when a sleep-ending input is received.
■Parameters Affected
None
■Trigger Condition(S)
By default, when the device is in the Standby or I2C_USB sleep modes, the bandgap circuit is powered-up approximately every 8
ms to facilitate detection of POR or LVD events. This interval can be lengthened or the periodic power-up disabled to reduce sleep
current by setting the ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively. If
the bandgap circuit refresh interval is set longer than the default 8 ms, the device may fail to wakeup from sleep and enter a locked
up state that can only be recovered by Watchdog Reset, XRES, or POR.
■Scope of Impact
The trigger conditions outlined above may cause the device to never wakeup.
■Workaround
Prior to entering Standby or I2C_USB sleep modes, do not lengthen or disable the bandgap refresh interval by manipulating the
ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively.
■Fix Status
This issue will not be corrected in the next silicon revision.
2. I2C Errors
■Problem Definition
The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is
transitioning in to or out of sleep mode.
■Parameters Affected
Affects reliability of I2C communication to device, and between I2C master and third party I2C slaves.
■Trigger Condition(S)
Triggered by transitions into and out of the device’s sleep mode.
■Scope of Impact
Data errors result in incorrect data reported to the I2C master, or incorrect data received from the master by the device. Bus
corruption errors can corrupt data in transactions between the I2C master and third party I2C slaves.
■Workaround
Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I2C block from the bus
prior to going to sleep modes. I2C transactions during sleep are supported by a protocol in which the master wakes the device prior
to the I2C transaction.
■Fix Status
To be fixed in future silicon.
■Changes
None
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 47 of 53
3. DoubleTimer0 ISR
■Problem Definition
When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is
used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode.
■Scope of Impact
The ISR may be executed twice.
■Workaround
In the ISR, firmware should clear the one-shot bit with a statement such as “and reg[B0h], FDh”
■Fix Status
Will not be fixed
■Changes
None
4. Missed GPIO Interrupt
■Problem Definition
When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may
be missed, and the corresponding GPIO ISR not run.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt.
■Scope of Impact
The GPIO interrupt service routine will not be run.
■Workaround
The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake
the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt.
Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0.
Alternatively, the ISR’s for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system
has attempted to generate a GPIO interrupt.
■Fix Status
Will not be fixed
■Changes
None
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 48 of 53
5. Missed Interrupt During Transition to Sleep
■Problem Definition
If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be
missed.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling sleep mode just prior to an interrupt.
■Scope of Impact
The relevant interrupt service routine will not be run.
■Workaround
None.
■Fix Status
Will not be fixed
■Changes
None
6. Wakeup from sleep with analog interrupt
■Problem Definition
Device wakes up from sleep when an analog interrupt is trigger
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 °C or above
■Scope of Impact
Device unexpectedly wakes up from sleep
■Workaround
Disable the analog interrupt before entering sleep and turn it back on upon wakeup.
■Fix Status
Will not be fixed
■Changes
None
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 49 of 53
Document History Page
Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons,
0–6 Sliders
Document Number: 001-54459
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 2737924 SNV 07/14/2009 New silicon and document
*A 2764528 MATT 09/16/2009 Updated AC Chip Level Specifications
Updated ADC User Module Electrical Specifications table
Added Note 5.
Added SRPOWER_UP parameter.
Updated Ordering information.
Updated Capacitance on Crystal Pins
*B 2803229 VZD 11/10/2009 Added “Contents” on page 4. Added Note 6 on page 20. Edited Features section
to include reference to Incremental ADC.
*C 2846083 DST /
KEJO
01/12/2010 Updated “AC Programming Specifications” on page 31 per CDT 56531.
Updated Idd typical values in “DC Chip-Level Specifications” on page 21.
Added 30-pin WLCSP pin and package details.
Added Contents on page 2.
*D 2935141 KEJO / ISW
/ SSHH
03/05/2010 Updated “Features” on page 1. Added “SmartSense” on page 5.
Updated “PSoC® Functional Overview” on page 5.
Removed SNR statement regarding on page 4 (Analog Multiplexer section).
Updated Additional System Resources on page 6 with the I2C enhanced slave
interface point.
Removed references to “system level” in “Designing with PSoC Designer” on
page 9.
Changed TC CLK and TC DATA to ISSP CLK and ISSP DATA respectively in all
the pinouts.
Modified notes in Pinouts.
Updated 30-ball pin diagram.
Removed IMO frequency trim options diagram in “Electrical Specifications” on
page 20.
Updated and formatted values in DC and AC specifications.
Updated Ordering information table.
Updated 48-pin SSOP package diagram. Added 30-Ball WLCSP package spec
001-50669.
Removed AC Analog Mux Bus Specifications section.
Added SPI Master and Slave mode diagrams.
Modified Definition for Timing for Fast/Standard Mode on the I2C Bus on page 28.
Updated “Thermal Impedances” on page 38.
Combined Development Tools with “Development Tool Selection” on page 39.
Removed references to “system level”.
Updated “Evaluation Tools” on page 39.
Added “Ordering Code Definitions” on page 43.
Updated “Acronyms” on page 44.
Added Glossary and “Reference Documents” on page 44.
Changed datasheet status from Preliminary to Final
*E 3043291 SAAC 09/30/2010 Change: Added the line “Supports SmartSense” in the “Low power CapSense®
block” bullet in the Features section.
Impact: Helps to know that this part has the feature of Auto Tuning.
Change: Replaced pod MPNs.
Areas affected: Foot kit column of table 37.
Change: Template and Styles update.
Areas affected: Entire datasheet.
Impact: Datasheet adheres to Cypress standards.
*F 3071632 JPX 10/26/2010 In Table 36 on page 34, modified tLOW and tHIGH min values to 42. Updated
tSS_HIGH min value to 50; removed max value.
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 50 of 53
*G 3247491 TTO / JPM /
ARVM / BVI
06/16/2011 Add 4 new parameters to Table 14 on page 22, and 2 new parameters to Ta b l e
15 on page 23.
Changed Typ values for the following parameters: IDD24, IDD12, IDD6, VOSLPC.
Added footnote # 49 and referred it to pin numbers 1, 14, 15, 42, and 43 under
Table 10 on page 19.
Added footnote # 53 and referred it to parameter VIOZ under Table 11 on page 20.
Added “tJIT_IMO” parameter to Table 27 on page 28.
Included footnote # 69 and added reference to tJIT_IMO specification under Table
27 on page 28.
Updated Solder Reflow Specifications on page 38 as per specs 25-00090 and
25-00103.
ISB0 Max value changed from 0.5 µA to 1.1 µA in Table 13 on page 21.
Added Table 26 on page 27.
Updated part numbers for “SmartSense_EMC” enabled CapSense controller.
*H 3367332 BTK /
SSHH /
JPM / TTO /
VMAD
09/09/2011 Added parameter “tOS” to Table 27 on page 28.
Added parameter “ISBI2C” to Table 13 on page 21.
Added Table 24 on page 27.
Added Table 25 on page 27.
Replaced text “Port 2 or 3 pins” with “Port 2 or 3 or 4 pins” in Table 14, Tab l e 15 ,
Table 16, and Table 28.
*I 3371807 MATT 09/30/2011 Updated Packaging Information (Updated the next revision package outline for
Figure 21, Figure 24 and included a new package outline Figure 26).
Updated Ordering Information (Added new part numbers CY8C20636A-24LQXI,
CY8C20636A-24LQXIT, CY8C20646A-24LQXI, CY8C20646A-24LQXIT,
CY8C20666A-24LQXI, CY8C20666A-24LQXIT, CY8C20666AS-24LQXI,
CY8C20666AS-24LQXIT, CY8C20646AS-24LQXI and
CY8C20646AS-24LQXIT).
Updated to new template.
*J 3401666 MATT 10/11/2011 No technical updates.
*K 3414479 KPOL 10/19/2011 Removed clock stretching feature on page 1.
Removed I2C enhanced slave interface point from Additional System Resources.
*L 3452591 BVI / UDYG 12/01/2011 Changed document title.
Updated DC Chip-Level Specifications table.
Updated Solder Reflow Specifications section.
Updated Getting Started and Designing with PSoC Designer sections.
Included Development Tools section.
Updated Software under Development Tool Selection section.
*M 3473330 ANBA 12/22/2011 Updated DC Chip-Level Specifications under Electrical Specifications (updated
maximum value of ISB0 parameter from 1.1 µA to 1.05 µA).
*N 3587003 DST 04/16/2012 Added note for WLCSP package on page 1.
Added Sensing inputs to pin table captions.
Updated Conditions for DC Reference Buffer Specifications.
Updated tJIT_IMO description in AC Chip-Level Specifications.
Added note for tVDDWAIT
, tVDDXRES, tACQ, and tXRESINI specs.
Removed WLCSP package outline.
*O 3638569 BVI 06/06/2012 Updated FSCLK parameter in the Table 36, “SPI Slave AC Specifications,” on
page 34.
Changed tOUT_HIGH to tOUT_H in Table 35, “SPI Master AC Specifications,” on
page 33.
Updated package diagram 001-57280 to *C revision.
Document History Page (continued)
Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons,
0–6 Sliders
Document Number: 001-54459
Revision ECN Orig. of
Change
Submission
Date Description of Change
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 51 of 53
*P 3774062 UBU 10/11/2012 Updated Electrical Specifications:
Updated AC Chip-Level Specifications:
Updated Table 27:
Changed minimum value of F32K1 parameter from 19 kHz to 15 kHz.
Updated Packaging Information:
spec 001-09116 – Changed revision from *F to *G.
spec 001-13937 – Changed revision from *D to *E.
spec 51-85061 – Changed revision from *E to *F.
spec 001-13191 – Changed revision from *F to *G.
spec 001-57280 – Changed revision from *C to *D.
*Q 3807186 PKS 15/11/2012 No content update; appended to EROS document.
*R 3836626 SRLI 01/03/2013 Updated Document Title to read as “CY8C20XX6A/S, 1.8 V Programmable
CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6
Sliders”.
Updated Features.
Updated PSoC® Functional Overview:
Replaced “CY8C20X36A/46A/66A/96A/46AS/66AS” with “CY8C20XX6A/S”.
Updated Getting Started:
Replaced “CY8C20X36A/46A/66A/96A/46AS/66AS” with “CY8C20XX6A/S”.
Updated Pinouts:
Updated 16-pin QFN (10 Sensing Inputs)[3, 4]:
Replaced “12 Sensing Inputs” with “10 Sensing Inputs” in heading, added Note
3 only.
Updated 24-pin QFN (17 Sensing Inputs) [8]:
Replaced “12 Sensing Inputs” with “17 Sensing Inputs” in heading, added Note
8 only.
Updated 24-pin QFN (15 Sensing Inputs (With USB)) [13]:
Replaced “18 Sensing Inputs” with “15 Sensing Inputs” in heading, added Note
13 only.
Updated 30-ball WLCSP (24 Sensing Inputs) [18]:
Replaced “26 Sensing Inputs” with “24 Sensing Inputs” in heading, added Note
18 only.
Updated 32-pin QFN (25 Sensing Inputs) [22]:
Replaced “27 Sensing Inputs” with “25 Sensing Inputs” in heading, added Note
22 only.
updated 32-pin QFN (22 Sensing Inputs (With USB)) [27]:
Replaced “24 Sensing Inputs” with “22 Sensing Inputs” in heading, added Note
27 only.
Updated 48-pin SSOP (31 Sensing Inputs) [32]:
Replaced “33 Sensing Inputs” with “31 Sensing Inputs” in heading, added Note
32 only.
Updated 48-pin QFN (33 Sensing Inputs) [36]:
Replaced “35 Sensing Inputs” with “33 Sensing Inputs” in heading, added Note
36 only.
Updated 48-pin QFN (33 Sensing Inputs (With USB)) [41]:
Replaced “35 Sensing Inputs” with “33 Sensing Inputs” in heading, added Note
41 only.
Updated 48-pin QFN (OCD) (33 Sensing Inputs) [46]:
Added “33 Sensing Inputs” in heading, added Note 46 only.
Updated Packaging Information:
spec 001-42168 – Changed revision from *D to *E.
spec 001-57280 – Changed revision from *D to *E.
*S 3997568 BVI 05/11/2013 Added Errata.
*T 4044148 BVI 06/28/2013 Added Errata Footnotes.
Updated Packaging Information:
spec 001-09116 – Changed revision from *G to *H.
Updated to new template.
Document History Page (continued)
Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons,
0–6 Sliders
Document Number: 001-54459
Revision ECN Orig. of
Change
Submission
Date Description of Change
CY8C20XX6A/S
Document Number: 001-54459 Rev. *Y Page 52 of 53
*U 4185313 BVI 11/07/2013 Updated Features.
Updated Packaging Information:
spec 001-09116 – Changed revision from *H to *I.
*V 4622119 SSHH 01/13/2015 Added More Information.
*W 4825924 SSHH 07/07/2015 Updated Pinouts:
Updated 16-pin QFN (10 Sensing Inputs)[3, 4]:
Updated Table 1:
Added Note 7 and referred the same note in description of VSS pin.
Updated 24-pin QFN (17 Sensing Inputs) [8]:
Updated Table 2:
Added Note 12 and referred the same note in description of VSS pin.
Updated 24-pin QFN (15 Sensing Inputs (With USB)) [13]:
Updated Table 3:
Added Note 17 and referred the same note in description of VSS pin.
Updated 30-ball WLCSP (24 Sensing Inputs) [18]:
Updated Table 4:
Added Note 21 and referred the same note in description of VSS pin.
Updated 32-pin QFN (25 Sensing Inputs) [22]:
Updated Table 5:
Added Note 26 and referred the same note in description of VSS pin.
Updated 32-pin QFN (22 Sensing Inputs (With USB)) [27]:
Updated Table 6:
Added Note 31 and referred the same note in description of VSS pin.
Updated 48-pin SSOP (31 Sensing Inputs) [32]:
Updated Table 7:
Added Note 35 and referred the same note in description of VSS pin.
Updated 48-pin QFN (33 Sensing Inputs) [36]:
Updated Table 8:
Added Note 40 and referred the same note in description of VSS pin.
Updated 48-pin QFN (33 Sensing Inputs (With USB)) [41]:
Updated Table 9:
Added Note 45 and referred the same note in description of VSS pin.
Updated 48-pin QFN (OCD) (33 Sensing Inputs) [46]:
Updated Table 10:
Added Note 52 and referred the same note in description of VSS pin.
Updated Ordering Information:
Updated Table 41:
Updated part numbers.
Updated Packaging Information:
spec 001-13937 – Changed revision from *E to *F.
spec 001-13191 – Changed revision from *G to *H.
*X 5394582 SSHH 08/08/2016 Updated to new template.
Completing Sunset Review.
*Y 5741602 SSHH 05/18/2017 Updated Development Tool Selection:
Updated Accessories (Emulation and Programming):
Updated Table 40:
Updated part numbers.
Updated Ordering Information:
Updated Table 41:
Updated part numbers.
Updated to new template.
Document History Page (continued)
Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons,
0–6 Sliders
Document Number: 001-54459
Revision ECN Orig. of
Change
Submission
Date Description of Change
Document Number: 001-54459 Rev. *Y Revised May 18, 2017 Page 53 of 53
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
CY8C20XX6A/S
© Cypress Semiconductor Corporation, 2009–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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