Low Power, Rail-to-Rail Output, Precision
JFET Amplifiers
Data Sheet AD8641/AD8642/AD8643
Rev. E
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FEATURES
Low supply current: 250 μA max
Very low input bias current: 1 pA max
Low offset voltage: 750 μV max
Single-supply operation: 5 V to 26 V
Dual-supply operation: ±2.5 V to ±13 V
Rail-to-rail output
Unity-gain stable
No phase reversal
SC70 package
APPLICATIONS
Line-/battery-powered instruments
Photodiode amplifiers
Precision current sensing
Medical instrumentation
Industrial controls
Precision filters
Portable audio
ATE
GENERAL DESCRIPTION
The AD8641/AD8642/AD8643 are low power, precision JFET
input amplifiers featuring extremely low input bias current and
rail-to-rail output. The ability to swing nearly rail-to-rail at the
input and rail-to-rail at the output enables designers to buffer
CMOS DACs, ASICs, and other wide output swing devices in
single-supply systems. The outputs remain stable with
capacitive loads of more than 500 pF.
The AD8641/AD8642/AD8643 are suitable for applications
utilizing multichannel boards that require low power to manage
heat. Other applications include photodiodes, ATE reference
level drivers, battery management, and industrial controls.
The AD8641/AD8642/AD8643 are fully specified over the
extended industrial temperature range of –40°C to +125°C. The
AD8641 is available in 5-lead SC70 and 8-lead SOIC lead-free
packages. The AD8642 is available in 8-lead MSOP and 8-lead
SOIC lead-free packages. The AD8643 is available in 14-lead
SOIC and 16-lead, 3 mm × 3 mm, LFCSP lead-free packages.
PIN CONFIGURATIONS
OUT
1
+IN
3
VEE
2
VCC
5
–IN
4
AD8641
TOP VIEW
(Not to Scale)
05072-101
Figure 1. 5-Lead SC70 (KS-5)
NC
1
–IN
2
+IN
3
VEE
4
NC
8
VCC
7
OUT
6
NC
5
AD8641
TOP VIEW
(Not to Scale)
05072-102
NC = NO CONNECT
Figure 2. 8-Lead SOIC (R-8)
OUT
A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
AD8642
TOP VIEW
(Not to Scale)
05072-105
Figure 3. 8-Lead SOIC (R-8)
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
AD8642
TOP VIEW
(Not to Scale)
05072-064
Figure 4. 8-Lead MSOP (RM-8)
05072-103
OUT
A
1
OUT D
14
–IN A
2
–IN D
13
+IN A
3
+IN D
12
V+
4
V–
11
+IN B
5
+IN C
10
–IN B
6
–IN C
9
OUT B
7
OUT C
8
TOP VIEW
(Not to Scale)
AD8643
Figure 5. 14-Lead SOIC (R-14)
05072-104
12
11
10
9
+IN C
V–
+IN D
–IN D
1
–IN A
2
3
5
–IN B
OUT B
OUT C
–IN C
6
7
8
4
+IN B
V+
+IN A
16
15
14
13
AD8643
TOP VIEW
PIN 1
INDICATOR
NC
OUT A
OUT D
NC
NOTES
1. NC = NO CONNE CT.
2. EXPOSED PAD SHOULD BE CONNECTED TO V+.
Figure 6. 16-Lead LFCSP (CP-16) (Not Drawn to Scale)
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings ............................................................5
Thermal Resistance.......................................................................5
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 15
REVISION HISTORY
9/11—Rev. D to Rev. E
Changes to Thermal Resistance Section........................................ 5
7/11—Rev. C to Rev. D
Changes to Figure 6.......................................................................... 1
11/10—Rev. B to Rev. C
Changes to Figure 6.......................................................................... 1
Added Thermal Resistance Section and Table 4 .......................... 5
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 15
4/05—Rev. A to Rev. B
Added AD8643 ...................................................................Universal
Added 14-Lead SOIC.........................................................Universal
Added 16-Lead LFCSP.......................................................Universal
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 14
3/05—Rev. 0 to Rev. A
Added AD8642 ...................................................................Universal
Changes to General Description .....................................................1
Added Figure 3 and Figure 4............................................................1
Changes to Specifications.................................................................3
Changes to Absolute Maximum Ratings........................................5
Changes to Figure 22.........................................................................8
Changes to Figure 23.........................................................................9
Changes to Figure 41...................................................................... 12
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide.......................................................... 14
10/04—Initial Version: Revision 0
Data Sheet AD8641/AD8642/AD8643
Rev. E | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 50 750 μV
AD8643 LFCSP only 1 mV
–40°C < TA < +85°C 1.5 mV
+85°C < TA < +125°C, VCM = 1.5 V 1.6 mV
Input Bias Current IB 0.25 1 pA
–40°C < TA < +125°C 180 pA
Input Offset Current IOS 0.5 pA
–40°C < TA < +125°C 60 pA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.5 V 74 93 dB
Large Signal Voltage Gain AVO R
L = 10 kΩ, VO = 0.5 to 4.5 V 80 140 V/mV
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C 2.5 μV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH 4.95 V
I
L = 1 mA, –40°C to +125°C 4.94 V
Output Voltage Low VOL 0.05 V
I
L = 1 mA, –40°C to +125°C 0.01 0.05 V
Output Current IOUT ±6 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 5 V to 26 V 90 107 dB
Supply Current/Amplifier ISY 195 250 μA
–40°C < TA < +125°C 270 μA
DYNAMIC PERFORMANCE
Slew Rate SR 2 V/μs
Gain Bandwidth Product GBP AD8641, AD8642 3 MHz
AD8643 2.5 MHz
Phase Margin Øm 50 Degrees
NOISE PERFORMANCE
Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4.0 μV p-p
Voltage Noise Density eN f = 1 kHz 28.5 nV/√Hz
Current Noise Density iN f = 1 kHz 0.5 fA/√Hz
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 4 of 16
VS= ±13 V, VCM = 0 V, TA =25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 70 750 μV
AD8643 LFCSP only 1 mV
–40° < TA < +125°C 1.5 mV
Input Bias Current IB 0.25 1 pA
–40°C < TA < +125°C 260 pA
Input Offset Current IOS 0.5 pA
–40°C < TA < +125°C 65 pA
Input Voltage Range –13 +10 V
Common-Mode Rejection Ratio CMRR VCM = −13 V to +10 V 90 107 dB
Large Signal Voltage Gain AVO R
L = 10 kΩ, VO = –11 V to +11 V 215 290 V/mV
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C 2.5 μV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH +12.95 V
I
L = 1 mA, –40°C to +125°C +12.94 V
Output Voltage Low VOL –12.95 V
I
L = 1 mA, –40°C to +125°C –12.94 V
Output Current IOUT ±12 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±13 V 90 107 dB
Supply Current/Amplifier ISY 200 290 μA
–40°C < TA < +125°C 330 μA
DYNAMIC PERFORMANCE
Slew Rate SR 3 V/μs
Gain Bandwidth Product GBP 3.5 MHz
Phase Margin Øm 60 Degrees
NOISE PERFORMANCE
Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4.2 μV p-p
Voltage Noise Density eN f = 1 kHz 27.5 nV/√Hz
Current Noise Density iN f = 1 kHz 0.5 fA/√Hz
Data Sheet AD8641/AD8642/AD8643
Rev. E | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 3.
Parameter Rating
Supply Voltage 27.3 V
Input Voltage VS− to VS+
Differential Input Voltage ±Supply Voltage
Output Short-Circuit Duration Indefinite
Storage Temperature Range
KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range
KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 4-layer board. For the LFCSP
package, solder the exposed pad to a copper plane, which
should be connected to V+.
Table 4.
Package Type θJA θ
JC Unit
5-Lead SC70 (KS) 430 149 °C/W
8-Lead SOIC (R) 121 43 °C/W
8-Lead MSOP (RM) 142 45 °C/W
14-Lead SOIC (R) 110 36 °C/W
16-Lead LFCSP (CP) 81 16 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
0
10
20
30
40
50
60
70
FREQUENCY
–0.60
–0.55
–0.50
–0.45
–0.40
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
V
OS
(mV)
05072-002
80
V
SY
=
±13V
Figure 7. Input Offset Voltage
NUMBER OF AMPLIFIERS
OFFSET VOLTAGE (μV/°C)
05072-003
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
16
14
12
10
8
6
4
2
0
V
SY
=
±13V
Figure 8. Offset Voltage Drift
0
10
20
30
40
50
60
70
FREQUENCY
–0.60
–0.55
–0.50
–0.45
–0.40
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
V
OS
(mV)
05072-004
V
SY
=
±
2.5V
Figure 9. Input Offset Voltage
NUMBER OF AMPLIFIERS
T
C
V
OS
(μV/°C)
05072-005
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
0
2
4
6
8
10
12
14
16
18
20 V
SY
= 5V
V
CM
= 1.5V
Figure 10. Offset Voltage Drift
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
INPUT BIAS (pA)
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15
VCM (V)
05072-006
VSY = ±13V
TA = 25°C
Figure 11. Input Bias Current vs. VCM
–
0.4
–
0.3
–
0.2
–
0.1
0
0.1
INPUT BIAS (pA)
0.2
0.3
0.4
–15.0 –12.5 –10.0 –7.5 –5.0 –2.5
0 2.5 5.0 7.5 10.0 12.5 15.0
V
CM
(V)
05072-007
V
SY
= ±13V
T
A
= 25°C
0.5
–
0.5
Figure 12. Input Bias Current vs. VCM
Data Sheet AD8641/AD8642/AD8643
Rev. E | Page 7 of 16
INPUT BIAS CURRENT (pA)
0.1
1
10
100
1000
50 750 25 100 125 150
TEMPERATURE (°C)
05072-008
V
SY
=
±13V
Figure 13. Input Bias Current vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
INPUT BIAS (pA)
–5 –4 –3 –2 –1 0 1 2 3 4 5
V
CM
(V)
05072-009
V
SY
=
+5V OR ±5V
Figure 14. Input Bias Current vs. VCM
V
OS
(μV)
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15
V
CM
(V)
05072-010
0
–100
0
200
600
800
1000
400
100
500
700
900
300
V
SY
=
±13V
Figure 15. Input Offset Voltage vs. VCM
–500
–400
–300
–200
–100
0
100
200
300
400
500
V
OS
(μV)
1.0 1.50 0.5 2.0 2.5
V
CM
(V)
05072-011
V
SY
=
5V
Figure 16. Input Offset Voltage vs. VCM
OPEN-LOOP GAIN (V/V)
10k
1M
100k
10M
LOAD RESISTANCE (kΩ)
0.1 101 100
05072-012
V
SY
= ±13V
V
SY
= ±2.5V
Figure 17. Open-Loop Gain vs. Load Resistance
A
VO
(V/mV)
1
100
10
1000
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
05072-013
A. V
SY
= ±13V, V
O
= ±11V, R
L
= 10kΩ
B. V
SY
= ±13V, V
O
= ±11V, R
L
= 2kΩ
C. V
SY
= +5V, V
O
= +0.5V/+4.5V, R
L
= 10kΩ
D. V
SY
= +5V, V
O
= +0.5V/+4.5V, R
L
= 2kΩ
E. V
SY
= +5V, V
O
= +0.5V/+4.5V, R
L
= 600Ω
A
B
C
D
E
Figure 18. Open-Loop Gain vs. Temperature
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 8 of 16
–600
–400
–200
–300
–500
0
–100
OFFSET VOLTAGE (μV)
200
100
400
300
600
500
–5 0–15 –10 5 10 15
OUTPUT VOLTAGE (V)
05072-014
10kΩ1kΩ
100kΩ
V
SY
=
±13V
Figure 19. Input Error Voltage vs. Output Voltage for Resistive Loads
–350
–250
–150
–200
–300
–50
–100
INPUT VOLTAGE (μV)
50
0
150
100
250
200
0 50 100 150 200 250 300 350
OUTPUT VOLTAGE FROM SUPPLY RAIL (mV)
05072-015
RL = 1kΩ
POS RAIL
NEG RAIL
RL = 10kΩ
RL = 2kΩ
RL = 100kΩ
RL = 100kΩ
RL = 10kΩ
RL = 1kΩ
RL = 2kΩ
V
SY
=
±
5V
Figure 20. Input Error Voltage vs. Output Voltage
Within 300 mV of Supply Rails
0
100
200
300
400
500
ISY (μA)
600
700
800
4 8 12 16 20 24 28
VSY (V)
05072-016
+25°C
–55°C
+125°C
Figure 21. Quiescent Current vs. Supply Voltage at Different Temperatures
SATURATION VOLTAGE (mV)
1
10
100
1000
10000
0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)
05072-017
–
V
SY
– V
OL
V
SY
– V
OH
V
SY
=
±
13V
Figure 22. Output Saturation Voltage vs. Load Current
SATURATION VOLTAGE (mV)
1
10
100
1000
10000
0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)
05072-018
V
OL
V
SY
–V
OH
V
SY
=5V
Figure 23. Output Saturation Voltage vs. Load Current
–30 –135
–90
–45
0
45
90
135
180
225
270
315
–20
–10
0
10
20
30
40
50
60
70
10k 100k 1M 10M
PHASE (Degrees)
GAIN
PHASE
V
SY
=
±
13V
R
L
= 2k
Ω
C
L
= 40pF
GAIN (dB)
FREQUENCY (Hz)
05072-019
Figure 24. Open-Loop Gain and Phase Margin vs. Frequency
Data Sheet AD8641/AD8642/AD8643
Rev. E | Page 9 of 16
–30 –135
–90
–45
0
45
90
135
180
225
270
315
–20
–10
0
10
20
30
40
50
60
70
10k 100k 1M 10M
PHASE (Degrees)
GAIN
PHASE
GAIN (dB)
FREQUENCY (Hz)
05072-020
V
SY
= 5V
R
L
= 2k
Ω
C
L
= 40pF
Figure 25. Open-Loop Gain and Phase Margin vs. Frequency
FREQUENCY (Hz)
–30
–20
–10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
V
SY
=
±
13V
R
L
= 2k
Ω
C
L
= 40pF
G = +100
G = +1
G = +10
05072-021
Figure 26. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
–30
–20
–10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
G = +100
G = +1
G = +10
05072-022
VSY = 5V
RL = 2k
Ω
CL = 40pF
Figure 27. Closed-Loop Gain vs. Frequency
–60
–40
–20
0
20
40
60
80
100
120
140
1k 10k 100k 1M 10M
FREQUENCY (Hz)
CMRR (dB)
05072-023
VSY =
±
13V
Figure 28. CMRR vs. Frequency
–60
–40
–20
0
20
40
60
80
100
120
140
1k 10k 100k 1M 10M
FREQUENCY (Hz)
CMRR (dB)
05072-024
VSY =5V
Figure 29. CMRR vs. Frequency
–60
–40
–20
0
20
40
60
80
100
120
140
1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
05072-025
+PSRR
–PSRR
VSY =
±
13V
Figure 30. PSRR vs. Frequency
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 10 of 16
–60
–40
–20
0
20
40
60
80
100
120
140
1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
05072-026
VSY =5V
+PSRR
–PSRR
Figure 31. PSRR vs. Frequency
0.01
0.1
1
10
100
1000
Z
OUT
(Ω)
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
05072-027
G = +100
G = +10
G = +1
V
SY
=
±
13V
Figure 32. Output Impedance vs. Frequency
0.01
0.1
1
10
100
1000
Z
OUT
(
Ω
)
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
05072-028
G = +100
G = +10
G = +1
V
SY
=5V
Figure 33. Output Impedance vs. Frequency
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
INPUT BIAS (pA)
–5 –4 –3 –2 –1 0 1 2 3 4 5
V
CM
(V)
05072-009
05072-029
CH1 10.0V CH2 10.0V M400
μ
s A CH1 1.00V
1
T 0.00000s
2
V
IN
V
OUT
T
V
SY
=
±
13V
Figure 34. No Phase Reversal
–15
–10
–5
0
5
10
15
OUTPUT SWING (V)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SETTLING TIME (μs)
05072-030
VS = ±13V
GAIN = +5
TS – (0.1%)
TS – (1%)
TS + (0.1%)
TS + (1%)
Figure 35. Output Swing and Error vs. Settling Time
0
10
20
30
40
50
60
70
OVERSHOOT (%)
CAPACITANCE (pF)
1 10010 1000
05072-031
OS+
OS–
V
S
=
±
13V
R
L
= 10k
Ω
V
IN
= 100mV p-p
A
V
= +1
Figure 36. Small Signal Overshoot vs. Load Capacitance
Data Sheet AD8641/AD8642/AD8643
Rev. E | Page 11 of 16
0
10
20
30
40
50
60
70
OVERSHOOT (%)
CAPACITANCE (pF)
1 10010 1000
05072-032
OS+
OS–
V
S
=
±
2.5V
R
L
= 10k
Ω
V
IN
= 100mV p-p
A
V
= +1
Figure 37. Small Signal Overshoot vs. Load Capacitance
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
INPUT BIAS (pA)
–5 –4 –3 –2 –1 0 1 2 3 4 5
V
CM
(V)
05072-009
05072-033
CH1 1.00V M1.00s A CH1 –20.0V
1
V
S
= ±13V
G = +1M
CH1 p-p = 4.26V
Figure 38. 0.1 Hz to 10 Hz Noise
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
INPUT BIAS (pA)
–5 –4 –3 –2 –1 0 1 2 3 4 5
V
CM
(V)
0
5072-009
05072-034
CH1 1.00V M1.00s A CH1 –20.0V
1
V
S
= ±2.5V
G = +1M
CH1 p-p = 4.06V
Figure 39. 0.1 Hz to 10 Hz Noise
VOLTAGE NOISE DENSITY (nV/ Hz)
1
10
100
1k
FREQUENCY (Hz)
10 1k100 10k
05072-035
V
SY
=
±13V
Figure 40. Voltage Noise Density
VOLTAGE NOISE DENSITY (nV/ Hz)
1
10
100
1k
FREQUENCY (Hz)
10 1k100 10k
05072-036
V
SY
=
5V
Figure 41. Voltage Noise Density
0.000001
0.00001
0.0001
0.001
1k10012
THD + NOISE (%)
FREQUENCY (Hz)
05072-037
0.004
0k
1V p-p INPUT
2V p-p INPUT
4V p-p INPUT
8V p-p INPUT
V
SY
= ±13V
LOAD = 100kΩ
GAIN = +1
10k
Figure 42. Total Harmonic Distortion + Noise vs. Frequency
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 12 of 16
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
(dB)
20 100 1k 10k 100k
FREQUENCY (Hz)
05072-041
–
+
V
IN
2kΩ
–
+
2kΩ
2kΩ
20kΩ
V
IN
= 18V p-p
V
IN
= 4.5V p-p
V
IN
= 9V p-p
Figure 43. Channel Separation
Data Sheet AD8641/AD8642/AD8643
Rev. E | Page 13 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-203-AA
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0.22
0.08
312
45
0.65 BSC
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
Figure 44. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 45. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 14 of 16
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 46. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS
(I N PARENTHESE S ) ARE ROUNDED-O FF MIL LI M E TER EQUIVALENTS FO R
REFE RE NCE ONLYAND ARE NO T APPRO P RIATE FOR USE IN DESIGN.
COMP LI ANT TO JEDEC S TANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 ( 0.3445)
8.55 ( 0.3366)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 47. 14-Lead Standard Small Outline Package [SOIC_N]
(R-14)
Dimensions shown in millimeters and (inches)
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
1
0.50
BSC
0.60 MAX
PIN1
INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
07-17-2008-A
Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad (CP-16-3)
Dimensions shown in millimeters
Data Sheet AD8641/AD8642/AD8643
Rev. E | Page 15 of 16
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8641AKSZ-R2 −40°C to +125°C 5-Lead SC70 KS-5 A07
AD8641AKSZ-REEL7 −40°C to +125°C 5-Lead SC70 KS-5 A07
AD8641AKSZ-REEL −40°C to +125°C 5-Lead SC70 KS-5 A07
AD8641ARZ −40°C to +125°C 8-lead SOIC_N R-8
AD8641ARZ-REEL7 −40°C to +125°C 8-lead SOIC_N R-8
AD8641ARZ-REEL −40°C to +125°C 8-lead SOIC_N R-8
AD8642ARMZ −40°C to +125°C 8-lead MSOP RM-8 A0A
AD8642ARMZ-REEL −40°C to +125°C 8-lead MSOP RM-8 A0A
AD8642ARZ −40°C to +125°C 8-lead SOIC_N R-8
AD8642ARZ-REEL7 −40°C to +125°C 8-lead SOIC_N R-8
AD8642ARZ-REEL −40°C to +125°C 8-lead SOIC_N R-8
AD8643ARZ −40°C to +125°C 14-lead SOIC_N R-14
AD8643ARZ-REEL7 −40°C to +125°C 14-lead SOIC_N R-14
AD8643ARZ-REEL −40°C to +125°C 14-lead SOIC_N R-14
AD8643ACPZ-R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA
AD8643ACPZ-REEL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA
AD8643ACPZ-REEL −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA
1 Z = RoHS Compliant Part.
AD8641/AD8642/AD8643 Data Sheet
Rev. E | Page 16 of 16
NOTES
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05072-0-9/11(E)
