74LCX125MTC - Fairchild - Datasheet.Directory

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

74LCX125 Rev. 1.7.0

February 2008

74LCX125

Low Voltage Quad Buffer with 5V Tolerant

Inputs and Outputs

Features

■

5V tolerant inputs and outputs

■

2.3V–3.6V V

specifications provided

■

6.0ns t

max. (V

3.3V), 10µA I

max.

■

Power down high impedance inputs and outputs

■

Supports live insertion/withdrawal

(1)

■

±24mA output drive (V

3.0V)

■

Latch-up performance exceeds JEDEC 78 conditions

■

ESD performance:

– Human body model

2000V

– Machine model

100V

■

Leadless DQFN package

Note:

1. To ensure the high-impedance state during power up

or down, OE should be tied to V

through a pull-up

resistor: the minimum value of the resistor is

determined by the current-sourcing capability of the

driver.

General Description

The LCX125 contains four independent non-inverting

buffers with 3-STATE outputs. The inputs tolerate volt-

ages up to 7V allowing the interface of 5V systems to 3V

systems.

The 74LCX125 is fabricated with an advanced CMOS

technology to achieve high speed operation while main-

taining CMOS low power dissipation.

Ordering Information

Note:

2. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LCX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX125BQX

(2)

MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Implements proprietary noise/EMI reduction circuitry

74LCX125 Rev. 1.7.0 2

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Connection Diagrams

Pin Assignments for SOIC, SOP, and TSSOP

(Top View)

Pad Assignments for DQFN

(Top Through View)

Pin Description

Logic Symbol

IEEE/IEC

Truth Table

HIGH Voltage Level

LOW Voltage Level

High Impedance

Immaterial

Pin Names Description

Inputs

Output Enable Inputs

Outputs

Inputs Output

LLL

LHH

HXZ

74LCX125 Rev. 1.7.0 3

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Note:

3. I

Absolute Maximum Rating must be observed.

Recommended Operating Conditions

(4)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Note:

4. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

Supply Voltage –0.5V to +7.0V

DC Input Voltage –0.5V to +7.0V

DC Output Voltage,

Output in 3-STATE –0.5V to +7.0V

Output in HIGH or LOW State

(3)

–0.5V to V

+ 0.5V

DC Input Diode Current, V

GND –50mA

DC Output Diode Current

GND –50mA

+50mA

DC Output Source/Sink Current ±50mA

DC Supply Current per Supply Pin ±100mA

GND

DC Ground Current per Ground Pin ±100mA

STG

Storage Temperature –65°C to +150°C

Symbol Parameter Min. Max. Units

Supply Voltage

Operating 2.0 3.6 V

Data Retention 1.5 3.6

Input Voltage 0 5.5 V

Output Voltage

HIGH or LOW State 0 V

3-STATE 0 5.5

Output Current

3.0V–3.6V ±24 mA

2.7V–3.0V ±12

2.3V–2.7V ±8

Free-Air Operating Temperature –40 85 °C

∆

V Input Edge Rate, V

0.8V–2.0V, V

3.0V 0 10 ns

74LCX125 Rev. 1.7.0 4

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

DC Electrical Characteristics

Note:

5. Outputs disabled or 3-STATE only.

AC Electrical Characteristics

Note:

6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction,

either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

Symbol Parameter V

(V) Conditions

–40°C to +85°C

UnitsMin. Max.

HIGH Level Input Voltage 2.3–2.7 1.7 V

2.7–3.6 2.0

LOW Level Input Voltage 2.3–2.7 0.7 V

2.7–3.6 0.8

HIGH Level Output Voltage 2.3–3.6 I

–100µA V

– 0.2 V

2.3 I

–8mA 1.8

2.7 I

–12mA 2.2

3.0 I

–18mA 2.4

–24mA 2.2

LOW Level Output Voltage 2.3–3.6 I

100µA 0.2 V

2.3 I

8mA 0.6

2.7 I

12mA 0.4

3.0 I

16mA 0.4

24mA 0.55

Input Leakage Current 2.3–3.6 0

≤

VI ≤ 5.5V ±5.0 µA

IOZ 3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V,

VI = VIH or VIL

±5.0 µA

IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA

ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA

3.6V ≤ VI, VO ≤ 5.5V(5) ±10

∆ICC Increase in ICC per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA

Symbol Parameter

TA = –40°C to +85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V,

CL = 50 pF

VCC = 2.7V,

CL = 50 pF

VCC = 2.5V ± 0.2V,

CL = 30 pF

Min. Max. Min. Max. Min. Max.

tPHL, tPLH Propagation Delay 1.5 6.0 1.5 6.5 1.5 7.2 ns

tPZL, tPZH Output Enable Time 1.5 7.0 1.5 8.0 1.5 9.1 ns

tPLZ, tPHZ Output Disable Time 1.5 6.0 1.5 7.0 1.5 7.2 ns

tOSHL, tOSLH Output to Output Skew(6) 1.0 ns

74LCX125 Rev. 1.7.0 5

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Dynamic Switching Characteristics

Capacitance

Symbol Parameter VCC (V) Conditions

TA = 25°C

UnitTypical

VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6

VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7.0 pF

COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8.0 pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25.0 pF

74LCX125 Rev. 1.7.0 6

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

AC Loading and Waveforms (Generic for LCX Family)

Figure 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V

VCC x 2 at VCC = 2.5 ± 0.2V

tPZH, tPHZ GND

Symbol

VCC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

Vmi 1.5V 1.5V VCC / 2

Vmo 1.5V 1.5V VCC / 2

VxVOL + 0.3V VOL + 0.3V VOL + 0.15V

VyVOH – 0.3V VOH – 0.3V VOH – 0.15V

74LCX125 Rev. 1.7.0 7

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Schematic Diagram (Generic for LCX Family)

74LCX125 Rev. 1.7.0 8

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Tape and Reel Specification

Tape Format for DQFN

Tape Dimensions inches (millimeters)

Reel Dimensions inches (millimeters)

Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status

BQX Leader (Start End) 125 (Typ.) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (Typ.) Empty Sealed

Tape Size A B C D N W1 W2

12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)

74LCX125 Rev. 1.7.0 9

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Physical Dimensions

Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X45°

0.10

BC A

14 B

SEE DETAIL A

5.60

0.65

1.70 1.27

8.75

8.50

7.62

6.00 4.00

3.80

(0.33)

1.27 0.51

0.35

1.75 MAX

1.50

1.25 0.25

0.10 0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

0.50

0.25

74LCX125 Rev. 1.7.0 10

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX125 Rev. 1.7.0 11

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 5. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX125 Rev. 1.7.0 12

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

F. DRAWING FILE NAME: MTC14REV6

R0.09 min

12.00°TOP & BOTTO

0.43 TYP

1.00

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

R0.09min

E. LANDPATTERN STANDARD: SOP65P640X110-14M

0.65

6.10

1.65

0.45

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS

74LCX125 Rev. 1.7.0 13

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Thefollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx®

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK®

EZSWITCH™ *

™

Fairchild®

Fairchild Semiconductor®

FACT Quiet Series™

FACT®

FAST®

FastvCore™

FlashWriter®*

FPS™

FRFET®

Global Power ResourceSM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC®

OPTOPLANAR®

PDP-SPM™

Power220®

POWEREDGE®

Power-SPM™

PowerTrench®

Programmable Active Droop™

QFET®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SupreMOS™

SyncFET™®

The Power Franchise®

TinyBoost™

TinyBuck™

TinyLogic®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC®

Ultra FRFET™

UniFET™

VCX™

*EZSWITCH™ and FlashWriter®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary First Production

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

Obsolete Not In Production

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I33

74LCX125 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs