8-Bit Latches
fax id: 7014
CY54/74FCT373T
CY54/74FCT573T
Cypress Semiconductor Corporation • 3 9 01 North First Str e et • S an Jo se • CA 95134 • 408-943-2600
May 1994 – Revised March 18, 1997
1CY54/74FCT573T
Features
• Function and pinout compatible with FCT, and F logic
• FCT-C speed at 4.2 ns max. (Com’ l),
FCT-A speed at 5.2 ns max. (Com’ l)
• Reduced VOH (typical ly = 3.3V) versions of equiv alent
FCT functions
• Edge-rate con trol circuitry for significantly improv ed
noise c h aracteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Extended commercial range of −40°C to +85°C
• Fully compatible with TTL inp ut and outp ut logic levels
• Sink current 64 mA ( Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
Functional Description
The FCT373T and FCT573T consist of eight latches with
three-state outputs for bus organize d applic ation s. When latch
enable (LE) is HIGH, the flip-flops appear tr ansparent to the
data. Data that meets the required set-up times are latched
when LE tr ansitions fr om HIGH to LOW. Data appears on the
bus when the (OE) is LOW. When o utput enable is HI GH, t he
bus output is in th e im pedance state. In this mode, data ma y
be entered into the latches. The FCT573T is identical to the
FCT373T except for the f low-through pinout , which simpli fies
board design.
The outputs are designed with a power-off disabl e feature to
allow for li ve insertion of boards.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10 11
12
16
17
18
19
20
13
14
VCC
15
DIP/SOIC/QSOP
T op Vie w
O0
D0
D1
O2
D2
D3
O3
D7
D6
O6
O5
D5
D4
O4
LE
OE
GND
O7
O1
1
2
3
4
5
6
7
8
9
10 11
12
16
17
18
19
20
13
14
VCC
15
DIP/SOIC/QSOP
Top View
D0
D1
D2
D4
D5
D6
D7
O1
O2
O3
O4
O5
O6
O7
LE
OE
GND
O0
D3
LE
OE
D0
O0
D1
O1
D2
O2
D3
O3
D4
O4
D5
O5
D6
O6
D7
O7
CP D
Q
O0
D0
LE
OE
CP D
Q
O1
D1
CP D
Q
O2
D2
CP D
Q
O3
D3
CP D
Q
O4
D4
CP D
Q
O5
D5
CP D
Q
O6
D6
CP D
Q
O7
D7
FCT373T FCT573T
Logic Symbol
CY54/74FCT373T
CY54/74FCT573T
2
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Supply Voltage t o Ground Potential ...............–0.5V to +7.0V
DC Input Voltage .. .............. ............................ –0. 5V to +7.0V
DC Output Volta ge .........................................–0. 5V to +7.0V
DC Output Current (Maximum Sink Cur rent/ Pin) ...... 120 mA
Power Dissipation. .........................................................0.5W
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Function Table[1]
Inputs Outputs
OE LE D O
L H H H
L H L L
L L X Q0
H X X Z Operating Range
Range Range Ambient
Temperature VCC
Commercial DT 0°C to +70°C 5V ± 5%
Commercial T, AT, CT –40°C to +85°C 5V ± 5%
Military[4] All –55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VOH Output HIGH Volt a ge VCC=Min., IOH= –32 mA Com’l 2.0 V
VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
VCC=Min., IOH=–12 mA Mil 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V
VCC=Min., IOL=32 mA Mil 0.3 0.55 V
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
VHHysteresis[6] All inputs 0.2 V
VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
IIInput HIGH Current VCC=Max., VIN=VCC 5µA
IIH Input HIGH Current VCC=Max., VIN=2.7V ±1µA
IIL Input LOW Current VCC=Max., VIN=0.5V ±1µA
IOZH Off State HIGH-Level Output
Current VCC=Max., VOUT=2.7V 10 µA
IOZL Off State LOW-Level
Output Current VCC=Max., V OUT=0.5V –10 µA
IOS Output Short Circuit Curre nt[7] VCC=Max., VOUT=0.0V –60 –120 –225 mA
IOFF Power-Off Disable VCC=0V, VOUT=4.5V ±1µA
Notes:
1. H = HIGH Voltage Level
L = LO W Voltage Level
X = Don’t Care
Z = HIGH Impedance
Qn = Previous state o f flip flops (Qn-1)
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unuse d inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. TA is the “instant on” case temperature.
5. Typical values are at VCC=5.0V, TA=+25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one s econd. The use of high-speed test apparatus and/or sample
and hold tec hniques are preferable in order to min imize internal chip heating and more accurately reflec t operational values. O therwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
CY54/74FCT373T
CY54/74FCT573T
3
Capacitance[6]
Parameter Description Typ.[5] Max. Unit
CIN Input Capacitanc e 6 10 pF
COUT Output Capacitance 8 12 pF
Power Supply Characteristics
Parameter Description Test Conditions Typ.[5] Max. Unit
ICC Quiescent Power Supply Current V CC=Max., VIN ≤ 0.2V, VIN ≥ VCC – 0.2V 0.1 0.2 mA
∆ICC Quiescent Power Supply Current
(TTL inputs HIGH) VCC=Max ., V IN=3.4V, f1=0, Outpu ts Op en[8] 0.5 2.0 mA
ICCD Dynamic Power Supply Current[9] VCC=M ax., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND, VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
0.6 0.12 mA/MHz
ICTotal Power Supply Current[10] VCC=Max., 50% Duty Cycle, Outputs Open,
O ne Bit Toggl ing at f1=10 MHz,
OE=GND, LE=VCC
VIN ≤ 0.2V or V IN ≥ VCC – 0.2V
0.7 1.4 mA
VCC=Max., 50% Duty Cycle, Outputs Open,
O ne Bit Toggl ing at f1=10 MHz,
OE=GND, LE=VCC, VIN=3.4V or VIN=GND
1.0 2.4 mA
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=2.5 MH z,
OE=GND, LE=VCC,
VIN ≤ 0.2V or V IN ≥ VCC – 0.2V
1.3 2.6[11] mA
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=2.5 MH z,
OE=GND, LE=VCCVIN=3.4V or VIN=GND
3.3 10.6[11] mA
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculatio ns.
10. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
CY54/74FCT373T
CY54/74FCT573T
4
e
Switching Characteristics Over the Operatin g Ra nge[12]
Parameter Description
FCT373T/FCT573T FCT373AT/FCT573AT
Unit Fig.
No.[13]
Military Commercial Military Commercial
Min. Max. Min. Max. Min. Max. Min. Max.
tPLH
tPHL Propagation Del a y
D to O 1.5 8.5 1.5 8.0 1.5 5.6 1. 5 5.2 ns 1, 3
tPLH
tPHL Propagation Del a y
LE to O 2.0 15.0 2.0 13.0 2.0 9.8 2.0 8.5 ns 1, 5
tPZH
tPZL Output Enable Time 1.5 13.5 1.5 12.0 1.5 7.5 1.5 6.5 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time 1.5 10.0 1.5 7.5 1.5 6.5 1. 5 5.5 ns 1, 7, 8
tSSet-Up Tim e
HIGH to LOW
D to LE
2.0 2.0 2.0 2.0 ns 9
tHSet-Up Tim e
HIGH to LOW
D to LE
1.5 1.5 1.5 1.5 ns 9
tWLE Pulse
Width HIGH 6.0 6.0 6.0 5.0 ns 5
Parameter Description
FCT373CT/
FCT573CT FCT373DT/
FCT573DT
Unit Fig. No.[13]
Commercial Commercial
Min. Max. Min. Max.
tPLH
tPHL Propagation Delay D t o O 1.5 4.2 1.5 3.8 ns 1, 3
tPLH
tPHL Propagation Delay LE to O 2.0 5.5 2.0 4.0 n s 1, 5
tPZH
tPZL Outp ut Enable Tim e 1.5 5.5 1.5 4.8 ns 1, 7, 8
tPHZ
tPLZ Output D isable Time 1.5 5.0 1.5 4.0 ns 1, 7, 8
tSSet-Up Time, HIGH to L OW D to LE 2.0 1.5 ns 9
tHSet-Up Time, HIGH to L OW D to LE 1.5 1.0 ns 9
tWLE Pulse Width HIGH 5.0 3.0 ns 5
Shaded areas contain preliminary information.
Note:
12. Minimu m limi t s a re guarante ed but not tested on Propagati on Dela ys.
13. See “Parameter Measurement Information” in the Gener al Information section.
CY54/74FCT373T
CY54/74FCT573T
5
Ordering Information–FCT373T
Speed
(ns) Ordering Code Package
Name Package Ty pe Operating
Range
3.8 CY74FCT373DTQC Q5 20- Lead (150-Mil) QSOP Commercial
CY74FCT373DTSOC S5 20- Lead (300-Mil) Molded SOIC
4.2 CY74FCT373CTQC Q5 20-Lead (1 50-Mil) QSOP Commercial
CY74FCT373CTSOC S5 20-Lead (300-Mil) Molded SOIC
5.2 CY74FCT373ATPC P5 20-Lead (300-Mil) Molded DIP Commercial
CY74FCT373ATQC Q5 20-Lead (1 50-Mil) QSOP
CY74FCT373ATSOC S5 20-Lead (300-Mil) Molded SOIC
5.6 CY54FCT373ATDMB D6 20-Lead (300-Mil) CerDIP Military
8.0 CY74FCT373TQC Q5 20-Lead (1 50-Mil) QSOP Commercial
CY74FCT373TSOC S5 20-Lead (300-Mil) Molded SOIC
8.5 CY54FCT373TDMB D6 20-Lead (300-Mil) CerDIP Military
Orde rin g Inf orm a tio n—F CT 5 73 T
Speed
(ns) Ordering Code Package
Name Package Ty pe Operating
Range
3.8 CY74FCT573DTQC Q5 20- Lead (150-Mil) QSOP Commercial
CY74FCT573DTSOC S5 20- Lead (300-Mil) Molded SOIC
4.2 CY74FCT573CTQC Q5 20-Lead (1 50-Mil) QSOP Commercial
CY74FCT573CTSOC S5 20-Lead (300-Mil) Molded SOIC
5.2 CY74FCT573ATPC P5 20-Lead (300-Mil) Molded DIP Commercial
CY74FCT573ATQC Q5 20-Lead (1 50-Mil) QSOP
CY74FCT573ATSOC S5 20-Lead (300-Mil) Molded SOIC
5.6 CY54FCT573ATDMB D6 20-Lead (300-Mil) CerDIP Military
8.0 CY74FCT573TQC Q5 20-Lead (1 50-Mil) QSOP Commercial
CY74FCT573TSOC S5 20-Lead (300-Mil) Molded SOIC
8.5 CY54FCT573TDMB D6 20-Lead (300-Mil) CerDIP Military
Shaded areas contain preliminary information.
Document #: 38-00272-B
CY54/74FCT373T
CY54/74FCT573T
6
Package Diagrams
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835 D-8 Config.A
20-Lead (300-Mil) Molded DIP P5
CY54/74FCT373T
CY54/74FCT573T
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cy press Semi conductor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
20-Lead Quarter Size Outline Q5
20-Lead (300-Mil) Molded SOIC S5
