LCMXO2-640HC-4SG48I - LATTICE SEMICONDUCTOR

MachXO2™ Family Data Sheet

DS1035 Version 3.3, March 2017

www.latticesemi.com 1-1 DS1035 Introduction_02.2

May 2016 Data Sheet DS1035

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and 

18 to 334 I/Os

Ultra Low Power Devices

• Advanced 65 nm low power process

• As low as 22 µW standby power

• Programmable low swing differential I/Os

• Stand-by mode and other power saving options

Embedded and Distributed Memory

• Up to 240 kbits sysMEM™ Embedded Block

RAM

• Up to 54 kbits Distributed RAM

• Dedicated FIFO control logic

On-Chip User Flash Memory

• Up to 256 kbits of User Flash Memory

• 100,000 write cycles

• Accessible through WISHBONE, SPI, I2C and

JTAG interfaces

• Can be used as soft processor PROM or as

Flash memory

Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated gearing logic

• 7:1 Gearing for Display I/Os

• Generic DDR, DDRX2, DDRX4

• Dedicated DDR/DDR2/LPDDR memory with

DQS support

High Performance, Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide

range of interfaces:

– LVCMOS 3.3/2.5/1.8/1.5/1.2

– LVTTL

–PCI

– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

– SSTL 25/18

– HSTL 18

– Schmitt trigger inputs, up to 0.5 V hysteresis

• I/Os support hot socketing

•On-chip differential termination

• Programmable pull-up or pull-down mode

Flexible On-Chip Clocking

• Eight primary clocks

• Up to two edge clocks for high-speed I/O 

interfaces (top and bottom sides only)

• Up to two analog PLLs per device with 

fractional-n frequency synthesis

– Wide input frequency range (7 MHz to 

400 MHz)

Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• Single-chip, secure solution

• Programmable through JTAG, SPI or I2C

• Supports background programming of non-vola-

tile memory

• Optional dual boot with external SPI memory

TransFR™ Reconfiguration

• In-field logic update while system operates

Enhanced System Level Support

• On-chip hardened functions: SPI, I2C, timer/

counter

• On-chip oscillator with 5.5% accuracy

• Unique TraceID for system tracking

• One Time Programmable (OTP) mode

• Single power supply with extended operating

range

• IEEE Standard 1149.1 boundary scan

• IEEE 1532 compliant in-system programming

Broad Range of Package Options

• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,

fpBGA, QFN package options

• Small footprint package options

– As small as 2.5 mm x 2.5 mm

• Density migration supported

•Advanced halogen-free packaging

MachXO2 Family Data Sheet

Introduction

1-2

Introduction

MachXO2 Family Data Sheet

Table 1-1. MachXO2™ Family Selection Guide

XO 2- 256 XO 2- 640 XO2-640U1XO2-1200 XO2-1200U1XO2-2000 XO2-2000U1XO2-4000 XO2-7000

LUTs 256 640 640 1280 1280 2112 2112 4320 6864

Distributed RAM (kbits) 2 5 5 10 10 16 16 34 54

EBR SRAM (kbits) 0 18 64 64 74 74 92 92 240

Number of EBR SRAM Blocks (9

kbits/block) 027788101026

UFM (kbits) 0 24 64 64 80 80 96 96 256

Device Options: HC2Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s

HE3Ye s Ye s Ye s Ye s

ZE4Yes Yes Yes Yes Yes Yes

Number of PLLs 001111222

Hardened 

Functions:

I2C 222222222

SPI 111111111

Timer/Coun-

ter 111111111

Packages IO

25-ball WLCSP5

(2.5 mm x 2.5 mm, 0.4 mm) 18

32 QFN6

(5 mm x 5 mm, 0.5 mm) 21 21

48 QFN8, 9

(7 mm x 7 mm, 0.5 mm) 40 40

49-ball WLCSP5

(3.2 mm x 3.2 mm, 0.4 mm) 38

64-ball ucBGA

(4 mm x 4 mm, 0.4 mm) 44

84 QFN7

(7 mm x 7 mm, 0.5 mm) 68

100-pin TQFP

(14 mm x 14 mm) 55 78 79 79

132-ball csBGA

(8 mm x 8 mm, 0.5 mm) 55 79 104 104 104

144-pin TQFP

(20 mm x 20 mm) 107 107 111 114 114

184-ball csBGA7

(8 mm x 8 mm, 0.5 mm) 150

256-ball caBGA

(14 mm x 14 mm, 0.8 mm) 206 206 206

256-ball ftBGA

(17 mm x 17 mm, 1.0 mm) 206 206 206 206

332-ball caBGA

(17 mm x 17 mm, 0.8 mm) 274 278

484-ball ftBGA

(23 mm x 23 mm, 1.0 mm) 278 278 334

1. Ultra high I/O device.

2. High performance with regulator – VCC = 2.5 V, 3.3 V

3. High performance without regulator – VCC = 1.2 V

4. Low power without regulator – VCC = 1.2 V

5. WLCSP package only available for ZE devices.

6. 32 QFN package only available for HC and ZE devices.

7. 184 csBGA package only available for HE devices.

8. 48-pin QFN information is ‘Advanced’.

9. 48 QFN package only available for HC devices.

1-3

Introduction

MachXO2 Family Data Sheet

Introduction

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from

256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature

Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-

engineered source synchronous I/O support, advanced configuration support including dual-boot capability and

hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These fea-

tures allow these devices to be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has sev-

eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs

and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low

static power for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE)

devices. The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest.

Similarly, the high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest.

HC devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V.

ZE and HE devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply volt-

age all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space

saving 2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration

within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key

parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range

of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-

bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-

down and bus-keeper features are controllable on a “per-pin” basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may

be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-

ilar state machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the

JTAG test access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using

external Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and

route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into

the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of

reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft

core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas-

ing their productivity.

www.latticesemi.com 2-1 DS1035 Architecture_02.3

March 2016 Data Sheet DS1035

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Architecture Overview

The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The

larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM

(EBRs). Figure 2-1 and Figure 2-2 show the block diagrams of the various family members.

Figure 2-1. Top View of the MachXO2-1200 Device

Figure 2-2. Top View of the MachXO2-4000 Device

sysMEM Embedded

Block RAM (EBR)

sysCLOCK PLL

PIOs Arranged into

sysIO Banks

Programmable Function Units

with Distributed RAM (PFUs)

Embedded Function

Block (EFB)

User Flash Memory

(UFM)

On-chip Configuration

Flash Memory

Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a lower LUT count and no PLL or EBR blocks.

MachXO2-640 has no PLL, a lower LUT count and two EBR blocks. MachXO2-640U has a lower LUT count, one PLL and seven EBR blocks.

sysMEM Embedded

Block RAM (EBR)

Programmable Function Units

with Distributed RAM (PFUs)

On-chip Configuration

Flash Memory

sysCLOCK PLL

PIOs Arranged into

sysIO Banks

Embedded

Function Block(EFB)

User Flash

Memory (UFM)

Note: MachXO2-1200U, MachXO2-2000/U and MachXO2-7000 are similar to MachXO2-4000. MachXO2-1200U and MachXO2-2000 have a lower LUT count,

one PLL, and eight EBR blocks. MachXO2-2000U has a lower LUT count, two PLLs, and 10 EBR blocks. MachXO2-7000 has a higher LUT count, two PLLs,

and 26 EBR blocks.

MachXO2 Family Data Sheet

Architecture

2-2

Architecture

MachXO2 Family Data Sheet

The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimen-

sional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are

located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic,

RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports

operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing

channel resources. The place and route software tool automatically allocates these routing resources.

In the MachXO2 family, the number of sysIO banks varies by device. There are different types of I/O buffers on the

different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast

memory blocks; these blocks are found in MachXO2-640/U and larger devices. These blocks can be configured as

RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT

usage.

The MachXO2 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is

configured, the device enters into user mode with these registers SET/RESET according to the configuration set-

ting, allowing device entering to a known state for predictable system function.

The MachXO2 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on MachXO2-

640U, MachXO2-1200/U and larger devices. These blocks are located at the ends of the on-chip Flash block. The

PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase rela-

tionships of the clocks.

MachXO2 devices provide commonly used hardened functions such as SPI controller, I2C controller and timer/

counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These hardened

functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also

be accessed through the SPI, I2C and JTAG ports.

Every device in the family has a JTAG port that supports programming and configuration of the device as well as

access to the user logic. The MachXO2 devices are available for operation from 3.3 V, 2.5 V and 1.2 V power sup-

plies, providing easy integration into the overall system.

PFU Blocks

The core of the MachXO2 device consists of PFU blocks, which can be programmed to perform logic, arithmetic,

distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0

to 3 as shown in Figure 2-3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs

associated with each PFU block.

2-3

Architecture

MachXO2 Family Data Sheet

Figure 2-3. PFU Block Diagram

Slices

Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1

shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU

contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8.

The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-

select and wider RAM/ROM functions.

Table 2-1. Resources and Modes Available per Slice

Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-

tive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the

carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the

adjacent PFU). Table 2-2 lists the signals associated with Slices 0-3.

Slice

PFU Block

Resources Modes

Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM

Slice 1 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM

Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM

Slice 3 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 0

LUT4 &

CARRY

LUT4 &

CARRY

FF/

Latch

FCIN FCO

D FF/

Latch

Slice 1

LUT4 &

CARRY

LUT4 &

CARRY

Slice 2

LUT4 &

CARRY

LUT4 &

CARRY

From

Routin g

Slice 3

LUT4 &

CARRY

LUT4 &

CARRY

FF/

Latch

D FF/

Latch

D FF/

Latch

D FF/

Latch

D FF/

Latch

D FF/

Latch

2-4

Architecture

MachXO2 Family Data Sheet

Figure 2-4. Slice Diagram

Table 2-2. Slice Signal Descriptions

Function Type Signal Names Description

Input Data signal A0, B0, C0, D0 Inputs to LUT4

Input Data signal A1, B1, C1, D1 Inputs to LUT4

Input Multi-purpose M0/M1 Multi-purpose input

Input Control signal CE Clock enable

Input Control signal LSR Local set/reset

Input Control signal CLK System clock

Input Inter-PFU signal FCIN Fast carry in1

Output Data signals F0, F1 LUT4 output register bypass signals

Output Data signals Q0, Q1 Register outputs

Output Data signals OFX0 Output of a LUT5 MUX

Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice

Output Inter-PFU signal FCO Fast carry out1

1. See Figure 2-3 for connection details.

2. Requires two PFUs.

LUT4 &

Carry

Slice

Flip-flop/

Latch

OFX0

LUT4 &

Carry

OFX1

F/SUM

F/SUM D

FCI From

Different

Slice/PFU

Memory &

Control

Signals

FCO To Different Slice/PFU

LUT5

Mux

From

Routing

For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:

• WCK is CLK

• WRE is from LSR

• DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2

• WAD [A:D] is a 4-bit address from slice 2 LUT input

CLK

LSR

FXB

FXA

Flip-flop/

Latch

2-5

Architecture

MachXO2 Family Data Sheet

Modes of Operation

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.

Logic Mode

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16

possible input combinations. Any four input logic functions can be generated by programming this lookup table.

Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as

LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four

slices.

Ripple Mode

Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following func-

tions can be implemented by each slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Up/down counter with asynchronous clear

• Up/down counter with preload (sync)

• Ripple mode multiplier building block

• Multiplier support

• Comparator functions of A and B inputs

— A greater-than-or-equal-to B

— A not-equal-to B

— A less-than-or-equal-to B

Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-

figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-

ated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices.

RAM Mode

In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0

and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals.

MachXO2 devices support distributed memory initialization.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of slices required to implement different distributed RAM primitives. For more information about

using RAM in MachXO2 devices, please see TN1201, Memory Usage Guide for MachXO2 Devices.

Table 2-3. Number of Slices Required For Implementing Distributed RAM

SPR 16x4 PDPR 16x4

Number of slices 3 3

Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

2-6

Architecture

MachXO2 Family Data Sheet

ROM Mode

ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through

the programming interface during PFU configuration.

For more information on the RAM and ROM modes, please refer to TN1201, Memory Usage Guide for MachXO2

Devices.

Routing

There are many resources provided in the MachXO2 devices to route signals individually or as buses with related

control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-

ments.

The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2

(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec-

tions in the horizontal and vertical directions.

The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and

route tool is completely automatic, although an interactive routing editor is available to optimize the design.

Clock/Control Distribution Network

Each MachXO2 device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins

each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These

eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to

drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly.

The MachXO2 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high

fanout nets. MachXO2-640U, MachXO2-1200/U and higher density devices have two edge clocks each on the top

and bottom edges. Lower density devices have no edge clocks. Edge clocks are used to clock I/O registers and

have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge

outputs and CIB sources.

The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks

for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals,

MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such

as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the

global clock network for internally-generated global clocks and control signals.

The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteris-

tics table.

The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The

available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2-

640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes The available clock sources

include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs.

2-7

Architecture

MachXO2 Family Data Sheet

Figure 2-5. Primary Clocks for MachXO2 Devices

Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight

inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven

come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO2 Exter-

nal Switching Characteristics table.

811

Clock Pads

Routing

Primary Clock 0

Primary Clock 1

Primary Clock 2

Primary Clock 3

Primary Clock 4

Primary Clock 5

Primary Clock 6

Edge Clock

Divider

Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices.

Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL

and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes.

Primary Clock 7

Dynamic

Clock

Enable

Dynamic

Clock

Enable

Dynamic

Clock

Enable

Dynamic

Clock

Enable

Dynamic

Clock

Enable

27:1

Up to 8

PLL Outputs

Dynamic

Clock

Enable

Dynamic

Clock

Enable

Dynamic

Clock

Enable

Clock

Switch

Clock

Switch

2-8

Architecture

MachXO2 Family Data Sheet

Figure 2-6. Secondary High Fanout Nets for MachXO2 Devices

sysCLOCK Phase Locked Loops (PLLs)

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The MachXO2-640U, MachXO2-1200/U

and larger devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its

source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which

can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference fre-

quency and thus synthesize a higher frequency clock output.

The MachXO2 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency syn-

thesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more

information about using the PLL with Fractional-N synthesis, please see TN1199, MachXO2 sysCLOCK PLL

Design and Usage Guide.

Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The

output dividers can have a value from 1 to 128. The output dividers may also be cascaded together to generate low

frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO2 clock

distribution network directly or general purpose routing resources can be used.

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is

detected. A block diagram of the PLL is shown in Figure 2-7.

The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2,

and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock.

8:1

Clock Pads Routing

Secondary High

Fanout Net 0

Secondary High

Fanout Net 1

Secondary High

Fanout Net 2

Secondary High

Fanout Net 3

Secondary High

Fanout Net 4

Secondary High

Fanout Net 5

Secondary High

Fanout Net 6

Secondary High

Fanout Net 7

2-9

Architecture

MachXO2 Family Data Sheet

This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode,

the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the

tLOCK parameter has been satisfied.

The MachXO2 also has a feature that allows the user to select between two different reference clock sources

dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are

shown in the sysCLOCK PLL Timing table.

The MachXO2 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be

dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the

design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are

updated through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been sat-

isfied. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table.

For more details on the PLL and the WISHBONE interface, see TN1199, MachXO2 sysCLOCK PLL Design and

Usage Guide.

Figure 2-7. PLL Diagram

Table 2-4 provides signal descriptions of the PLL block.

Table 2-4. PLL Signal Descriptions

Port Name I/O Description

CLKI I Input clock to PLL

CLKFB I Feedback clock

PHASESEL[1:0] I Select which output is affected by Dynamic Phase adjustment ports

PHASEDIR I Dynamic Phase adjustment direction

PHASESTEP I Dynamic Phase step – toggle shifts VCO phase adjust by one step.

CLKOP, CLKOS, CLKOS2, CLKOS3

REFCLK

Internal Feedback

FBKSEL

CLKOP

CLKOS

CLKOS2

CLKOS3

REFCLK

Divider

M (1 - 40)

LOCK

ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3

RST, RESETM, RESETC, RESETD

CLKFB

CLKI

Dynamic

Phase

Adjust

PHASESEL[1:0]

PHASEDIR

PHASESTEP

FBKCLK

Divider

N (1 - 40)

Fractional-N

Synthesizer

Phase detector,

VCO, and

loop filter.

CLKOS3

Divider

(1 - 128)

CLKOS2

Divider

(1 - 128)

Phase

Adjust

Phase

Adjust

Phase

Adjust/

Edge Trim

CLKOS

Divider

(1 - 128)

CLKOP

Divider

(1 - 128)

Lock

Detect

ClkEn

Synch

ClkEn

Synch

ClkEn

Synch

ClkEn

Synch

PLLDATO[7:0] , PLLACK

PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]

D0 D1

Mux

DPHSRC

Phase

Adjust/

Edge Trim

STDBY

Mux

2-10

Architecture

MachXO2 Family Data Sheet

sysMEM Embedded Block RAM Memory

The MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a

9-kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes

including data buffering, PROM for the soft processor and FIFO.

sysMEM Memory Block

The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be

used in a variety of depths and widths as shown in Table 2-5.

CLKOP O Primary PLL output clock (with phase shift adjustment)

CLKOS O Secondary PLL output clock (with phase shift adjust)

CLKOS2 O Secondary PLL output clock2 (with phase shift adjust)

CLKOS3 O Secondary PLL output clock3 (with phase shift adjust)

LOCK O PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feed-

back signals.

DPHSRC O Dynamic Phase source – ports or WISHBONE is active

STDBY I Standby signal to power down the PLL

RST I PLL reset without resetting the M-divider. Active high reset.

RESETM I PLL reset - includes resetting the M-divider. Active high reset.

RESETC I Reset for CLKOS2 output divider only. Active high reset.

RESETD I Reset for CLKOS3 output divider only. Active high reset.

ENCLKOP I Enable PLL output CLKOP

ENCLKOS I Enable PLL output CLKOS when port is active

ENCLKOS2 I Enable PLL output CLKOS2 when port is active

ENCLKOS3 I Enable PLL output CLKOS3 when port is active

PLLCLK I PLL data bus clock input signal

PLLRST I PLL data bus reset. This resets only the data bus not any register values.

PLLSTB I PLL data bus strobe signal

PLLWE I PLL data bus write enable signal

PLLADDR [4:0] I PLL data bus address

PLLDATI [7:0] I PLL data bus data input

PLLDATO [7:0] O PLL data bus data output

PLLACK O PLL data bus acknowledge signal

Table 2-4. PLL Signal Descriptions (Continued)

Port Name I/O Description

2-11

Architecture

MachXO2 Family Data Sheet

Table 2-5. sysMEM Block Configurations

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be

loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero

pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO2 devices have been designed such

that multiple EBRs share the same initialization memory space if they are initialized to the same pattern.

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block

can also be utilized as a ROM.

Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on specific design inputs.

Single, Dual, Pseudo-Dual Port and FIFO Modes

Figure 2-8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM

modes, the input data and addresses for the ports are registered at the input of the memory array. The output data

of the memory is optionally registered at the memory array output.

Memory Mode Configurations

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

True Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

Pseudo Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

FIFO

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

2-12

Architecture

MachXO2 Family Data Sheet

Figure 2-8. sysMEM Memory Primitives

Table 2-6. EBR Signal Descriptions

Port Name Description Active State

CLK Clock Rising Clock Edge

CE Clock Enable Active High

OCE1Output Clock Enable Active High

RST Reset Active High

BE1Byte Enable Active High

WE Write Enable Active High

AD Address Bus —

DI Data In —

DO Data Out —

CS Chip Select Active High

AFF FIFO RAM Almost Full Flag —

FF FIFO RAM Full Flag —

AEF FIFO RAM Almost Empty Flag —

EF FIFO RAM Empty Flag —

RPRST FIFO RAM Read Pointer Reset —

1. Optional signals.

2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.

3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec-

tively.

4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).

5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the

read port chip select, ORE is the output read enable.

DI[17:0]

CLKW

FIFO RAM

DO[17:0]

RST

FULLI

AFF

AEF

CLKR

CSR[1:0]

ORE

RPRST

CSW[1:0] EMPTYI

ROM

DO[17:0]

AD[12:0]

CLK

RST

CS[2:0]

OCE

EBR EBR

AD[12:0]

DI[8:0]

DO[8:0]

CLK

RST

CS[2:0]

OCE

Single-Port RAM

ADA[12:0]

DIA[8:0]

CLKA

CEA

RSTA

WEA

CSA[2:0]

DOA[8:0]

OCEA

ADB[12:0]

DI[8:0]

CLKB

CEB

RSTB

WEB

CSB[2:0]

DOB[8:0]

OCEB

True Dual Port RAM

ADW[8:0]

DI[17:0]

CLKW

CEW

RST

CSW[2:0]

ADR[12:0]

CLKR

CER

DO[17:0]

CSR[2:0]

OCER

BE[1:0]

Pseudo Dual Port RAM

EBREBREBR

2-13

Architecture

MachXO2 Family Data Sheet

The EBR memory supports three forms of write behavior for single or dual port operation:

1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for

all data widths.

3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.

FIFO Configuration

The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,

RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The

Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.

Table 2-7 shows the range of programming values for these flags.

Table 2-7. Programmable FIFO Flag Ranges

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset

that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset

state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is

in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from

the FIFO.

Memory Core Reset

The memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-

chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with

port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and

associated resets for both ports are as shown in Figure 2-9.

Flag Name Programming Range

Full (FF) 1 to max (up to 2N-1)

Almost Full (AF) 1 to Full-1

Almost Empty (AE) 1 to Full-1

Empty (EF) 0

N = Address bit width.

2-14

Architecture

MachXO2 Family Data Sheet

Figure 2-9. Memory Core Reset

For further information on the sysMEM EBR block, please refer to TN1201, Memory Usage Guide for MachXO2

Devices.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before

the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-10. The GSR input

to the EBR is always asynchronous.

Figure 2-10. EBR Asynchronous Reset (Including GSR) Timing Diagram

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during

device wake up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-

nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-10. The reset timing

rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST

and RPReset are always asynchronous EBR inputs. For more details refer to TN1201, Memory Usage Guide for

MachXO2 Devices.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

SET

Output Data

Latches

Memory Core

Port A[18:0]

SET

Port B[18:0]

RSTB

GSRN

Programmable Disable

RSTA

Reset

Clock

Enable

2-15

Architecture

MachXO2 Family Data Sheet

Programmable I/O Cells (PIC)

The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respec-

tive sysIO buffers and pads. On the MachXO2 devices, the PIO cells are assembled into groups of four PIO cells

called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.

On all the MachXO2 devices, two adjacent PIOs can be combined to provide a complementary output driver pair.

The MachXO2-640U, MachXO2-1200/U and higher density devices contain enhanced I/O capability. All PIO pairs

on these larger devices can implement differential receivers. Half of the PIO pairs on the top edge of these devices

can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these higher density devices

have on-chip differential termination and also provide PCI support.

2-16

Architecture

MachXO2 Family Data Sheet

Figure 2-11. Group of Four Programmable I/O Cells

1 PIC

PIO A

Output

& Tristate

Input Register

Block

PIO B

Output

& Tristate

Input Register

Block

PIO C

Output

& Tristate

Input Register

Block

Notes:

1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices.

2. Output gearbox is available only in PIC on the top edge of MachXO2-640U, MachXO2-1200/U and larger devices.

PIO D

Output

& Tristate

Input Register

Block

Core Logic/

Routing

Input

Gearbox

Output

Gearbox

2-17

Architecture

MachXO2 Family Data Sheet

PIO

The PIO contains three blocks: an input register block, output register block and tri-state register block. These

blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.

Table 2-8. PIO Signal List

Input Register Block

The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condi-

tion high-speed interface signals before they are passed to the device core. In addition to this functionality, the input

Figure 2-12 shows the input register block for the PIOs located on the left, top and bottom edges. Figure 2-13

shows the input register block for the PIOs on the right edge.

Left, Top, Bottom Edges

Input signals are fed from the sysIO buffer to the input register block (as signal D). If desired, the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK).

If an input delay is desired, users can select a fixed delay. I/Os on the bottom edge also have a dynamic delay,

DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input

block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK)

by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to

sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams.

Pin Name I/O Type Description

CE Input Clock Enable

D Input Pin input from sysIO buffer.

INDD Output Register bypassed input.

INCK Output Clock input

Q0 Output DDR positive edge input

Q1 Output Registered input/DDR negative edge input

D0 Input Output signal from the core (SDR and DDR)

D1 Input Output signal from the core (DDR)

TD Input Tri-state signal from the core

Q Output Data output signals to sysIO Buffer

TQ Output Tri-state output signals to sysIO Buffer

DQSR901 Input DQS shift 90-degree read clock

DQSW901 Input DQS shift 90-degree write clock

DDRCLKPOL1 Input DDR input register polarity control signal from DQS

SCLK Input System clock for input and output/tri-state blocks.

RST Input Local set reset signal

1. Available in PIO on right edge only.

2-18

Architecture

MachXO2 Family Data Sheet

Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges)

Right Edge

The input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In

addition to the modes described above, the input register block on the right edge also supports DDR memory

mode.

In DDR memory mode, two registers are used to sample the data on the positive and negative edges of the modi-

fied DQS (DQSR90) in the DDR Memory mode creating two data streams. Before entering the core, these two data

streams are synchronized to the system clock to generate two data streams.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred to the system clock domain from the DQS domain. The DQSR90 and

DDRCLKPOL signals are generated in the DQS read-write block.

Figure 2-13. MachXO2 Input Register Block Diagram (PIO on Right Edge)

SCLK

INCK

INDD

D Q

Programmable

Delay Cell D/L Q

D Q

INDD

DQSR90

SCLK

DDRCLKPOL

Programmable

Delay Cell D/L Q

INCK

D Q

D Q D Q

D Q

2-19

Architecture

MachXO2 Family Data Sheet

Output Register Block

The output register block registers signals from the core of the device before they are passed to the sysIO buffers.

Left, Top, Bottom Edges

In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type

In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling

edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to

switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-14 shows the output register block on the left, top and bottom edges.

Figure 2-14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)

Right Edge

The output register block on the right edge is a superset of the output register on left, top and bottom edges of the

device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right

edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the out-

put register block on other edges.

In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling

edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used

to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-15 shows the output register block on the right edge.

Output path

D/L Q

Tri-state path

D1 D Q D Q Q1

D/L Q

SCLK

2-20

Architecture

MachXO2 Family Data Sheet

Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges)

Tri-state Register Block

The tri-state register block registers tri-state control signals from the core of the device before they are passed to

the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that

then feeds the output.

The tri-state register blocks on the right edge contain an additional register for DDR memory operation. In DDR

memory mode, the register TS input is fed into another register that is clocked using the DQSW90 signal. The out-

put of this register is used as a tri-state control.

Input Gearbox

Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed

as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2-9 shows the

gearbox signals.

Table 2-9. Input Gearbox Signal List

Name I/O Type Description

D Input High-speed data input after programmable delay in PIO A

input register block

ALIGNWD Input Data alignment signal from device core

SCLK Input Slow-speed system clock

ECLK[1:0] Input High-speed edge clock

RST Input Reset

Q[7:0] Output Low-speed data to device core:

Video RX(1:7): Q[6:0]

GDDRX4(1:8): Q[7:0]

GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7

GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3

D Q

D1 D Q Q1

D/L QQ0

DQSW90

SCLK

D Q TQ

D/L Q

Output Register Block

Tristate Register Block