WM8726CGED/RV - WOLFSON MICROELECTRONICS

w WM8726

24-bit 192kHz Stereo DAC

W OLFSON MI CROELECTRONICS plc

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Production Dat a, May 2008, Rev 4.6

DESCRIPTION

The WM8726 is a high performance stereo DAC designed

for audio appl ications such as DVD, hom e theatre s ystems ,

and digital TV. The WM8726 supports data input word

lengths f rom 16 to 24-bits and sampl ing rates up to 192kHz.

The WM8726 consists of a serial interface port, digital

interpolation filters, multi-bit sigma delta modulators and

stereo DAC.

The W M8726 has a hardware control interface for select ion

of audio data interface format, mute and de-emphasis. The

WM8726 supports I2S, right Justified or DSP interfaces.

The WM8726 is an ideal device to interface to AC-3™,

DTS™, and MPEG audio decoders for surround sound

applicat ions, or f or use i n DVD players , inc luding supporting

the implementation of 2 channels at 192kHz for high-end

DVD-Audio applications.

The WM8726 is available in a 14-lead SOIC package.

FEATURES

• Stereo DAC

• Audio Performance

- 97 dB SNR (‘A’ weighted @ 48kHz)

- -89 dB THD

• DAC Sampling Frequency: 8kHz – 192kHz

• Pin Selectable Audio Data Interface Format

- I

2S, 16-bit Right Jus t ified or DSP

• 3.0V - 5.5V Supply Operation

• 14-lead SOIC Package

• Pin Compatible with WM8725

APPLICATIONS

• DVD Players

• Home Theatre Systems

• Digital TV

• Digital Set Top Boxes

• Automotive

BLOCK DIAGRAM

WM8726

BCKIN AUDIO

INTERFACE

MUTE

CONTROL

INTERFACE

VOUTL

VOUTR

LRCIN

DIN MUTE

DIGITAL

FILTERS

MCLK

DEEMPHMUTEFORMAT

CAP

RIGHT

DAC

LEFT

DAC

GNDVDD

SIGMA

DELTA

MODULATOR

SIGMA

DELTA

MODULATOR

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TABLE OF CONTENTS

DESCRIPTION ............................................................................................................1

FEATURES..................................................................................................................1

APPLICATIONS ..........................................................................................................1

BLOCK DIAGRAM......................................................................................................1

TABLE OF CONTENTS ..............................................................................................2

PIN CONFIGURATION.............. .... .... .... .... .... .... .... .... ............ .... .... .... .... .... .... .... ..........3

ORDERING INFORMATION .......... ........... .... .... .... .... .... .... .... .... ............ .... .... ... .... .... ...3

PIN DESCRIPTION ........... ............ .... .... .... .... .... .... .... .... ............ .... .... .... .... .... .... ... .... ...4

ABSOLUTE MAXIMUM RATINGS..............................................................................5

DC ELECTRICAL CHARACTERISTICS.....................................................................6

ELECTRICAL CHARACTERISTICS ...........................................................................6

TERMINOLOGY................................................................................................................. 7

MASTER CLOCK TIMING...........................................................................................8

DIGITAL AUDIO INTERFACE.....................................................................................8

POWER ON RESET (POR).........................................................................................9

DEVICE DESCRIPTION............................................................................................11

GENERAL INTRODUCTION.............................................................................................11

DAC CIRCUIT DESCRIPTION............. ... ... ... .... ... ... ....... ... ... ... .... ... ... .... ...... ... .... ... ... ... .... ..11

CLOCKING SCHEMES .................................................. ................................ ...................12

DIGITAL AUDIO INTERFACE.... ................................ ................................. ......................12

AUDIO DATA SAMPLING RATES........... ..........................................................................14

HARDWARE CONTROL MODES............................................................... ......................15

DIGITAL FILTER CHARACTERISTICS....................................................................17

DAC FILTER RESPONSES........ ... ... .... ... ...... .... ... ... ... .... ... ...... .... ... ... ... .... ... ...... .... ... ... .... ..17

DIGITAL DE-EMPHASIS CHARACTERISTICS.......... ................. ................................ ......18

APPLICATIONS INFORMATION..............................................................................19

RECOMMENDED EXTERNAL COMPONENTS................................................................19

RECOMMENDED EXTERNAL COMPONENTS VALUES................................. ................19

RECOMMENDED ANALOGUE LOW PASS FILTER ........................................................20

PCB LAYOUT RECOMMENDATIONS. ... ...... .... ... ... ... .... ... ...... .... ... ... .... ... ... ....... ... ... ... .... ..20

PACKAGE DIMENSIONS .........................................................................................21

IMPORTANT NOTICE...............................................................................................22

ADDRESS:........................................................................................................................22

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PIN CONFIGURATION

WM8726

VDD

VOUTL

MUTE

DEEMPH

MCLK

FORMAT

GND

VOUTR

CAP

BCKIN

LRCIN

DIN

ORDERING INFORMATION

DEVICE TEMPERATURE

RANGE PACKAGE MOISTURE

SENSITIVITY LEVEL PEAK SOLDERI NG

TEMPERATURE

WM8726GED/V -40 to +85oC 14-lead SOI C

(Pb-free) MSL2 260oC

W M8726G ED/ RV -40 to +85oC 14-lead SOI C

(Pb-free, tape and reel) MSL2 260oC

Notes:

1. Reel quantity = 3,000

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PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 LRCIN Digital input Sample rate clock input

2 DIN Digital input Serial audio data input

3 BCKIN Digital input Bit clock i nput

4 NC No connect No internal connection

5 CAP Analogue output Analogue internal reference

6 VOUTR Analogue output Right channel DAC output

7 GND Supply Negative supply

8 VDD Supply Positive supply

9 VOUTL Analogue output Left channel DAC output

10 MUTE Digital input Soft mute control, Internal pull down

High Impedance = Automute

High = Mute ON

Low = Mute OFF

11 NC No connect No internal connection

12 DEEMPH Digital input De-emphasis select, Internal pull up

High = de-emphasis ON

Low = de-emphasis OFF

13 FORMAT Digital input Data input format s el ect , Inter nal pull up

Low = 16-bit right justified or DSP ‘late’

High = 16-24-bit I2S or DSP ‘early’

14 MCLK Digital input Master clock input

Note:

1. Digital input pins have Schmitt trigger input buffers.

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ABSOLUTE MAXIMUM RATINGS

Absolut e Maxim um Rati ngs ar e s t ress rat ings only. P ermane nt da m age to the dev ic e m ay be c aus ed by c onti nuous ly oper ati ng at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD S ensitive Device. This device is manuf actured on a CMOS process . It is theref ore generically susc eptible

to damage fr om excessive st atic voltages . Proper ESD precautions must be taken during handling and storage

of this devic e.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity . Suppl ied in m ois t ure barrier bag.

MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Hum idi ty. Suppl i ed in m oist ure barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION MIN MAX

Supply volt age -0.3V +7V

Voltage range digi t al inputs GND -0.3V VDD +0.3V

Master Clock Frequenc y 50MHz

Operating temperature range , TA -40°C +85°C

Storage temperature aft er solder ing -65°C +150°C

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DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Supply range VDD 3.0 5.5 V

Ground GND 0 V

Supply current VDD = 5V 27 mA

Supply current VDD = 3.3V 23 mA

Power down current (note 4) VDD=3.3V 0.6 mA

ELECTRICAL CHARACTERISTICS

All MIN/MAX characterist ics are guaranteed over the recom m ended operat ing condi ti ons . Typic al c haracteristi c s are based on

measurements taken under the test conditions specified below.

Test Conditions

VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital Logic Levels (TTL Levels)

Input LOW level VIL 0.8 V

Input HIGH level VIH 2.0 V

Output LOW VOL IOL = 2mA GND + 0.3V V

Output HIGH VOH IOH = 2mA VD D - 0 .3V V

Analogue Reference Levels

Reference voltage (CAP) VDD/2 V

Potenti al divi der resi s t anc e RCAP V DD to CAP and CAP

to GND 33k Ω

DAC Output (Load = 10kΩ 50pF)

0dBFs Full scale output voltage A t DAC output s 1.1 x

VDD/5 V

rms

DAC Performance (+25˚C )

SNR (Note 1,2,3) A-weighted,

@ fs = 48kHz 90 97 dB

SNR (Note 1,2,3) A-weighted

@ fs = 96kHz 94 dB

SNR (Note 1,2,3) A-weighted

@ fs = 192kHz 94 dB

SNR (Note 1,2,3) A-weighted,

@ fs = 48kHz

VDD = 3.3V

93 dB

SNR (Note 1,2,3) A-weighted

@ fs = 96kHz

VDD = 3.3V

93 dB

SNR (Note 1,2,3) Non ‘A’ weighted @ fs

= 48kHz 95 dB

THD (Note 3) 1kHz, 0dBFs -89 dB

Dynamic Range (Note 2) 1kHz, THD+N @

-60dBFs 90 97 dB

DAC channel separati on 93 dB

Analogue Output Levels Load = 10kΩ, 0dBFS 1.1 VRMS

Output level Load = 10kΩ, 0dBFS,

(VDD = 3.3V) 0.72 VRMS

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Test Conditions

VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Gain mismatch

channel-to-channel ±1 %FSR

To midrail or a.c.

coupled 1 kΩ

Minimum resistance load

To midrail or a.c.

coupled

(VDD = 3.3V)

1 kΩ

Maximum capac i tanc e l oad 5V or 3.3V 100 pF

Output d.c. level VDD/2 V

Power On Reset (POR)

POR threshold 2.4 V

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted

over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a

filter will result i n higher THD+N and lower SNR and Dynamic Range readings than are found in the Elec t ric al

Characteris ti c s. T he low pass fil ter rem oves out of band noise; alt hough it is not audible it m ay aff ec t dynamic spec i fi c ati on

values.

3. CAP pin decoupled with 10uF and 0.1uF capaci tors (sm all er values m ay result in reduced performanc e) .

4. Power down occurs 1.5µs after MCLK is stopped.

TERMINOLOGY

1. Signal-to-noi s e rati o ( dB) - SN R i s a meas ure of the di ff erenc e in lev el between the full sc ale output and the out put with no

signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range ( dB) - DNR is a m eas ure of the diff erence bet ween the highest and lowest portions of a signal . Normally a

THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.

THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Stop band attenuat ion (dB) - Is the degree to which the frequency s pectr um is att enuated (out side audio band).

5. Channel Separati on (dB) - Als o known as Cross-Talk . This i s a measur e of the amount one channel is isol ated from the

other. Normally measured by sending a full scale signal down one channel and measuring the other.

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MASTER CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless other wise stat ed.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

System Clock Timing Information

MCLK Master clock pulse width high tMCLKH 8 ns

MCLK Master clock pulse width low tMCLKL 8 ns

MC LK M aster cl ock cycle tim e tMCLKY 20 ns

MCLK Duty cycle 40:60 60:40

Time from MCLK stoppi ng to power

down. 1.5 12 µs

DIGITAL AUDIO INTERFACE

BCKIN

LRCIN

BCH

BCL

BCY

DIN

LRSU

LRH

Figure 2 Digital Audio Data Timing

Test Conditions

VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless other wise stat ed.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Audio Data Input Timing Information

BCKIN cycle time tBCY 40 ns

BCKIN pulse width high tBCH 16 ns

BCKIN pulse width low tBCL 16 ns

LRCIN set-up time to

BCKIN rising edge tLRSU 8 ns

LRCIN hold time from

BCKIN rising edge tLRH 8 ns

DIN set-up time to BCKIN

rising edge tDS 8 ns

DIN hold time from BCK IN

rising edge tDH 8 ns

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POWER ON RESET (POR)

The W M8726 has an int ernal power-on-reset (POR) circ uit which is us ed to reset the digital logic

into a default st ate after power up. A block diagram of the res et cir cui t is s hown in Figure 3

Figure 3 Block Diagram of Power-On-Reset

The acti ve low reset s ignal NPOR will be ass erted low until VDD=2.4V , whi ch means VMID rises

to 1.2V. When this threshold has been reached, then the NPOR is released and the digital

interface has been reset. This is illustrated in the diagram shown in Figure 4.

Figur e 4 Generation of In tern al NPOR At Power-On-Reset

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Figure 5 illustrates the NPOR generation when the power is removed.

Figur e 5 Generation o f NPOR at Power- Off-Reset

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DEVICE DESCRIPTION

GENERAL INTRODUCTION

The W M8726 is a high performance DAC designed for digital consumer audio applications. The

range of features ma ke it ideal ly suited for use in DVD players, AV recei vers and other consumer

audio equipment.

The W M8726 is a com plete 2-c hannel stereo audio digital -to-analogue converter, inc luding digital

interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC

and output smoothing filters. It is fully compatible and an ideal partner for a range of industry

standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC design is

used, utilising a 128x oversampling rate, to optimise signal to noise performance and offer

increased clock jitter tolerance. (In ‘high-rate’ operation, the oversam pling ratio is 64x for system

clock s of 128fs or 192fs)

Control of internal func tionalit y of the device i s provided by hardware control (pin programm ed) .

Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between

clock rates being automatically controlled. Sample rates (fs) from less than 8kHz to 96kHz are

allowed, provided the appropriat e system cl ock is input. Support is als o provided for up to 192kHz

using a master clock of 128fs or 192fs.

The audio data interf ace supports 16-bit right jus tifi ed or 16-24-bit I2S (Phil ips left j us ti fi ed, one bi t

delayed) int erface f orm ats. A DSP interf ace is al so suppor ted, enhanc ing t he interface options for

the user.

A single 3.0-5.5V supply may be used, the output amplitude scaling with absolute supply level.

Low supply volt age operation and low current cons umpt ion c ombined with the low pin count sm all

package m ake the WM8726 attrac ti ve for many cons umer applications.

The device is packaged in a small 14-pi n SOIC.

DAC CIRCUIT DESCRIPTION

The WM8726 DAC is designed to allow playback of 24-bit PCM audio or similar data with high

resolution and low noise and distortion. Sample rates up to 192kHz may be used, with much lower

sam ple rat es ac ceptable provided that the ratio of sample rat e ( LRCIN) t o mas ter c l oc k (MCLK) is

maintained at one of the required rates.

The two DACs on the WM8726 are implemented using sigma-delta oversampled conversion

techniques . T hese requi re that t he PC M sampl es are digi tally fil tered and interpolated to generat e

a set of sam ples at a m uch higher rate than the up to 192kHz input rate. This sample stream is

then digitally modulated to generate a digital pulse stream that is then converted to analogue

signals in a s witched c apac i tor DA C. The advantage of this tec hnique is that t he DAC is linearised

using noise shaping techniques, allowing the 24-bit resolution to be met using non-critical

analogue com ponents. A further advantage is that the high s ampl e rate at the DAC output means

that smoot hing filt ers on the output of the DAC need only have fairly crude charact eristi cs in order

to rem ove the c haract eris ti c steps, or i m ages on the output of the DAC. To ensure that generati on

of tones characteristic to sigma-delta convertors is not a problem, dithering is used in the digital

modulator along with a higher order modulat or. The multi -bit s wit ched c ap ac it or tec hnique us ed i n

the DAC reduces sensitiv ity to cl ock jitt er, and dramat ically reduces out of band nois e compared

to switched c urrent or single bit techniques us ed in other im pl em ent ati ons .

The voltage on the CAP pin is used as the ref erence for the DACs. Therefore the amplit ude of the

signals at the DAC outputs will scal e with the ampli tude of the voltage at the CAP pin. An external

reference c ould be used t o drive int o the CA P pi n if desired, with a value typically of about m idrail

ideal for optimum perf ormance.

The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers

will s ource load cur rents of several mA and si nk current up t o 1.5m A allowing s ignificant loads t o

be driven. The output source is active and the sink is Class A, i.e. fixed value, so greater loads

might be driven if an external ‘pull-down’ resis to r is c onnected at the output.

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Typically an external low pass filter circuit will be used to remove residual out of band noise

characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8726

produces far les s out of band noise than si ngle bit traditi onal sigm a delta DACs, and s o in many

applicat i ons this fil ter m ay be removed, or replaced with a sim pl e RC pole.

CLOCKING SCHEMES

In a typic al di git al audio syst em there is onl y one c ent ral c l oc k s ourc e produci ng a reference clock

to which all audio data processing is synchronised. This clock is often referred to as the audio

syst em’s Mast er Clock . T he external master c lock c an be applied directl y through the MCLK input

pin with no configuration necessary for sample rate selection.

Note that on the WM8726, MCLK is used to derive clocks for the DAC path. The DAC path

consis ts of DAC sam pling cl ock, DAC di gital f ilter cl ock and DAC digital audio interf ace tim ing. In

a system where there are a number of possible sources for the reference clock it is recommended

that the clock source with the lowest jitter be used to optimise the performance of the DAC.

The device can be powered down by stopping MCLK. In this state the power consumption is

subst anti al ly reduced.

DIGITAL AUDIO INTERFACE

Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface

forma ts are support ed:

• Right Justified mode

• I

2S mode

• DSP mode

All formats send the MSB first. The data format is selected with the FORMAT pin. When

FORMAT is LOW, right justified data format is selected and word lengths up to 16-bits may be

used. W hen the F ORMAT pin is HIGH, I2S f ormat is selec ted and word lengt h of any value up to

24-bits may be us ed. (I f a word lengt h shorter than 24- bit s i s us ed, the unus ed bits will be p added

with zeros). I f LRCIN is 4 BCKINs or l ess duration, the DSP com patible format is s elected. Early

and Late clock form at s are support ed, s elected by the state of the FORMAT pin.

‘Pac ked’ mode (i.e. only 32 or 48 c l oc ks per LRCIN peri od) operation is also supported in both I2S

(16-24 bits ) and right justi fied form ats, (16 bit). If a ‘pack ed’ form at of 16-bit word length is applied

(16 BCKINS per LRCIN half period), the device auto-detects this mode and switches to 16-bit

data length.

I2S MODE

The WM8726 supports word lengths of 16-24 bits in I2S m ode.

In I2S mode, the digital audio interface receives data on the DIN input. Audio Data is time

mult iplexed with LRCIN indicat ing whether the left or right channel is present. LRCIN is also us ed

as a timing reference to indicate the beginning or end of the data words.

In I2S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word

length. LRCIN must be high f or a minimum of word length BCKINs and low for a minimum of word

length B CKI Ns. A ny m ar k to spac e ratio on LRCIN is ac ceptable provided the above requirement s

are met. In I2S m ode , t he MS B i s s ampled on t he s econd risi ng edge of B CKI N foll owing a LRCIN

transi ti on. LRCIN is low during the left sam pl es and high during the right s am pl es.

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LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

n321 n-2 n-1

LSB

MSB

n321 n-2 n-1

LSB

MSB

1 BCKIN

1 BCKI N

Figure 6 I2S Mode Timing Diagram

RIGHT JUSTIFIED MODE

The WM8726 supports word lengths of 16-bits i n right justi fi ed m ode.

In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is

tim e mult iplexed with LRCIN indi cating whether the left or right channel is present . LRCIN is also

used as a timi ng referenc e to indi c ate the beginn ing or end of the data words.

In right jus tifi ed m ode, the m inim um number of BCKI Ns per LRCI N period is 2 t im es t he sel ect ed

word length. LRCI N m ust be hi gh f or a mi ni m um of word length BCKINs and low for a minim um of

word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above

requirements are met.

In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN

transi ti on. LRCIN is high during the left s amples and low during the right sam pl es.

LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

321 14 15

LSBMSB

321 14 15

LSBMSB

Figure 7 Right Justified Mode Timing Diagram

DSP MODE

A DSP compatible, time division multiplexed format is also supported by the WM8726. This

format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of

predetermi ned word length. (16-bits). The ‘synch’ pulse replac es the norm al durati on LRCIN, and

DSP mode is auto-detected by the shorter than normal duration of the LRCIN. If LRCIN is of 4

BCKIN or less duration, the DSP compatible format is selected. Mode A and Mode B clock

forma ts are support ed, s elected by the state of the FORMAT pin.

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Figure 8 DSP Mode A Timing

Figure 9 DSP Mode B Timing

AUDIO DATA SAMPLING RATES

The m ast er clock for W M8726 supp orts audi o sam pli ng rates from 128fs to 768fs , where fs is the

audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The

mas ter cloc k is us ed to operate the digi ta l fi lt ers and the nois e s haping ci rc ui ts.

The WM8726 has a master clock detection circuit that automatically determines the relation

between the m ast er cloc k f requency and t he sam pli ng rate (to within +/- 8 mast er clock s). I f there

is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The

master clock should be synchronised with LRCIN, although the WM8726 is tolerant of phase

differenc es or ji tt er on this clock .

MASTER CLOCK FREQUENCY (MHZ) (MCLK)

SAMPLING

RATE

(LRCIN) 128fs 192fs 256fs 384fs 512fs 768fs

32kHz 4.096 6.144 8.192 12.288 16.384 24.576

44.1kHz 5.6448 8.467 11.2896 16.9344 22.5792 33.8688

48kHz 6.144 9.216 12.288 18.432 24.576 36.864

96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable

192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable

Table 1 Master Clock Frequenci es Versus S ampli n g Rate

LRCIN

BCKIN

DIN

Input Word Length (16 bits)

1/fs

LEF T CHANNEL

2 1 15

LSBMSB 16

21 15

RIGHT CHANNEL NO VAL ID DATA

Max 4 BC K I N's

LRCIN

BCKIN

DIN

Input Word Length (16 bits)

1/fs

LEF T CHANNEL

2 1 15

LSBMSB 16

21 15

RIGHT CHANNEL NO VALID DATA

1 BCKI N 1 BCKIN

max 4 BCKI N's

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HARDWARE CONTROL MO DE S

The WM8726 is hardware programmable providing the user with options to select input audio data

forma t, de-em phas i s and mut e.

MUTE AND AUTO M U TE OPER ATION

Pin 10 (MUTE) controls sel ect ion of MUTE direct ly, and can be used to enable and disabl e the

automute function, or as an output of the automuted signal.

MUTEB PIN DESCRIPTION

0 Normal Operation, MUTE off

1 Mute DAC channels

Floating Enable IZD, MUTE becomes an output t o indic ate when IZD occurs.

Table 2 Mute and Automute Control

Figure 10 Application and Release of MUTE

The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high

causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking

MUTE low again allows data into the filter. Refer to Figure 10.

The Infinite Zero Detect (IZD) function detects a series of zero value audio samples of 1024

samples long being applied to both channels. After such an event, a latch is set whose output

(AUTOMUTED) is c onnected through a 10kohm resi s tor to the MUTE pin. Thus if the MUTE pin is

not being driven, the automute function will assert mute.

If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a bi-

direct ional source, then both MUTE and automut e functions are available. I f MUTE is not driven,

AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive

external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-zero

input.

-2.5

-2

-1.5

-1

-0.5

0.5

1.5

0 0.001 0.002 0.003 0.004 0.005 0.006

Time(s)

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A diagram showing how the various Mute modes interact is shown below in Figure 11.

AUTOMUTED

(Internal Signal)

10k

Ω

SOFTMUTE

(Internal Signal)

MUTE

Figure 11 Selection Logic for MUTE Modes

INPUT AUDIO FORMAT SELECTION

FORMAT (pin 13) controls the data input format.

FORMAT INPUT DATA MODE

0 16 bit right justi fi ed

1 16–24 bit I2S

Table 3 Input Audio Format Selection

Notes:

1. In 16-24 bit I2S m ode, any dat a from 16-24 bits or more is supported provided that LRCIN is

high for a minimum of data width BCKINs and low for a minimum of data width BCKINs,

unless Note 2. For data widths greater than 24 bits, the LSB’s will be truncated and the

most significant 24 bits will be used by the internal processing.

2. If exactly 16 BCKIN cy cles occur i n both the low and high period of LRCIN the WM8726 will

assum e the data i s 16-bit and accept the data ac c ordingl y.

INP UT DSP FOR MAT SEL ECTION

FORMAT 50% LRCIN DUTY CYCLE LRCIN of 4 BCKIN or Less Duration

16 bit

(MSB-first, right justified) DSP format – ‘late’ mode

1 I2S format up to 24 bit

(Philips s erial data prot oc ol ) DSP format – ‘early’ mode

Table 4 DSP Interface Formats

DE-EMPHASIS CONTROL

DEM (pin 12) is an input control for selection of de-emphasis filtering to be applied.

DEEMPH DE-EMPHASIS

0 Off

1 On

Table 5 De-emphasis Control

DAC OUTPUT PHASE

In the DAC to analog output , the analog output data VOUTL/R, is a phase invert ed representat ion of the

digital i nput s ignal .

WM8726 Production Data

w PD Rev 4.6 May 2008

DIGITAL FILTER CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Pass band Edge -3dB 0.487fs

Pass band Ripple f < 0.444fs ±0.05 dB

Stopband Attenuation f > 0.555fs -60 dB

Table 6 Digital Filter Characteri stics

DAC FILTER RESPONSES

-120

-100

-80

-60

-40

-20

0 0.5 1 1.5 2 2.5 3

Response (dB)

Frequency (Fs)

Figure 12 DAC Digital Filter Frequency Response

-44.1, 48 and 96kHz

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Response (dB)

Frequency (Fs)

Figure 13 DAC Digital Filter Ripple

-44.1, 48 and 96kHz

-80

-60

-40

-20

0 0.2 0.4 0.6 0.8 1

Response (dB)

Frequency (Fs)

Figure 14 DAC Digital Filter Frequency Response -192kHz

-1

-0.8

-0.6

-0.4

-0.2

0.2

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Response (dB)

Frequency (Fs)

Figure 15 DAC Digit al Fil ter Ripp le -192kHz

WM8726 Production Data

w PD Rev 4.6 May 2008

DIGITAL DE-EMPHASIS CHARACTERISTI CS

-10

-8

-6

-4

-2

0 2 4 6 8 10 12 14 16

Response (dB)

Frequency (kHz)

Figure 16 De-Emphasis Freq uency Response (32kHz)

-3

-2.5

-2

-1.5

-1

-0.5

0.5

0 2 4 6 8 10 12 14 16

Response (dB)

Frequency (kHz)

Figure 17 De-Emphasis Error (32kHz)

-10

-8

-6

-4

-2

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 18 De-Emphasis Frequ ency Response (44.1kHz)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 19 De-Emphasis Error (44.1kHz)

-10

-8

-6

-4

-2

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 20 De-Emphasis Freq uency Response (48kHz)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 21 De-Emphasis Error (48kHz)

WM8726 Production Data

w PD Rev 4.6 May 2008

APPLICATIONS INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

VDD

GND

CAP

AGND

Hardware Control

WM8726

Notes:

1. C2, C5 should be positioned as close to the WM8726 as possible.

2. Capacitor types should be carefully chosen. Capacitors with very low ESR are

recommended for optimum performance.

3. C3 and C4 not required if using the recommended low pass filter in Figure 20.

VDD

13 FORMAT

12 DEEMPH

VOUTR

VOUTL C

AC-Coupled

VOUTR/L

to External LPF

10 MUTE 6

14 MCLK

3BCKIN

2DIN

Audio Serial Data I/F

AGND

1LRCIN

+ +

Figure 22 External Component Diagram

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE SUGGESTED

VALUE DESCRIPTION

C1 10µF De-coupling for VDD

C2 0.1µF De-c oupl ing for VDD

C3 and C4 10µF Output AC coupling caps to rem ove mi drai l DC level from outputs

C5 0.1µF

C6 10µF Reference de-co upli ng capac itors for CAP pin

Table 7 External Components Description

WM8726 Production Data

w PD Rev 4.6 May 2008

RECOMMENDED ANALOGUE LOW PASS FILTER

+VS

-VS

10uF 51

Ω

7.5K

Ω

680pF

1.8k

Ω

47k

Ω

4.7k

Ω

4.7k

Ω

1.0nF

Figure 23 Recommended 2nd Order Low Pass Filter

An external low pass filter is recommended (see Figure 20) if the device is driving a wideband

amplifier. In some applications, a passive RC filter may be adequate.

PCB LAYOUT RECOMMENDATIONS

Care should be taken in the layout of the PCB that the WM8726 is to be mounted to. The

following notes will help i n this res pect:

1. The VDD supply to the device should be as noise free as possible. This can be

accom pl i shed to a lar ge degree with a 10uF bulk capac it or plac ed locall y to the devic e and a

0.1uF high frequency dec oupling c apacit or plac ed as c los e to t he VDD pi n as possibl e. It is

best to place the 0.1uF c apacitor dir ectly between the VDD and GND pins of the devic e on

the same layer to minimize track inductance and thus improve device decoupling

effectiveness.

2. The CAP pin should be as noise free as possible. This pin provides the decoupling for

the on chi p reference ci rcuits and thus any noise present on this pin will be di rectly c oupled

to the device outputs. In a similar manner to the VDD decoupling described in 1. above, this

pin should be decoupled with a 10uF bulk capacitor local to the device and a 0.1uF

capaci tor as c lose to the CAP pin as poss ibl e.

3. Separate analogue and digital track routing from each other. The device is split into

analogue (pins 5 – 9) and digi t al (pins 1 – 4 & pins 10 – 14) sect ions t hat all ow the routing of

these signals to be easi ly separated. By physic ally separating anal ogue and digit al signal s,

crosstalk from the PCB can be minimized.

4. Use an unbroken solid GND plane. To achieve best performance from the device, it is

advisable to have either a GND plane l ayer on a m ulti layer PCB or to dedicate one side of a

2 layer PCB to be a GND plane. For double sided implementations it is best to route as

many signals as possible on the device mounted side of the board, with the opposite side

acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions

from the PCB and mini m i zes cros stalk between signals .

An evaluat ion board is availabl e for the WM8726 that demonstrates the above techniques and the

excellent performance achievable from the device. This can be ordered or the User manual

downloaded from the Wolfs on web site at www.wolfsonmicro.com

WM8726 Production Data

w PD Rev 4.6 May 2008

PACKAGE DIMENSIONS

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).

D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

Symbols Dimensions

(mm) Dimensions

(Inches)

MIN MAX MIN MAX

A1.35 1.75 0.0532 0.0688

A1 0.10 0.25 0.0040 0.0098

B0.33 0.51 0.0130 0.0200

C0.19 0.25 0.0075 0.0098

D8.55 8.75 0.3367 0.3444

E3.80 4.00 0.1497 0.1574

e1.27 BSC 0.05 BSC

H5.80 6.20 0.2284 0.2440

h0.25 0.50 0.0099 0.0196

L0.40 1.27 0.0160 0.0500

α0o8o0o8o

REF: JEDEC.95, MS-012

0.10 (0.004)

SEATING PLANE

DM001.C

D: 14 PIN SOIC 3.9mm Wide Body

h x 45

-C-

WM8726 Production Data

w PD Rev 4.6 May 2008

IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,

delivery and payment supplied at the time of order acknowledgement.

W olfson warrants performance of it s products to the s pecific ations i n effect at t he date of s hipment . W olfson reserves the right

to m ake changes to its products and specificat ions or to discontinue any product or service without notice. Customers should

therefore obtain the lat es t vers ion of relevant inf ormation from Wolfson to verify that the inform ation is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating

safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or custom er product

design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such

selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

W ol fs on’ s produc ts are not int ended f or us e i n l if e support s ystems , appl i ances , nuc l ear s ys tems or systems where mal func t i on

can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of

products by the cust om er for suc h purposes is at the c us tomer’s own risk.

W olfson does not grant any lic ence (express or im plied) under any patent ri ght, copyright, m ask work right or other intellect ual

property right of Wolfs on c overing or relat ing to any com bi nation, machine, or process in which its produc ts or services m i ght be

or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval,

licenc e, warranty or endorsement thereof. Any third party trade marks contai ned in this docum ent belong to the respect ive third

party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is

accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not

liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any represent ations made, warranties given, and/or liabi lities acc epted by any person which differ from thos e contained in this

datasheet or in W ol fs on’s standard t erm s and conditi ons of sale, del ivery and payment are made, given and/or accepted at that

person’s own risk . W olf son i s not l iable for any such repres entations, warranties or l iabilities or for any reli ance placed thereon

by any person.

ADDRESS:

W ol fs on Microel ec t ronic s plc

W es t fi eld Hous e

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Emai l :: sal es @wolfs onmicro.c om