Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. 00B
04/23/08
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
512K x 32 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION
APRIL 2008
FEATURES
High-speed access times:
8, 10, 20 ns
High-performance, low-power CMOS process
Multiple center power and ground pins for greater
noise immunity
Easy memory expansion with CE and OE op-
tions
CE power-down
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single power supply
VDD 1.65V to 2.2V (IS61WV51232Axx)
speed = 20ns for VDD 1.65V to 2.2V
VDD 2.4V to 3.6V (IS61/64WV51232Bxx)
speed = 10ns for VDD 2.4V to 3.6V
speed = 8ns for VDD 3.3V + 5%
Packages available:
90-ball miniBGA (8mm x 13mm)
Industrial and Automotive Temperature Support
Lead-free available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS61WV51232Axx/Bxx and IS64WV51232Bxx
are high-speed, 16M-bit static RAMs organized as 512K
words by 32 bits. It is fabricated using ISSI's high-perform-
ance CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-perfor-
mance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory.
The device is packaged in the JEDEC standard 90-ball BGA
(8mm x 13mm).
A0-A18
CE
OE
WE
512K x 32
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
VSS
VDD
I/O
DATA
CIRCUIT
DQa-d
BWa-d
CE2
2
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
PIN CONFIGURATION
PACKAGE CODE:
B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ1
DQ2
VSS
VSS
VDD
VSS
A0
A15
CE2
BWb
VDD
VSS
VSS
DQ13
DQ14
DQ0
VDD
DQ3
DQ6
DQ7
BWa
A1
A14
A17
NC
DQ8
DQ9
DQ12
VDD
DQ15
VSS
VSS
DQ4
DQ5
NC
A3
A2
A13
A16
A18
VSS
DQ10
DQ11
VSS
VSS
VDD
VDD
DQ27
DQ26
NC
A4
A10
A8
A9
OE
VDD
DQ21
DQ20
VDD
VDD
DQ31
VSS
DQ28
DQ25
DQ24
BWd
A5
A7
A12
WE
DQ23
DQ22
DQ19
VSS
DQ16
DQ30
DQ29
VDD
VDD
VSS
VDD
A6
A11
CE
BWc
VSS
VDD
VDD
DQ18
DQ17
PIN DESCRIPTIONS
A0-A18 Address Inputs
DQx Data I/O
CE, CE2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
BWx (x=a-d) Byte Write Control
VDD Power
Vss Ground
NC No Connection
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3
Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to VDD + 0.5 V
VDD VDD Relates to GND –0.3 to 4.0 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
CI/O Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
TRUTH TABLE
CECE
CECE
CE CE2 OEOE
OEOE
OE WEWE
WEWE
WE BWaBWa
BWaBWa
BWa BWbBWb
BWbBWb
BWb BWcBWc
BWcBWc
BWc BWdBWd
BWdBWd
BWd DQ0-7 DQ8-15 DQ16-23 DQ24-31 Mode Power
HXXXXXXXHigh-Z High-Z High-Z High-Z Power Down (ISB)
XLXXXXXXHigh-Z High-Z High-Z High-Z Power Down (ISB)
LHLHLLLLData Out Data Out Data Out Data Out Read All Bits (ICC)
L H L H L H H H Data Out High-Z High-Z High-Z Read Byte a (ICC)
Bits Only
L H L H H L H H High-Z Data Out High-Z High-Z Read Byte b (ICC)
Bits Only
L H L H H H L H High-Z High-Z Data Out High-Z Read Byte c (ICC)
Bits Only
LHLHHHHL High-Z High-Z High-Z Data Out Read Byte d (ICC)
Bits Only
LHXLLLLLData In Data In Data In Data In Write All Bits (ICC)
L H X L L H H H Data In High-Z High-Z High-Z Write Byte a (ICC)
Bits Only
L H X L H L H H High-Z Data In High-Z High-Z Write Byte b (ICC)
Bits Only
L H X L H H L H High-Z High-Z Data In High-Z Write Byte c (ICC)
Bits Only
L H X L H H H L High-Z High-Z High-Z Data In Write Byte d (ICC)
Bits Only
LHHHXXXXHigh-Z High-Z High-Z High-Z Selected, (ICC)
Outputs
Disabled
4
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 1.8 V
VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND VIN VDD –1 1 µA
ILO Output Leakage GND VOUT VDD, Outputs Disabled 1 1 µA
Note:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND VIN VDD –1 1 µA
ILO Output Leakage GND VOUT VDD, Outputs Disabled 1 1 µA
Note:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter Test Conditions VDD Min. Max. Unit
VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 V
VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V 0.2 V
VIH Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V
VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
ILI Input Leakage GND VIN VDD –1 1 µA
ILO Output Leakage GND VOUT VDD, Outputs Disabled 1 1 µA
Notes:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width -2.0ns). Not 100% tested.
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
OPERATING RANGE (VDD) (IS61WV51232BLL)(1)
Range Ambient Temperature VDD (8 nS)1VDD (10 nS)1
Commercial 0°C to +70°C 3.3V + 5% 2.4V-3.6V
Industrial –40°C to +85°C 3.3V + 5% 2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets
8ns.
OPERATING RANGE (VDD) (IS64WV51232BLL)
Range Ambient Temperature VDD (10 nS)
Automotive –40°C to +125°C 2.4V-3.6V
HIGH SPEED
OPERATING RANGE (VDD) (IS61WV51232ALL)
Range Ambient Temperature VDD Speed
Commercial 0°C to +70°C 1.65V-2.2V 20ns
Industrial –40°C to +85°C 1.65V-2.2V 20ns
Automotive –40°C to +125°C 1.65V-2.2V 20ns
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. 110 90 50 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 115 95 60
Auto. 140 100
typ.
(2)
60
ICC1 Operating VDD = Max., Com. 85 85 45 mA
Supply Current IOUT = 0 mA, f = 0 Ind. 90 90 55
Auto. 110 90
ISB1TTL Standby Current VDD = Max., Com. 30 30 30 mA
(TTL Inputs) VIN = VIH or VIL Ind. 35 35 35
CE VIH, f = 0 Auto. 70 70
ISB2CMOS Standby VDD = Max., Com. 20 20 20 mA
Current (CMOS Inputs) CE VDD – 0.2V, Ind. 25 25 25
VIN VDD – 0.2V, or Auto. 60 60
VIN 0.2V
, f = 0 typ.
(2)
4
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
6
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 -35
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. 30 25 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 35 30
Auto. 60 60
typ.
(2)
25
ICC1 Operating VDD = Max., Com. 20 20 mA
Supply Current IOUT = 0 mA, f = 0 Ind. 30 30
Auto. 50 50
ISB1TTL Standby Current VDD = Max., Com. 15 15 mA
(TTL Inputs) VIN = VIH or VIL Ind. 20 20
CE VIH, f = 0 Auto. 40 40
ISB2CMOS Standby VDD = Max., Com. 0.8 0.8 mA
Current (CMOS Inputs) CE VDD – 0.2V, Ind. 1.2 1.2
VIN VDD – 0.2V, or Auto. 2 2
VIN 0.2V
, f = 0 typ.
(2)
0.1 0.1
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
OPERATING RANGE (VDD) (IS61WV51232BLS)(1)
Range Ambient Temperature VDD (25 nS)1
Commercial 0°C to +70°C 2.4V-3.6V
Industrial –40°C to +85°C 2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 25ns. When operated in the range of 3.3V
+ 5%, the device meets 20ns.
LOW POWER
OPERATING RANGE (VDD) (IS61WV51232ALS)
Range Ambient Temperature VDD Speed
Commercial 0°C to +70°C 1.65V-2.2V 35ns
Industrial –40°C to +85°C 1.65V-2.2V 35ns
Automotive –40°C to +125°C 1.65V-2.2V 35ns
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC TEST LOADS
Figure 1.
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Figure 2.
Z
O = 50Ω
1.5V
50Ω
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS (HIGH SPEED)
Parameter Unit Unit Unit
(2.4V-3.6V) (3.3V + 5%) (1.65V-2.2V)
Input Pulse Level 0.4V to VDD-0.3V 0.4V to VDD-0.3V 0.4V to VDD-0.2V
Input Rise and Fall Times 1.5ns 1.5ns 1.5ns
Input and Output Timing VDD/2 VDD/2 + 0.05 VDD/2
and Reference Level (VRef)
Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2
8
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 10 ns
tAA Address Access Time 8 10 ns
tOHA Output Hold Time 2.5 2.5 ns
tACE CE Access Time 8 10 ns
tDOE OE Access Time 5.5 6.5 ns
tHZOE
(2)
OE to High-Z Output 3 4 ns
tLZOE
(2)
OE to Low-Z Output 0 0 ns
tHZCE
(2
CE to High-Z Output 0 3 0 4 ns
tLZCE
(2)
CE to Low-Z Output 3 3 ns
tBA Byte Enable to Data Valid
5.5
6.5 ns
tLZB Byte Enable to Low-Z 0 0 ns
tHZB Byte Enable to High-Z 0 3 0 3 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading
specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol Parameter Min. Max. Unit
tRC Read Cycle Time 20 ns
tAA Address Access Time 20 ns
tOHA Output Hold Time 2.5 ns
tACE CE Access Time 20 ns
tDOE OE Access Time 8 ns
tHZOE(2) OE to High-Z Output 0 8 ns
tLZOE(2) OE to Low-Z Output 0 ns
tHZCE(2 CE to High-Z Output 0 8 ns
tLZCE(2) CE to Low-Z Output 3 ns
tBA Byte Enable to Data Valid 8 ns
tLZB Byte Enable to Low-Z 0 ns
tHZB Byte Enable to High-Z 0 3 ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
10
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.e
p
s
ADDRESS
OE
BWa-d
CE
DOUT
t
HZCE
t
HZB
t
BA
t
LZB
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 10 ns
tSCE CE to Write End 6.5 8 ns
tAW Address Setup Time 6.5 8 ns
to Write End
tHA Address Hold from Write End 0 0 ns
tSA Address Setup Time 0 0 ns
tPWB BWa-d Valid to End of Write 6.5 8 ns
tPWE1WE Pulse Width 6.5 8 ns
tPWE2WE Pulse Width (OE = LOW) 8.0 10 ns
tSD Data Setup to Write End 5 6 ns
tHD Data Hold from Write End 0 0 ns
tHZWE
(2)
WE LOW to High-Z Output 3.5 5 ns
tLZWE
(2)
WE HIGH to Low-Z Output 2 2 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading
specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
Shaded area product in development
12
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20 ns
Symbol Parameter Min. Max. Unit
tWC Write Cycle Time 20 ns
tSCE CE to Write End 12 ns
tAW Address Setup Time 12 ns
to Write End
tHA Address Hold from Write End 0 ns
tSA Address Setup Time 0 ns
tPWB
BWa-d
Valid to End of Write 12 ns
tPWE1WE Pulse Width (OE = HIGH) 12 ns
tPWE2WE Pulse Width (OE = LOW) 17 ns
tSD Data Setup to Write End 9 ns
tHD Data Hold from Write End 0 ns
tHZWE(3) WE LOW to High-Z Output 9 ns
tLZWE(3) WE HIGH to Low-Z Output 3 ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input
pulse levels of 0V to 0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input
Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
14
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 2
(WE Controlled. OE is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
BWa-d
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.e
p
s
WRITE CYCLE NO. 3
(WE Controlled. OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
BWa-d
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR3.eps
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 4
(Byte Controlled, Back-to-Back Write)
(1,3)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
BWa-d
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. The internal Write time is defined by the overlap of and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate
the Write. The t
SA
, t
HA
, t
SD
, and t
HD
timing is referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the BWa-d pins can be used to control the Write function.
16
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Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
DATA RETENTION WAVEFORM (CE Controlled)
V
DD
CE V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
1.65V
1.4V
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61WV51232ALL/BLL)
Symbol Parameter Test Condition Min. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V
IDR Data Retention Current VDD = 1.2V, CE VDD – 0.2V Ind. 25 mA
Auto. 60
tSDR Data Retention Setup Time See Data Retention Waveform 0 ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
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17
Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
DATA RETENTION WAVEFORM (CE Controlled)
V
DD
CE V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
1.65V
1.4V
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61WV51232ALS/BLS)
Symbol Parameter Test Condition Min. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V
IDR Data Retention Current VDD = 1.2V, CE VDD – 0.2V Ind. 1.2 mA
Auto. 2
tSDR Data Retention Setup Time See Data Retention Waveform 0 ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 (81) IS61WV51232BLL-10BI 90-ball BGA (8mm x 13mm)
IS61WV51232BLL-10BLI 90-ball BGA (8mm x 13mm), Lead-free
Note:
1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V - 3.6V
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns) Order Part No. Package
20 IS61WV51232ALL-20BI 90-ball BGA (8mm x 13mm)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 IS64WV51232BLL-10BA3 90-ball BGA (8mm x 13mm)
PACKAGING INFORMATION
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
07/31/07
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: B (90-Ball)
mBGA - 8mm x 13mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 90
A 1.45 0.057
A1 0.25 0.40 0.01 0.016
D 12.90 13.00 13.10 0.508 0.512 0.516
D1 11.20 0.441
E 7.90 8.00 8.10 0.311 0.315 0.319
E1 6.40 0.252
e 0.80 0.031
9 8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ø 0.45 + 0.10/−0.05 (90X)
D
e
e
A1
SEATING PLANE
A
D1
E1
E
Notes:
1. Controlling dimensions are in millimeters.
2. 0.8 mm Ball Pitch