Nuvoton Bus Termination Regulator W83312SN W83312SN Table of Content1. GENERAL DESCRIPTION .............................................................................................................. 1 2. FEATURES ...................................................................................................................................... 1 3. BLOCK DIAGRAM ........................................................................................................................... 2 4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT .................................................. 2 5. PIN DESCRIPTION.......................................................................................................................... 3 6. FUNCTIONAL DESCRIPTION ........................................................................................................ 4 7. 6.1 VTT SINK/SOURCE REGULATOR.......................................................................................... 4 6.2 GENERAL REGULATOR ......................................................................................................... 4 6.3 SHUTDOWN FUNCTION ......................................................................................................... 5 6.4 OVER CURRENT PROTECTION ............................................................................................ 5 6.5 OVER TEMPERATURE PROTECTION................................................................................... 5 6.6 THERMAL DESIGN .................................................................................................................. 5 6.7 INPUT CAPACITOR ................................................................................................................. 6 6.8 OUTPUT CAPACITOR ............................................................................................................. 6 6.9 LAYOUT CONSIDERATION .................................................................................................... 6 ELECTRICAL CHARACTERISTIC .................................................................................................. 7 7.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7 7.2 THERMAL INFORMATION ...................................................................................................... 7 7.3 RECOMMENDED OPERATING CONDITIONS....................................................................... 7 7.4 ELECTRICAL CHARACTERISTICS......................................................................................... 7 8. TYPICAL OPERATING WAVEFORMS ........................................................................................... 9 9. PACKAGE DIMENSION ................................................................................................................ 19 10. ORDERING INFORMATION.......................................................................................................... 20 11. TOP MARKING SPECIFICATION ................................................................................................. 20 12. REVISION HISTORY ..................................................................................................................... 21 -I- Publication Date: Dec., 2008 Revision A2 W83312SN 1. GENERAL DESCRIPTION The W83312SN is a linear regulator which provides a power achieves peak 3.0Amp bidirectional sinking and sourcing capability for a high speed bus terminator application. The chip simply implements a stable power supply which tracks half of input power dynamically for bus terminator with a single chip. The W83312SN is promoted with small footprint 8-SOP 150mil power package. With W83312SN design, a high integration, high performance, and cost-effective solution are promoted. 2. FEATURES 2.1. 2.2. 2.3. General z Memory Termination Regulator for DDR1, DDR2, DDR3 and Low Power DDR3 z Sink and Source 3A Peak Current z Integrated Power MOSFET z Adjustable VOUT by External Resistors z Low External Component Count z Low Output Voltage Offset z Current Limit Protection z Over Temperature Protection z 0 to 70 Ambient Operating Temperature Range Package z SOP-8 150mil with Exposed Pad Package z Lead Free (ROHS Compliant) and Halogen Free Application z Desktop PCs, Notebooks, and Workstations z Graphics Card Memory Termination z Set Top Boxes, Digital TVs and Printers z Active Termination Buses z DDR1, DDR2 and DDR3 Memory Systems -1- Publication Date: Dec., 2008 Revision A2 W83312SN 3. BLOCK DIAGRAM VIN VCNTL Current Limit Protection Control VREF VOUT Logic GND Thermal Shutdown 4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT VIN 1 8 NC GND 2 7 NC VREF 3 6 VCNTL VOUT 4 5 NC W83312SN (Top View) -2- Publication Date: Dec., 2008 Revision A2 W83312SN VDDQ=2.5V/1.8V/1.5V VCNTL=3.3V/5V CCNTL CIN R1 VIN VCNTL VREF Enable CSS R2 VTT = VDDQ x R2 / (R1+R2) VOUT GND COUT Typical Application Circuits 5. PIN DESCRIPTION SYMBOL VIN PIN 1 I/O FUNCTION I Main power input pin which supplies current to output pin. For lower power dissipation consideration, using VDDQ (Supply voltage for DRAM) as power source is recommended. Internal reference voltage source. Generally, VREF tracks VDDQ/2 for DDR application. VREF 3 I Using voltage dividing resistors and capacitor as low pass filter for noise immunity and output voltage soft start is recommended. If using an N-MOSFET as shutdown function, please make sure the sinking current capability can pull down VREF under 0.2V. VOUT 4 O Voltage output pin which is regulated to track VREF voltage. VCNTL 6 I Power for internal control logic circuitry. A ceramic decoupling capacitor with 1uF is required. GND 2 NC 5, 7, 8 Ground. Connect to negative terminal of the output capacitor. No connection. -3- Publication Date: Dec., 2008 Revision A2 W83312SN 6. FUNCTIONAL DESCRIPTION 6.1 VTT Sink/Source Regulator The W83312SN is a sink/source tracking Double Data Rate (DDR) termination regulator specifically designed for low input voltage, low cost and low external component count systems where space is a key application parameter. The W83312SN integrates a high performance, low dropout linear regulator that is capable of both sinking and sourcing current. 6.2 General Regulator The W83312SN could also serves as a general linear regulator. The W83312SN accepts an external reference voltage at VREF pin and provides output voltage regulated to this reference voltage. The W83312SN supports VREF voltage from 0.6V to 3.0V, making it versatile and idea for many types of low power LDO applications. The dropout voltage is the input voltage minus output voltage that produces 1% decrease in output voltage. W83312SN VCNT L=5V 0.6 IOUT =1A IOUT =2A Dropout Voltage (V) 0.5 IOUT =1.5A IOUT =2.5A 0.4 0.3 0.2 0.1 0 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 VOUT (V) VCNTL=5V Parameter Dropout Voltage Conditions Typ. Max IOUT=1A, 0.6V VOUT 3.4V 0.15 0.3 IOUT=1.5A, 0.6V VOUT 3.4V 0.25 0.5 IOUT=2A, 0.6V VOUT 3.2V 0.35 0.7 IOUT=2.5A, 1.2V VOUT 3V 0.5 1 -4- Units V Publication Date: Dec., 2008 Revision A2 W83312SN W83312SN VCNT L=3.3V 0.6 Dropout Voltage (V) 0.5 IOUT =1A IOUT =1.5A IOUT =2A IOUT =2.5A 0.4 0.3 0.2 0.1 0 0.6 0.8 1 1.2 1.4 1.6 1.8 VOUT (V) VCNTL=3.3V Parameter Dropout Voltage Conditions Typ. Max IOUT=1A, 0.6V VOUT 1.8V 0.35 0.7 IOUT=1.5A, 0.6V VOUT 1.6V 0.35 0.7 IOUT=2A, 0.6V VOUT 1.6V 0.6 1.2 IOUT=2.5A, 0.8V VOUT 1.4V 0.45 0.9 Units V 6.3 Shutdown Function When the external reference voltage at VREF pin is under shutdown threshold, the internal regulator will be turned off and VOUT is at High-Z state. 6.4 Over Current Protection The W83312SN provides a current limit circuitry, which monitors the output current and controls NMOS's gate voltage to limit the output current at 3.5A, typically. 6.5 Over Temperature Protection The W83312SN monitors its junction temperature. If the device junction temperature exceeds its threshold value, typically 165C, the VOUT is shut off. The shutdown is a non-latch protection. 6.6 Thermal Design Since the W83312SN is a linear regulator, the VOUT current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between VIN and VOUT times IOUT current becomes the power dissipation as shown in below equation. PDISS_SOURCE = (VIN-VOUT) x IOUT_SOURCE -5- Publication Date: Dec., 2008 Revision A2 W83312SN In this case, if VIN is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. For the sink phase, VOUT voltage is applied across the internal LDO regulator and the power dissipation, PDISS_SINK can be calculated by below equation. PDISS_SINK = VOUT x IOUT_SINK Because the device does not sink and source current at the same time and the IOUT current may vary rapidly with time, the actual power dissipation should be the time average of the above dissipations over the thermal relaxation duration of the system. Another source of power consumption is the current used for the internal current control circuitry form VCNTL supply and the VIN supply. This can be estimate as 10mW or less during normal operating conditions. The power must be effectively dissipated from the package. Maximum power dissipation allowed by the package is calculated by below equation. PPKG = [ TJ(MAX) - TA(MAX)] / JA , where z TJ(MAX) is +125C z TA(MAX) is the maximum ambient temperature in the system z JA is the thermal resistance form junction to ambient 6.7 Input Capacitor Depending on the trace impedance between the VIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the VIN input capacitor. Use a 100uF (or greater) capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at VOUT. 6.8 Output Capacitor For stable operation, the total capacitance of the VOUT terminal must be greater than 100uF. Attach two or more capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series inductance (ESL). 6.9 Layout consideration Consider the following points before starting the W83312SN layout design. z The input bypass capacitor for VIN should be placed as close as possible to the pin with short and wide connections. z The output capacitor for VOUT should be placed close to the pin with short and wide connection in order to avoid ESR and/or ESL trace inductance. z In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly to the package's thermal pad. The wide traces of component and the side copper connected to the thermal land pad help to dissipate heat. The thermal land connected to the ground plane could also be used to help dissipation. -6- Publication Date: Dec., 2008 Revision A2 W83312SN 7. ELECTRICAL CHARACTERISTIC Absolute Maximum Ratings 7.1 RATING UNIT Input Voltage ITEM VIN SYMBOL -0.3 to 7 V Control Logic Input Voltage VCNTL -0.3 to 7 V Reference Voltage VREF -0.3 to 5 V 2 kV Machine Mode 200 V Latch-Up 100 mA -65 to 150 Human Body Mode Electrostatic discharge protection Storage Temperature Range Thermal Information 7.2 ITEM Power Dissipation, PD @ TA=25 Package Thermal Resistance, ESOP8, RATING UNIT Internal Limited W 75 /W JA Recommended operating conditions 7.3 ITEM SYMBOL MIN MAX 1.2 5.5 3 5.5 0.6 3 Sourcing 0 2.5 Sinking 0 2.5 Sourcing 0 3.0 Sinking 0 3.0 Operating Temperature Range 0 70 Junction Temperature Range 0 125 VIN Input Voltage VCNTL VREF Continuous Output Current Peak Output Current UNIT V V A A Electrical CHARACTERISTICS 7.4 Typicals and limits appearing in normal type apply for Tj = 25. Limits appearing in Boldface type apply over the entire junction temperature range for operation, 0 to 70 . VCNTL= 3.3V/5V, VIN=2.5V/1.8V/1.5V, VREF=1.25V/0.9V/0.75V, COUT=10uF, all voltage outputs unloaded (unless otherwise noted). PARAMETER SYMBOL TEST CONDITION MIN TYP MAX IOUT=0A, VCNTL=3.3V 0.5 0.7 IOUT=0A, VCNTL=5V 0.7 1 IOUT=0A, VCNTL=3.3V 0.3 0.5 IOUT=0A, VCNTL=5V 0.3 0.5 UNITS Input VCNTL Operating Current VIN Operating Current ICNTL IVIN -7- mA mA Publication Date: Dec., 2008 Revision A2 W83312SN VCNTL Quiescent Current in Shutdown Mode VIN Quiescent Current in Shutdown Mode VREF Leakage Current ISD_CNTL VREF < 0.2V, VCNTL=3.3V 60 90 VREF < 0.2V, VCNTL=5V 60 90 ISD_VIN VREF < 0.2V -1 0 1 IIH VREF=3.3V -1 0 1 IIL VREF=0V -1 0 1 IOUT=0A -5 0 5 uA uA uA Output (DDR1 / DDR2 / DDR3) Output Offset Voltage (VREFVOUT) VOS Load Regulation (VREF-VOUT) VL IOUT=0 +2.5A(1) mV -20 20 IOUT=0 -2.5A -20 20 3 3.5 4.5 A 150 165 175 (1) mV Protection Current Limit ILIM In any VIN Thermal Shutdown Temperature TSD 3.3V < VCNTL < 5V TSD 3.3V < VCNTL < 5V Thermal Shutdown Hysteresis 30 VREF Shutdown Mode Shutdown Threshold VIH Enable VIL Disable 0.6 V 0.2 Note1. 10ms period and 50% duty cycle current pulse -8- Publication Date: Dec., 2008 Revision A2 W83312SN 8. TYPICAL OPERATING WAVEFORMS VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 3A Sourcing VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 3A Sourcing VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 3A Sourcing VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 2.5A Sourcing VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 2.5A Sourcing VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 2.5A Sourcing -9- Publication Date: Dec., 2008 Revision A2 W83312SN VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 3A Sourcing VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 2.5A Sourcing VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 3A Sourcing VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 2.5A Sourcing VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 3A Sourcing VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 2.5A Sourcing -10- Publication Date: Dec., 2008 Revision A2 W83312SN VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 3A Sourcing VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 2.5A Sourcing VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 3A Sourcing VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 3A Sinking VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 2.5A Sourcing VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 2.5A Sinking -11- Publication Date: Dec., 2008 Revision A2 W83312SN VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 3A Sinking VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 2.5A Sinking VIN=1.8V, VCNT3O.9V @ 3A Sinking VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 2.5A Sinking VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 3A Sinking VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 2.5A Sinking -12- Publication Date: Dec., 2008 Revision A2 W83312SN VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 3A Sinking VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 2.5A Sinking VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 3A Sinking VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 2.5A Sinking VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 3A Sinking VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 2.5A Sinking -13- Publication Date: Dec., 2008 Revision A2 W83312SN VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 3A Sinking VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 2.5A Sinking VIN=2.5V, VCNTL=3.3V, VOUT=1.25V, VOUT short to GND VIN=2.5V, VCNTL=5V, VOUT=1.25V, VOUT short to GND VIN=2.5V, VCNTL=3.3V, VOUT=1.25V, VOUT short to VIN VIN=2.5V, VCNTL=5V, VOUT=1.25V, VOUT short to VIN -14- Publication Date: Dec., 2008 Revision A2 W83312SN VIN=1.8V, VCNTL=3.3V, VOUT=0.9V, VOUT short to GND VIN=1.8V, VCNTL=5V, VOUT=0.9V, VOUT short to GND VIN=1.8V, VCNTL=3.3V, VOUT=0.9V, VOUT short to VIN VIN=1.8V, VCNTL=5V, VOUT=0.9V, VOUT short to VIN VIN=1.5V, VCNTL=3.3V, VOUT=0.75V, VOUT short to GND VIN=1.5V, VCNTL=5V, VOUT=0.75V, VOUT short to GND -15- Publication Date: Dec., 2008 Revision A2 W83312SN VIN=1.5V, VCNTL=3.3V, VOUT=0.75V, VOUT short to VIN VIN=1.5V, VCNTL=5V, VOUT=0.75V, VOUT short to VIN VIN=1.2V, VCNTL=3.3V, VOUT=0.6V, VOUT short to GND VIN=1.2V, VCNTL=5V, VOUT=0.6V, VOUT short to GND VIN=1.2V, VCNTL=3.3V, VOUT=0.6V, VOUT short to VIN VIN=1.2V, VCNTL=5V, VOUT=0.6V, VOUT short to VIN -16- Publication Date: Dec., 2008 Revision A2 W83312SN VIN Current vs. Temperature DDR1 @ VCNTL=3.3V DDR1 @ VCNTL=5V -30 -20 -10 0 VIN Current (uA) VCNTL Current (uA) VCNTL Current vs. Temperature 580 560 540 520 500 480 460 440 420 400 260 250 240 230 220 210 200 190 180 170 160 150 140 DDR1 @ VCNTL=3.3V DDR1 @ VCNTL=5V -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90 Temperature (C) Temperature (C) DDR2 @ VCNTL=5V VCNTL Current (uA) VIN Current(uA) DDR2 @ VCNTL=3.3V 180 DDR2 @ VCNTL=3.3V 170 DDR2 @ VCNTL=5V 160 150 140 130 120 -30 -20 -10 0 580 560 540 520 500 480 460 440 420 400 VIN Current vs. Temperature 190 10 20 25 30 40 50 60 70 80 90 Temperature (C) -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90 Temperature (C) VIN Current vs. Temperature VCNTL Current vs. Temperature 160 DDR3 @ VCNTL=3.3V DDR3 @ VCNTL=5V 150 DDR3 @ VCNTL=3.3V VIN Current(uA) VCNTL Current (uA) VCNTL Current vs. Temperature 580 560 540 520 500 480 460 440 420 400 10 20 25 30 40 50 60 70 80 90 140 130 120 DDR3 @ VCNTL=5V 110 -30 -20 -10 0 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90 Temperature (C) -17- 10 20 25 30 40 50 60 70 80 90 Temperature (C) Publication Date: Dec., 2008 Revision A2 W83312SN VCNTL Current vs. Temperature VIN Current vs. Temperature 140 560 540 LP DDR @ VCNTL=3.3V LP DDR @ VCNTL=5V 130 VIN Current(uA) 520 500 480 460 440 LP DDR @ VCNTL=3.3V 420 400 LP DDR @ VCNTL=5V 120 110 100 -30 -20 -10 0 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90 Temperature (C) 10 20 25 30 40 50 60 70 80 90 Temperature (C) Turn On/Off Threshold vs. Temperature 0.45 Turn On Threshold @ VCNTL=3.3V Voltage (V) 0.4 Turn On Threshold @ VCNTL=5V 0.35 Turn Off Threshold @ VCNTL=3.3V Turn Off Threshold @ VCNTL=5V 0.3 0.25 0.2 0.15 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90 Temperature (C) VCNTL Shutdown Current vs. Temperature 70 VCNTL=3.3V 65 VCNTL Current (uA) VCNTL Current (uA) 580 VCNTL=5V 60 55 50 45 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90 Temperature (C) -18- Publication Date: Dec., 2008 Revision A2 W83312SN 9. PACKAGE DIMENSION ESOP-8 (150mil) 3/4 TAPING SPECIFICATION 8 Pin ESOP Package -19- Publication Date: Dec., 2008 Revision A2 W83312SN 10. ORDERING INFORMATION Supplied as Part Number Package Type W83312SN 8PIN ESOP (Green Package) Production Flow E Shape: 100 units/Tube T Shape: 2,500 units/T&R Commercial, 0 to +70 11. TOP MARKING SPECIFICATION W83312SN 752ABBX 1st Line: Nuvoton logo 2nd Line: W83312SN (Part number) 3rd line: Tracking code z 752: packages assembled in Year 2007, week 52 z A: assembly house ID z BB: Internal use only z X: the IC version (A means A; B means B & C means C...etc.) -20- Publication Date: Dec., 2008 Revision A2 W83312SN 12. REVISION HISTORY VERSION DATE PAGE A1 11/28/2008 All A2 12/29/2008 4, 5, 7 DESCRIPTION New Create Update the linear regulator chart & VIN Recommended Range Important Notice Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. -21- Publication Date: Dec., 2008 Revision A2