CY8CLEDAC01T - Cypress Semiconductor

CY8CLEDAC01

AC/DC Digital Current-Mode Controller

for LED Lighting

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-54122 Rev. *B Revised March 29, 2010

Features

■AC offline input range from 80 to 277 VAC

■Constant current control with primary-side feedback

■Energy star compliant for LED lighting

■Up to 30W output power range for universal inputs

■High efficiency (typically > 85%)

■Tight LED current regulation (typically < ± 2.5%)

■Supports up to 130 kHz switching frequency

■Primary-side sens i ng el i mi na t es op to -i so l at ors

■Quasi-resonant operation for highest efficiency and low EMI

■No external compensation components required

■Low startup current (typically 10A)

■Built-in soft start

■Multiple p r ot ection features

❐Current-sense resistor short protection (CSSP)

❐Over-temperature protection (OTP)

❐Output over-voltage protection (OVP)

❐Peak current limit protection (PCLP)

❐Output short circuit protection (OSCP)

❐Single-poi n t fa ul t protecti on

■Applications

❐Offline LED driver

❐LED replacement lamps

❐LED luminaires

❐Pre-regulator for intelligent DC-to-DC LED controllers

Description

The CY8CLEDAC01 is a digital current-mode controller incorpo-

rating proprietary primary side control technology. This new

technology eliminates the cost and complexity in traditional

designs which use opto-isolated feedback and secondary-side

regulation.

The CY8CLEDAC01 uses an advance digital control algorithm

to reduce system design time and improve reliability . The control

algorithm has cycle-by-cycle adaptive digital regulation; this

enables accurate secondary-side constant-current operation

without the n eed for secondary-side sense and control circuits.

The cycle-by-cycle adaptive digital regulation features fast

dynamic response and tight output regulation using critical

discontinuous conduction mode (CDCM) when driving LED

loads. The control algorithm for cycle-by-cycle regulation has

internal compensation for guaranteed system phase and gain

margins; requiring no external components for loop compen-

sation.

The CY8CLEDAC01 has full featured circuit protection not

normally available with other primary-side control solutions. The

built-in protection features include over-voltage protection

(OVP), output short circuit protection (OSCP), peak current limit

protection (PCLP), and current-sense resistor short protection

(CSSP), over-temperature protection (OTP).

The CY8CLEDAC01 also operates as a voltage-mode controller

with all the current-mode controller features, allowing it to

operate as a AC-to-DC front-end for intelligent LED controllers

such as Cypress’s PowerPSoC® family.

Figure 1. Simplified Application Diagram

AC Input

NTC

LED

VSENSE

VIN

VCC

OUTPUT

ISENSE

GND

OPTIONAL POWER

FACTOR CIRCUIT ISOLATED FLYBACK

CONVERSION

CONTROLLER

EMI FILTER

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 2 of 14

Contents

FEATURES ...........................................................................1

DESCRIPTION ......................................................................1

CONTENTS ...........................................................................2

LOGIC BLOCK DIAGRAM .............. .............. ... .............. ... .. .3

FUNCTIONAL DESCRIPTION ..............................................3

Overview ........................................................................3

Constant Current Operation ............ .............. .. ... ............4

Valley Mode Switching ...................................................4

Protection Features ............. .............. ... .............. ... ... ......4

Understanding Primary Feedback ..................................5

Constant Voltage Operation ...........................................6

Dynamic Load Transient ............................ ... .. .............. .6

Variable Frequency Operation ........ ................ ...............6

Internal Loop Compensation ..........................................6

PFM Mode at Light Load .............. ... .. .............. ... ............6

PIN INFORMATION ..............................................................7

ELECTRICAL SPECIFICATIONS .........................................8

Absolute Maximum Ratings ............................................8

ELECTRICAL CHARACTERISTICS ....................................9

TYPICAL PERFORMANCE CHARACTERISTICS ...............10

ORDERING INFORMATION .......... ... .............. ... ... ... .............12

ORDERING CODE DEFINITIONS ................ .. ... ... .............. ..12

PACKAGING INFORMATION ..............................................13

Physical Package Dimensions .......................................13

DOCUMENT HISTORY PAGE .......... ... .............. ... .............. ..14

SALES, SOLUTIONS, AND LEGAL INFORMAT IO N ..........14

Worldwide Sales and Design Support ............................14

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 3 of 14

Logic Block Diagram

Figure 2. Logic Block Diagram

Functional Description

Overview

The digital logic control block is the main block. All other blocks

are inputs or outputs for the control block.

The control block receives signals to determine the input voltage

(VIN), output voltage (VSENSE), temperature (SD), output

operation (VCC), and output current (ISENSE).

The control block has three output controls; SDMODE (shutdown

mode control), DAC VIPK (current control), and VGATE (gate drive

control).

The control block does not start operation until VCC has charged

to the startup threshold (VCCST) as shown in Figure 3. VCC is

charged through a diode connection from VIN. VIN receives a

voltage from a rectified main power input. When VCC is charged

to VCCST, the startup block enables the VIN scaling resistance

(ZVin) and the control block. The startup block also monitors the

VCC level and resets the system when VCC decreases to a

brown-out level (VCCUVL). The reset initiates a startup sequence

where VCC is charged to VCCST level through a diode connection

from VIN.

When the ZVin resistor is enabled, a voltage VIN_A is measurable

by an ADC. The output of the ADC is provided to the control block

for auto-calculation of the VINtON product where tON is the on

time for the flyback MOSFET. After the voltage on VIN_A is above

the startup low voltage threshold (VINSTLOW), the

CY8CLEDAC01 commences an adaptive soft start function. The

soft start control algorithm is applied at startup, during which the

initial output pulses are small and gradually increase until the full

pulse width is achieved.

The VSENSE pin connects to the Signal Conditioning bl ock. The

Signal Conditioning block provides two inputs to the control

block: VFB (Voltage Feed Back) and VVMS (V olt age Valley Mode

Switch). VFB provides over-voltage protection and VCC

measurement. VVMS is the valley switch detection. VFB is

monitored by the control block to determine if the output is

over-voltage. When the control block detects an over-voltage

condition, it enters a shutdown mode and wait for POR to

re-initialize the system. VVMS is monitored by the control block to

determine when the power in the flyback MOSFET is at a

minimum or in a 'valley'. The control block starts the next cycle

at the 'valley' for maximum efficiency and minimum switching

EMI.

ADC

DAC

IPEAK

VIPK

0 ~ 1V

1.1V

60kohm

Enable Startup

VIN_A

0.2 ~ 2V

ZVin

5kohm

Digital Logic

Control

VIN

VSENSE

VCC

OUTPUT

ISENSE

GND

Signal

Conditioning

VFB

VVMS

ISD

VSD-TH

Gate

Driver

VOCP

RSD

8.33kohm

SDMODE

VGATE

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 4 of 14

The SD pin connects to two blocks; a switched current source

(ISD) and an analog comparator . These two blocks work together

for OTP and optio nal OVP. For an OTP implementation, the SD

pin can be connected to an external NTC component. The

current source causes a voltage to be developed at the SD pin

which causes the analog comparator's ou tput to be high or low

depending upon a 1V comparator reference. If the voltage

across the NTC is less than 1V, the control block enters a

shutdown mode and wait for POR to reinitialize the system.

The ISENSE pin connects to circuitry composed of three blocks:

DAC VIPK, IPEAK comparator , and VOCP comparator . These three

blocks work together for soft-start control, peak current

detection, and over-current protection. The DAC VIPK controls

soft-start, minimizing stress associated with system st artup. The

IPEAK comparator monitors the voltage at the ISENSE pin. The

voltage is generated by current flowing through a small external

resistor (RISENSE - not shown). When the ISENSE voltage reaches

1V, th e IPEAK comparator asserts a high to the control block. The

control block shuts off the output and waits for VVMS detection; it

then starts the next cycle. The VOCP comparator provides

primary side over-current protection. When the voltage on

ISENSE reaches 1.1V, the VOCP signal gets asserted. When

over-current is detected, the control block enters a shutdown

mode and waits for POR to re initialize the system.

The OUTPUT pin connects to the Gate Driver block. The Gate

Driver connects to the OUTPUT pi n that in turn connects to the

flyback MOSFET gate pin (not shown). The OUTPUT pin is a

digital control pin that switches between a high level (approxi-

mately VCC) and a low level (approximately ground). The

duration for high (tON)and low (tOFF) of the Gate Driver is a

function of the control block operating upon its inputs: VINtON,

VFB, VVMS, SD, IPEAK, VOCP, and VCC.

Figure 3. Device Startup Sequence

Constant Current Operation

Constant current (CC) mode is the normal operating mode for

LED lighting applications. CY8CLEDAC01 operates in CC mode

when VSENSE is set below VSENSENOM. During this mode, the

CY8CLEDAC01 regulates the o utput curren t at a constant level

regardless of the output voltage. It operates in critical discon-

tinuous conduction mode (CDCM) while in CC mode.

To achieve CC regulation , the CY8CLEDAC01 senses the load

current indirectly through the primary current. The primary

current is detected by the ISENSE pin through a resistor from the

MOSFET source to ground.

Valley Mode Switching

To reduce EMI and switching losses in the MOSFET, the

CY8CLEDAC01 employs valley mode switching when operating

in CDCM by switching at the lowest MOSFET VDS (see

Figure 4). It detects valleys in the MOSFET drain voltage

indirectly through the VSENSE pin. This voltage is provided by the

auxiliary winding of the flyback transformer and represents a

copy of the secondary side characteristics (see Figure 7 on page

6).

Figure 4. Valley Mode Switching

T urning on at the lowest VDS generates lowest dV/dt; thus valley

mode switching minimizes switching losses and reduces EMI. To

limit the switching frequency range, the CY8CLEDAC01 can skip

valleys (second cycle in Figure 4) when the switching frequency

becomes too high.

The CY8CLEDAC01 supports valley mode switching in both CC

and constant voltage (CV) modes of operation. This feature is

superior to other quasi-resonant technologies which only support

valley mode switching during constant voltage operation.

Protection Features

The CY8CLEDAC01 has full featured circuit protection not

normally available with other primary-side control solutions.

The built-in protection features include over-voltage protection

(OVP), output shor t circuit prot ecti on (OSCP) , pe ak cu rrent li mit

protection (PCLP), and current-sense resistor short protection

(CSSP), over-temperature protection (OTP).

In an event a protection is triggered, VCC discharges below

VCCUVL and causes a POR except in case of PCLP. The

controller now initiates a new soft start cycle and continues to

attempt start-up. It is unable to start up until the fault condition is

removed.

Current Sense Resistor Short Protection (CSSP)

If the ISENSE sense resistor is shorted, there is a potential danger

of an over-current condition not being detected. The

CY8CLEDAC01 has a separate circuit to detect this fault. This

protection mode is triggered if the ISENSE voltage is below 0.15V

in CC mode and only at heavy loads in CV mode.

Over-T emperature Protection (OTP) and/or Output Over-Voltage

Protection (OVP)

The shutdown (SD) pin along with an external NTC provides

over-temperature protection. T he SD pin also provides optional

over-voltage protection by sensing a scaled auxiliary winding

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 5 of 14

voltage from the flyback transformer using external components.

The CY8CLEDAC01 switches between monitoring an

over-temperature fault and an over-voltage fault on the SD pin

by using the SDMODE control signal (shown in Figure 2 on page

3). For an over-temperature fault the voltage on the NTC is

detected by connecting an internal current source to the pin. For

an over-voltage fault the voltage on the SD pin is checked using

an internal pulldown resistance RSD. The measurements are

made during the last VGATE cycle in the measurement window to

allow transients to settle.(shown in Figure 5)

Figure 5. SD Detection

When SDMODE is high and the voltage across the NTC is lower

than 1V during normal operation or 1.2V during start-up an OTP

is triggere d. When SDMODE is low and the sensed voltage on the

SD pin is higher than 1V an OVP fault is triggered.

Output Over-Voltage Protection (OVP)

The CY8CLEDAC01 includes a function that protects against an

output over-voltage. The output voltage is monitored by the

VSENSE pin. The protection is triggered if the vol tage at this pin

exceeds the over-voltage threshold VSENSEMAX.

Peak Current Limit Protection (PCLP)

The ISENSE pin of the CY8CLEDAC01 monitors the primary peak

current. This enables cycle-by-cycle peak current control and

limiting. When the prima ry peak curren t multiplied by the sense

resistor value is greater than 1.1V, an over-current condition is

detected and the IC immediately turns off the MOSFET driver.

During the next switching cycle, the driver sends out a regular

switching pulse and turns off again if the OCP threshold is still

reached. Normal switching resumes if the fault is removed and

the OCP threshold is not reached.

Output Short Circuit Protection (OSCP)

The CY8CLEDAC01 includes a function that protects against an

output short circuit. The output voltage is monitored by the

VSENSE pin. The protection is triggered if the vol tage at this pin

is below 0.22V.

Note When the VSENSE is at this level, the controller is by default

operating in CC mode and hence an over current condition

cannot happen.

Single Point Fault Protection

The CY8CLEDAC01 detect a short on any of the following pins

ISENSE, VSENSE, VCC, OUTPUT, and SD. Therefo re, any single

point fault is protecte d ag a i nst.

Understanding Primary Feedback

Figure 6 illustrates a simplified flyback converter. When the

switch Q1 conducts during tON(t), the current ig(t) is directly

drawn from rectified sinusoid vg(t). Th e ene rgy Eg(t) is stored in

the magnetizing inductance LP. The rectifying diode D1 is

reverse biased and the load current IO is supplied by the

secondary capacitor CO. When Q1 turns off, D1 conducts and

the stored energy Eg(t) is delivered to the output.

Figure 6. Simplified Flyback Converter

When operating in CC mode, to tightly regulate outpu t current,

information about the load current needs to be accurately

sensed. To achieve CC regulation, this information can be

derived indirectly by sensing the primary current.

When operating in CV mode, to tigh tly regulate output voltage,

information about the o utput voltage and load curren t needs to

be accurately sensed. In the DCM flyback converter, this infor-

mation can be read through the auxiliary winding.

During the Q1 on time, the load current is supplied from the

output filter capacitor CO. The voltage across LP is vg(t),

assuming the voltage dropped across Q1 is zero. The current in

Q1 ramps up linearly at a rate of:

Equation 1

At the end of on time, the current has ramped up to:

Equation 2

This current represents a stored energy of:

Equation 3

When Q1 turns off, ig(t) in LP forces a reversal of polarities on all

windings. Ignoring the commutation time caused by the leakage

inductance LKP at the instant of turn-off, the primary current

transfers to the secondary at a peak amplitude of:

Equation 4

Assuming the secondary winding is master and the auxiliary

winding is slave, the auxiliary voltage is given by:

VGATE

SDMODE

OVP

Detection OTP

Detection

Connected to RSD Connected to ISD

vin(t) AC

iin(t)

vg(t)

ig(t) id(t)

Ts(t) Q1

LAUX

NAUX

gg L

tdi )()( 

ONg

peakg L

ttv



)(

)(

_)(

Epeakg

g

)()( _ti

ti peakg

d

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 6 of 14

Equation 5

and reflects the output voltage as shown in Figure 7.

Figure 7. Auxiliary Voltage Waveforms

The voltage at th e load differs from the secondary voltage by a

diode drop and IR losses. The diode drop is a function of current,

as are IR losses. Thus, if the secondary voltage is always read

at a constant secondary current, the difference between the

output voltage and the secondary voltage is a fixed V. Further ,

if the voltage can be read when the secondary current is small;

for example, at the knee of the auxiliary waveform (see Figure

7), then V is also small. With th e CY8CLEDAC01, V can be

ignored.

The real time waveform analyzer in the CY8CLEDAC01 reads

the auxiliary waveform information cycle by cycle. The part then

generates a feedback voltage VFB. The VFB signal precisely

represents the output voltage and is used to regulate the output

voltage.

Constant Voltage Operation

The CY8CLEDAC01 also features a constant voltage (CV)

mode. It operates in CV mode when VSENSE is set between

VSENSENOM and VSENSEMAX. After soft start is completed, the

digital control block measures the output conditions. It deter-

mines output power levels and adjusts the control system

according to a light load or a heavy load. It uses CDCM or pulse

width modulation (PWM) at high output power levels and

switches to pulse freque ncy modulation (PFM) at light loads to

minimize power dissipation. The PWM switching frequency is

between 30 kHz and 130 kHz, depending on the line and load

conditions.

Dynamic Load Transient

There are two components that compose the voltage drop during

a load transient event.

VDROP(sense) is the drop in voltage before the VSENSE signal i s

able to show a significant drop in output voltage. This is deter-

mined by Vmin or the reference voltage at which a load transient

is detected. The smaller the Vmin is, the smaller is the drop in

voltage.

Equation 6

Remember that a smaller Vmin is less tolerant of noise and can

lead to signal distortion in VSENSE.

The final drop in voltage is due to the time from when VSENSE

drops Vmin to w hen the next VSENSE signal appears. In the worst

case condition this is how much voltage drops during the longest

switching period.

Equation 7

A larger output capacitance in this case greatly reduces the

VDROP(IC).

Variable Frequency Operation

An internal circuit checks for the falling edge of VSENSE on every

switching cycle. If the falling edge of V SENSE is not detected, the

off-time is extended until the falling edge of VSENSE is detected.

The maximum allowed transformer reset time for the

CY8CLEDAC01 is 75 µs.

Internal Loop Compensation

The CY8CLEDAC01 incorporates an internal digital error

amplifier with no requirement for external loop compensation.

For a typical power supply design, the loop stability is guaranteed

to provide at least 45 degrees of phase margin and -20 dB of gain

margin.

PFM Mode at Light Load

The CY8CLEDAC01 normally operates in a fixed frequency

PWM or Critical Discontinuous Conduction Mode when IOUT is

greater than approximately 10 percent of the specified maximum

load current. As the output load IOUT is reduced, the on-time tON

is decreased. The moment the load current drops below 10

percent of nominal, the con troller transitions to pulse freque ncy

modulation (PFM) mode. Thereafter , the on-time is modulated by

the line voltage and the off-time is modulated by the load current.

The device automaticall y returns to PWM mode when the load

current increases.

)V(  O

AUX

AUX V



()

() () (min)

()

OUT design

DROP sense SENSE nom SENSE

SENSE nom

VVV



OUT

NoLoadPOUT

ICDROP C

V)(

)(





CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 7 of 14

Pin Information

Pin No. Name Type Description

1NC -No connection

2 VSENSE Ana log Input Sense signal input from auxiliary winding. This provides the secondary voltage

feedback used for output regulation.

3 VIN Analog Input Sense signal input from the rectified line voltage. VIN is used for line regulation. The

input line voltage is scaled down using a resistor network, and is used for input

under-voltage and over-voltage protection. This pin also provides the supply current

to the IC during startup.

4SD Analog Input External shutdown control. This pin should be pulled down to GND using a 20k

resistor if shutdown control is not required.

5 GND Ground Ground

6 ISENSE Analog Input Primary current sense. Used for cycle by cycle peak current control.

7OUTPUT Output Gate drive for external MOSFET switch

8 VCC Power Input Power supply for the controller during normal operation. The controller starts up

when VCC reaches 12V (typical) and shuts down when the VCC voltage is below 6V

(typical). A decoupling capacitor should be connected between the VCC pin and

GND.

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 8 of 14

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8CLEDAC01, of the PowerPSoC device family. For the most

up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at

http://www.cypress.com/powerpsoc. Specifications are valid for -40°C  TA  85°C and TJ  125°C, except where noted. Table 1 lists

the units of measure that are used in this section.

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. Not all user guidelines are production tested

Table 1. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure Symbol Unit of Measure

°C degrees Celsius kbit 1024 bits mA milliampere

dB decibels kHz kilohertz ms millisecond

Hz Hertz kkilohms mV millivolts

pp peak-to-peak MHz megahertz mA milliwatts

sigma:one standard deviation Mmegaohms nA nanoamperes

Vvolts Amicroamperes ns nanoseconds

ohms Fmicrofarads nV nanovolts

KB 1024 bytes Hmicrohenrys pA picoamperes

ppm parts per million smicroseconds pF picofarads

sps samples per second Vmicrovolts ps picoseconds

Wwatts Vrms microvolts

root-mean-square fF femtofarads

Aamperes Wmicrowatts

Symbol Description Min Typ Max Units Notes

VCC DC supply voltage range -0.3 -18 Vpin 8, ICC = 20 mA max

ICC DC supply current at VCC pin - - 20 mA pin 8

Output pin voltage -0.3 -18 Vpin 7

VSENSE pin voltage -0.7 -4.0 Vpin 2, ISENSE < 10 mA

VIN pin voltage -0.3 -18 Vpin 3

ISENSE pin voltage -0.3 -4.0 Vpin 6

SD pin voltage -0.3 -18 Vpin 4

PDPower Dissipation - - 526 mW TA < 25°C

TJ,max Maximum Junction Temperature - - 125 °C

TSTG Storage Temperature -65 -150 °C

TLEAD Lead Temperature - - 260 °C During IR reflow for < 15 seconds

JA Thermal Resistance Jun cti o n-t o-ambient - - 160 °C/W

VESD ESD Voltage Rating - - 2000 Vas per JEDEC JESD22-A114

ILU Latch Up Current -100 -100 mA as per JEDEC JESD78

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 9 of 14

Electrical Characteristics

Notes

1. Adjust VCC above the startup threshold before setting at 12V.

2. These parameters are not 10 0% tested, guaranteed by design and characterization.

3. Operating frequency varies based on the line and loa d conditions, see Functional Description on page 3 for more det ails.

VCC=12V; -40°C  TA  85°C unless otherwise specified[1]

Symbol Description Min Typ Max Units Notes

VIN Section (pin 3)

VINSTLOW Startup low voltage threshold 335 369 406 mV TA= 25°C Positive Edge

IINST Startup current - 10 15 AV

IN = 10V, CVCC=10 F

ZIN Input impedance - 5 - kAfter Startup

VSENSE Section (pin 2)

IBVS Input leakage current - - 1 A VSENSE = 2V

VSENSENOM Nominal voltage threshold 1.523 1.538 1.553 V TA = 25°C Negative Edge

VSENSEMAX Output OVP threshold 1.790 1.846 1.900 V TA = 25°C Negative Edge

OUTPUT Section (pin 7)

RDS(ON)LO Output low level ON-resistance - 40 - ISINK = 5 mA

RDS(ON)-HP Output high level ON-resistance - 102 - ISOURCE = 5 mA

tRRise time[2] - 200 300 ns TA= 25°C; CL = 330 pF; 10% to 90%

tFFall time[2] -4060nsT

A= 25°C; CL=330 p F; 10% to 90%

FSWMAX Maximum switching frequency[3] - 130 140 kHz Any Combination of Line and Loads

VCC Section (pin 8)

VCCMAX Maximum operating voltage - - 16 V

VCCST Startup threshold 10.8 12 13.2 V V CC Rising

VCCUVL Under-vol tage lockout threshold 5.5 6.0 6.6 V VCC Falling

ICC Operating current - 3.5 - mA CL= 330 pF; VSENSE = 1.5V

ISENSE Section (pin 6)

VPEAK Peak limit threshold 1.1 V

VRSNS ISENSE short protection reference - 0.15 - V

VREGTH CC regulation threshold limit - 1.0 - V

SD Section (pin 4)

VSDTH Shutdown threshold 0.95 1.0 1.05 V

VSDTHST Shutdown threshold in startup - 1.2 - V

IBVSD Input leakage current - - 1.0 AV

SD = 1.0V

RSD Pull down resistance 7.916 8.333 8.750 k

ISD Pull up current source 96 107 118 A

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 10 of 14

Typical Performance Characteristics

Figure 8. VCC Supply Current versus VCC Figure 9. Switching Freque ncy% Change versus

Temperature

Figure 10. Startup Threshold versus Temperature Figure 11. Internal Reference versus Temperature

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 11 of 14

Figure 12. TON Compensation Chart

Note

4. IOUT refers to the difference in constant current limit between 264 VAC and 90 VAC when no RDLY and CDLY are applied.

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 12 of 14

Ordering Information

Ordering Code Definitions

Ordering Code No. of Pins Package Temperature Range

CY8CLEDAC01 8 SOIC -40°C to 85°C

CY 8 C LED AC 01

01 = Non Dimmable

AC = Offline

Family Code: LED = LED Applications

Technology Code: C = CMOS

Marketing Code: 8 = PowerPSoC Family

Company ID: CY = Cypress

CY8CLEDAC01

Document Number: 001-54122 Rev. *B Page 13 of 14

Packaging Information

Physical Package Dimensions

Figure 13. 8-Pin Small Outline (SOIC) Package

001-54263 **

Document Number: 001-54122 Rev. *B Revised March 29, 2010 Page 14 of 14

PowerPSoC® and PSoC® are registered trademarks and PSoC Designer™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are

property of the respective corporations.

CY8CLEDAC01

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assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypr ess does n ot author ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

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Document Title: CY8CLEDAC01 AC/DC Digital Current-Mode Controller for LED Lighting

Document Number: 001-54122

Revision ECN No. Orig. of

Change Submission

Date Description of Change

** 2721319 KJV/AESA 06/19/2009 New data sheet

*A 2829351 KJV/PYRS 12/16/2009 Added Contents. Updated text in Features, Description, and Functional

Description sections. Upda ted Electrical Sp ecifications

*B 2901104 KJV/VED 03/29/2010 Release to web.