1
0.5MHz, Low Supply Voltage, Low Input Current BiMOS
Operational Amplifiers
CA5420A
The CA5420A is an integrated circuit operational amplifier that
combines PMOS transistors and bipolar transistors on a single
monolithic chip. It is designed and guaranteed to operate in
microprocessor logic systems that use V+ = 5V, V- = GND, since it
can operate down to ±1V supplies. It will also be suitable for 3.3V
logic systems.
The CA5420A BiMOS operational amplifier features
gate-protected PMOS transistors in the input circuit to provide
very high input impedance, very low input currents (less than
1pA). The internal bootstrapping network features a unique
guardbanding technique for reducing the doubling of leakage
current for every +10°C increase in temperature. The CA5420A
operates at total supply voltages from 2V to 20V either single or
dual supply. This operational amplifier is internally phase
compensated to achieve stable operation in the unity gain
follower configuration. Additionally, it has access terminals for a
supplementary external capacitor if additional frequency roll-off is
desired. Terminals are also provided for use in applications
requiring input offset voltage nulling. The use of PMOS in the
input stage results in common-mode input voltage capability
down to 0.45V below the negative supply terminal, an important
attribute for single supply application. The output stage uses a
feedback OTA type amplifier that can swing essentially from
rail-to-rail. The output driving current of 1.0mA (Min) is provided by
using nonlinear current mirrors.
This device has guaranteed specifications for 5V operation
over the full military temperature range of -55°C to +125°C.
The CA5420A has the same 8 lead pinout used for the industry
standard 741.
Features
• CA5420A at 5V Supply Voltage with Full Military
Temperature Range Guaranteed Specifications
• CA5420A Guaranteed to Operate from ±1V to ±10V
Supplies
• 2V Supply at 350µA Supply Current
• 1pA (Typ) Input Current (Essentially Constant to +85°C)
• Rail-to-Rail Output Swing (Drive ±2mA Into 1kΩ Load)
• Pin Compatible with 741 Op Amp
• Pb-Free (RoHS Compliant)
Applications
•pH Probe Amplifiers
• Picoammeters
• Electrometer (High Z) Instruments
• Portable Equipment
• Inaccessible Field Equipment
• Battery Dependent Equipment (Medical and Military)
•5V Logic Systems
• Microprocessor Interface
MOS
BIPOLAR
X1
X1
MOS
BIPOLAR
OTA BUFFER
(X2)
HIGH GAIN
(50k)
BUFFER AMPS;
BOOTSTRAPPED
INPUT PROTECTION
NETWORK
-
+
FIGURE 1. FUNCTIONAL DIAGRAM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 1998, 2005, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
August 18, 2011
FN1925.7
CA5420A
2FN1925.7
August 18, 2011
Pin Configuration
CA5420A
(8 LD SOIC)
TOP VIEW
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
CA5420AMZ 5420 AMZ -55 to +125 8 Ld SOIC M8.15
NOTES:
1. Add “96” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for CA5420A. For more information on MSL please see techbrief TB363.
1
2
3
4
8
7
6
5
+
V+
OFFSET
INV.
INPUT
V-
NON-INV.
INPUT
STROBE
OUTPUT
OFFSET
NULL
NULL
-
Pin is connected to Case.
CA5420A
3FN1925.7
August 18, 2011
+
Absolute Maximun Ratings Thermal Information
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . . . . . . . . 22V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 4). . . . . . . . . . . . . . . . . . . . . . Indefinite
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Thermal Resistance (Typical, Note 5) θJA (°C/W) θJC (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 157 N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range (All Types) . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Short circuit may be applied to ground or to either supply.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Typical Values Intended Only for Design Guidance. V+ = +5V; V- = GND, TA = +25°C
PARAMETER SYMBOL TEST CONDITIONS CA5420A UNITS
Input Resistance RI150 TΩ
Input Capacitance CI4.9 pF
Output Resistance RO300 Ω
Equivalent Input
Noise Voltage
eNf = 1kHz RS = 100Ω62 nV/√Hz
f = 10kHz 38 nV/√Hz
Short-Circuit Current To Opposite
Supply
Source IOM+2.6mA
Sink IOM-2.4mA
Gain Bandwidth Product fT0.5 MHz
Slew Rate SR 0.5 V/µs
Transient Response Rise Time trRL = 2kΩ, CL = 100pF 0.7 µs
Overshoot OS 15 %
Current from Terminal 8 To V- I8+20µA
Current from Terminal 8 To V+ I8-2mA
Settling Time 0.01% AV = 1 2VP-P Input 8 µs
0.10% AV = 1 2VP-P Input 4.5 µs
Electrical Specifications TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified.
PARAMETER SYMBOL
TEST
CONDITIONS
CA5420A
UNITS
MIN
(Note 6) TYP
MAX
(Note 6)
Input Offset Voltage VIO VO = 2.5V - 1 5 mV
Input Offset Current IIO VO = 2.5V - 0.02 4 pA
Input Current IIVO = 2.5V - 0.02 5 pA
Common Mode Rejection Ratio CMRR VCM = 0 to 3.7V, VO = 2.5V 75 83 - dB
Common Mode Input Voltage Range VlCR+V
O = 2.5V 3.7 4 - V
VlCR- - -0.3 0 V
Power Supply Rejection Ratio PSRR ΔV+ = 1V; ΔV- = 1V 70 83 - dB
Large Signal Voltage Gain AOL
VO = 0.5 to 4V RL = ∞85 87 - dB
VO = 0.5 to 4V RL = 10kΩ85 87 - dB
VO = 0.7 to 3V RL = 2kΩ80 85 - dB
Source Current ISOURCE VO = 0V 1.2 2.7 - mA
CA5420A
4FN1925.7
August 18, 2011
Sink Current ISINK VO = 5V 1.2 2.1 - mA
Output Voltage VOM+R
L = ∞4.85 4.94 - V
VOM- - 0.13 0.15 V
VOM+R
L = 10kΩ4.7 4.9 - V
VOM- - 0.12 0.15 V
VOM+R
L = 2kΩ3.5 4.6 - V
VOM--0.10.15V
Supply Current ISUPPLY VO = 0V - 400 550 µA
VO = 2.5V - 430 600 µA
Electrical Specifications TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified. (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
CA5420A
UNITS
MIN
(Note 6) TYP
MAX
(Note 6)
Electrical Specifications TA = -55°C to +125°C, V+ = 5V, V- = 0, Unless Otherwise Specified. Boldface limits apply over the
operating temperature range, -55°C to +125°C.
PARAMETER SYMBOL
TEST
CONDITIONS
CA5420A
UNITS
MIN
(Note 6) TYP
MAX
(Note 6)
Input Offset Voltage VIO VO = 2.5V - 2 10 mV
Input Offset Current IIO VO = 2.5V - 1.5 3nA
Up to TA = +85°C -210 pA
Input Current |II|VO = 2.5V - 2 5nA
Up to TA = +85°C -1015 pA
Common Mode Rejection Ratio CMRR VCM = 0 to 3.7V,
VO = 2.5V
70 80 - dB
Common Mode Input Voltage Range VlCR+V
O = 2.5V 3.7 4- V
VlCR- - -0.3 0V
Power Supply Rejection Ratio PSRR ΔV+ = 1V;
ΔV- = 1V
70 83 - dB
Large Signal Voltage Gain AOL
VO = 0.5 to 4V RL = ∞65 75 - dB
VO = 0.7 to 4V RL = 10kΩ80 87 - dB
VO = 0.7 to 2.5V RL = 2kΩ75 80 - dB
Source Current ISOURCE VO = 0V 12.7 - mA
Sink Current ISINK VO = 5V 12.1 - mA
Output Voltage VOM+R
L = ∞4.8 4.9 - V
VOM--0.160.2 V
VOM+R
L = 10kΩ4.7 4.9 - V
VOM- - 0.15 0.2 V
VOM+R
L = 2kΩ34- V
VOM--0.140.2 V
Supply Current ISUPPLY VO = 0V - 430 600 µA
VO = 2.5V - 480 650 µA
CA5420A
5FN1925.7
August 18, 2011
Electrical Specifications For Equipment Design at VSUPPLY = ±1V, TA = +25°C, Unless Otherwise Specified.
PARAMETER SYMBOL
TEST
CONDITIONS
CA5420A
UNITS
MIN
(Note 6) TYP
MAX
(Note 6)
Input Offset Voltage VIO -2 5 mV
Input Offset Current |IIO|-0.01 4 pA
Input Current |II|-0.02 5pA
Large Signal Voltage Gain AOL RL = 10kΩ10 100 - kV/V
80 100 - dB
Common Mode Rejection Ratio CMRR - 560 - µV/V
60 65 - dB
Common Mode Input Voltage Range VlCR+0.2 0.5 - V
VlCR--1 -1.3 - V
Power Supply Rejection Ratio PSRR - 32 425 µV/V
70 90 - dB
Maximum Output Voltage VOM+R
L = ∞0.9 0.95 - V
VOM--0.85 -0.91 - V
Supply Current ISUPPLY - 350 650 µA
Device Dissipation PD-0.7 1.1 mW
Input Offset Voltage Temp. Drift ΔVIO/ΔT - 4 - µV/°C
Electrical Specifications For Equipment Design at VSUPPLY = ±10V, TA = +25°C, Unless Otherwise Specified.
PARAMETER SYMBOL
TEST
CONDITIONS
CA5420A
UNITS
MIN
(Note 6) TYP
MAX
(Note 6)
Input Offset Voltage VIO -2 5 mV
Input Offset Current |IIO|-0.03 4 pA
Input Current |II|-0.05 5 pA
Large Signal Voltage Gain AOL RL = 10kΩ20 100 - kV/V
80 100 - dB
Common Mode Rejection Ratio CMRR - 100 320 µV/V
70 80 - dB
Common Mode Input Voltage Range VlCR+ 9 9.3 - V
VlCR- -10 -10.3 - V
Power Supply Rejection Ratio PSRR - 32 320 µV/V
70 90 - dB
Maximum Output Voltage VOM+R
L = ∞9.7 9.9 - V
VOM- -9.7 -9.85 - V
Supply Current ISUPPLY - 450 1000 µA
Device Dissipation PD-9 14 mW
Input Offset Voltage
Temperature Drift
ΔVIO/ΔT - 4 - µV/°C
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
CA5420A
6FN1925.7
August 18, 2011
Typical Applications
Picoammeter Circuit
The exceptionally low input current (typically 0.2pA) makes the
CA5420A highly suited for use in a picoammeter circuit. With only
a single 10GΩ resistor, this circuit covers the range from ±1.5pA.
Higher current ranges are possible with suitable switching
techniques and current scaling resistors. Input transient protection
is provided by the 1MΩ resistor in series with the input. Higher
current ranges require that this resistor be reduced. The 10MΩ
resistor connected to pin 2 of the CA5420A decouples the
potentially high input capacitance often associated with lower
current circuits and reduces the tendency for the circuit to oscillate
under these conditions.
High Input Resistance Voltmeter
Advantage is taken of the high input impedance of the CA5420A in
a high input resistance DC voltmeter. Only two 1.5V “AA” type penlite
batteries power this exceedingly high-input resistance
(>1,000,000MΩ) DC voltmeter. Full-scale deflection is ±500mV,
±150mV, and ±15mV. Higher voltage ranges are easily added with
external input voltage attenuator networks.
The meter is placed in series with the gain network, thus
eliminating the meter temperature co-efficient error term.
Supply current in the standby position with the meter
undeflected is 300µA. At full-scale deflection this current rises to
800µA. Carbon-zinc battery life should be in excess of 1,000
hours.
3
CA5420A
4
500-0-500
7
+1.5V
5
1
2
-1.5V
10pF
10GΩ
10MΩ1MΩ
BATTERY
RETURNS
10kΩ
6 M
µA
±50pA
±15pA
±5pA
±1.5pA
11kΩ
1.5kΩ
1.5kΩ
1kΩ
430Ω
150Ω
68Ω
1%
-
+
1%
1%
1%
FIGURE 2. PICOAMMETER CIRCUIT
2
CA5420A
4
500-0-500
7
+1.5V
5
1
3
-1.5V
10MΩ22MΩ
BATTERY
RETURNS
10kΩ
6 M
µA
±500mV
±150mV
±50mV
±15mV
1.1kΩ
1.5kΩ
1.5kΩ
1kΩ
430Ω
150Ω
68Ω
1%
-
+
100pF
1%
1%
1%
FIGURE 3. HIGH INPUT RESISTANCE VOLTMETER
Typical Performance Curves
FIGURE 4. OUTPUT VOLTAGE SWING AND COMMON MODE
INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
FIGURE 5. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT
RL = 100kΩ
10
SUPPLY VOLTAGE (V)
15
TA = +25°C
-1.0 510
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
VO+
VICR-
VICR+
VO-
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM THE POSITIVE AND NEGATIVE
SUPPLY VOLTAGE (V)
V+ = 5V
1010.10.001
LOAD (SOURCING) CURRENT (mA)
V- = 0V
TA = +25°C
1000
100
10
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q19 (mV)
V+ = 20V
V+ = 10V
V+ = 2V
CA5420A
7FN1925.7
August 18, 2011
FIGURE 6. OUTPUT VOLTAGE vs LOAD SINKING CURRENT FIGURE 7. SUPPLY CURRENT vs OUTPUT VOLTAGE
FIGURE 8. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 9. INPUT BIAS CURRENT DRIFT (ΔIB/ΔT)
FIGURE 10. INPUT NOISE VOLTAGE vs FREQUENCY FIGURE 11. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
Typical Performance Curves (Continued)
V- = -2V
V- = -5V
V- = -10V
V- = -20V
V+ = 0V
TA = +25°C
1010.10.01
LOAD (SINKING) CURRENT (mA)
10
100
1000
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q17 (mV)
2400
2000
1600
1200
800
400
01 2345
OUTPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
V+ = 5V
V- = GND
5.00
3.75
2.50
1.25
0
0 1 10 100 1000
LOAD RESISTANCE (kΩ)
OUTPUT VOLTAGE SWING (V)
V+ = 5V
TA = +25°C
V- = GND
RL TO GND
800
700
600
500
400
300
200
100
0
25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
V+ = 5V
V- = GND
VS = ±10V
VS = ±5V
VS = ±1V
106
FREQUENCY (Hz)
105
104
103
102
101
1
101
100
1000 TA = +25°C
EQUIVALENT INPUT NOISE VOLTAGE (nV√Hz)
FREQUENCY (Hz)
106
105
104
102
101
110
3
V+ = +10V, V- = 10V
TA =+ 25°C
RL = 10kΩ
CL = 0pF
0
20
40
60
80
100
-180
-135
-90
-45
0
OPEN LOOP VOLTAGE GAIN (dB)
OPEN LOOP PHASE (°)
CA5420A
8
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN1925.7
August 18, 2011
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISLCA5420A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE REVISION CHANGE
07/08/ 2011 FN1925.7 page 1 Features: Change "2V Supply at 300µA....." to "2V Supply at 350µA....."
page 3 Updated Thermal Resistance note for package.
page 3 Electrical Spec Table, V+ = 5V, V- = 0V (lower table): change PSRR min from 75dB to 70dB.
page 4 Electrical Spec Table, V+ = 5V, V- = 0V (upper table) Change Supply Current Vo =0V Max from 500µA to
550µA, and V0 = 2.5V change max from 550µA to 600µA.
page 4 Electrical Spec Table, TA = -55 to +125 V+ = 5V, V- = 0V (lower table) change Supply Current VO=0V Max
from 550µA to 600µA, change Vo=2.5V max from 600uA to 650uA.
page 5 Electrical Spec Table Vsupply =+/-1V (upper table) Common Mode Rejection Ratio, delete 1000uV/V
MAX spec and leave only a typ spec. PSRR change 320uV/V max to 425µV/V max.
page 9 POD M8.15 Updated to new POD format by removing table and moving dimensions onto drawing and
adding land pattern. Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
12/08/2009 FN1925.6 Electrical Specifications Table; TA = 25°C, V+ = 5V, V- = 0V; Change Input Offset Current Max from 0.5pA to 4pA
P3, same table as above; Input Current Max from 1pA to 5pA.
P4: same table as above; Output Voltage VOM+: Minimum spec for RL = Infinity from 4.9V to 4.85V
P5: In Vsupply = +/-1V, Large Signal Voltage Gain spec : Min from 20kV/V to 10kV/V and from 86dB to 80dB
P4; Large Signal Voltage Gain RL = inf; change min to 65dB and typ to75dB (was 85dB Min and 87dB Typ)
Updated Pb-free bullet in Features and Pb-free note in Ordering Information per Mark Kwoka's new verbiage
based on lead finish. Added TB347 link to ordering information for reel specifications. Added MSL link to Order
Info
Updated Caution statement in Abs Max per legal's new verbiage.
Added Pb-Free Reflow link to Thermal Info
Added POD to last page
Added standard Over Temp note to applicable elec spec tables
Corrected Input Offset Current Max from 0.4pA to 4pA
12/21/2005 FN1925.5 Added redline release FGs to ordering information table.
September 1998 FN1925.4 Initial Release
CA5420A
9FN1925.7
August 18, 2011
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/11
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
8°
0°
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
45
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)
