ANALOG DEVICES LC?MOS High Speed jxP-Compatible 8-Bit ADC with Track/Hold Function AD7820 FEATURES Fast Conversion Time: 1.364s max Built-In Track-and-Hold Function No Missed Codes No User Trims Required Single +5V Supply Ratiometric Operation No External Clock Extended Temperature Range Operation Skinny 20-Pin DIP, SOIC and 20-Terminal Surface Mount Packages GENERAL DESCRIPTION The AD7820 is a high speed, microprocessor-compatible 8-bit analog-to-digital converter which uses a half-flash conversion technique to achieve a conversion time of 1.36us. The converter has a OV to +5V analog input voltage range with a single + 5V supply. The half-flash technique consists of 31 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. The input to the AD7820 is tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold for signals with slew rates less than 100mV/ys. The part is designed for ease of microprocessor interface with the AD7820 appearing as a memory location or I/O port without the need for external interfacing logic. All digital outputs use latched, three-state output buffer circuitry to allow direct con- nection to a microprocessor data bus or system input port. A non-three state overflow output is also provided to allow cascading of devices to give higher resolution. The AD7820 is fabricated in an advanced, all ion-implanted, high speed, Linear Compatible CMOS (LC2MOS) process and features a low maximum power dissipation of 75mW. It is available in 20-pin DIPs, SOICs and in 20-terminal surface mount packages. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No licanse is granted by implica tion or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM Vop Veer (+) (12 OFL Vaee() (41 vai DBO-DB7 DATAOUT DRIVERS Vaer( +) % 4-8IT FLASH ADC (4LSB] TIMING AND CONTROL NC CIRCUITRY 7 6 13 8 GNO MoDE WaRDY CS Ro int PRODUCT HIGHLIGHTS 1. Fast Conversion Time The half-flash conversion technique, coupled with fabrication on Analog Devices LC?MOS process, enables very fast con- version times. The maximum conversion time for the WR-RD mode is 1.36us, with 1.6.s the maximum for the RD mode. 2. Total Unadjusted Error The AD7820 features an excellent total unadjusted error figure of less than 1/2LSB over the full operating temperature range. The part is also guaranteed to have no missing codes over the entire temperature range. 3. Built-In Track-and-Hold The analog input circuitry uses sampled-data comparators, which by nature have a built-in track-and-hold function. As a result, input signals with slew rates up to 100mV/us can be converted to 8-bits without external sample-and-hold. This corresponds to a 5V peak-to-peak, 7kHz sine-wave signal. 4, Single Supply Operation from a single +5V supply with a positive voltage reference allows operation of the AD7820 in microprocessor systems without any additional power supplies. One Technology Way, P.O. Box $106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 Telex: 924491 Cable: ANALOG NORWOODMASS eooreorree PINS 2-5, 14-17(Von = +5V; Veer (-+)= + 5V: Vper () = GND = OV unless otherwise stated). AD? 870 SPEC | F| C ATI 0 N S All specifications T,,j, t0 Trax unless otherwise specified. Specifications apply for _ RD Mode (Pin 7 = 0V) Parameter K Version L Version B, T Versions C, U Versions Units Coaditioas/Comments ACCURACY Resolution 8 8 8 8 Bits Total Unadjusted Error +1 +12 +1 +12 LSB max Wain Resolution for which No Missing Codes are guaranteed 8 8 8 8 Bits REFERENCE INPUT Input Resistance 1.0/4.0 1.0/4.0 1.0/4.0 1.0/4.0 kN min/kN max Vrzr( + ) Input Voltage Range Veer (-Vpp Veer (- Vpp VreF(~ YVpp Vrer(- YVpp Vmin/V max Vaer ( ) Input Voltage Range GND/Vrer( +) GND/Vper(+) GND/Vrer(+) GND/Vrer(+) V min/V max ANALOG INPUT Input Voltage Range Vrer( - /Vrer + ) Vrer( - YVrer +) Vrer( - YVeer( +) Vrer( - Vrer +) V min/V max Input Leakage Current +3 +3 +3 +3 vA max Input Capacitance 45 45 45 45 pF yp LOGIC INPUTS CS, WR,RD Vinu 2.4 2.4 2.4 2.4 Vmin Vint 0.8 0.8 0.8 0.8 V max Ina (CS, RD) 1 1 1 1 A max Tnn (WR) 3 3 3 3 pA max line -1 ~1 -1 -1 pA max Input Capacitance? 8 8 8 8 pF max Typically SpF MODE Vinu 3.5 3.5 3.5 3.5 V min Vint 1.5 LS 1.5 L5 V max Inu 200 200 200 200 A max 50 pA typ Iwi -1 -1 -1 -1 pA max Input Capacitance 8 8 8 8 pF max Typically SpF LOGIC OUTPUTS DBO-DB7, OFL, INT Vou 4.0 4.0 4.0 4.0 V min Isource= 360nA Vo. 0.4 0.4 0.4 0.4 Vmax Isivx = 1.6mA lout (DBO-DB7) +3 +3 +3 +3 pA max Floating State Leakage Output Capacitance* 8 8 8 8 pF max Typically SpF RDY Vor 0.4 0.4 0.4 0.4 V max Ign = 2.6mA lout +3 +3 +3 +3 A max Floating State Leakage Ourput Capacitance? 8 8 8g 8 pF max Typically 5pF SLEW RATE, TRACKING? 0.2 0.2 0.2 0.2 Vipstyp 0.1 0.1 0.1 0.1 V/s max POWER SUPPLY Vop 5 5 5 $ Volts + 5% for Specified Performance Ipp* 15 15 20 20 mA max CS=RD=0V Power Dissipation 0 40 ou 0 mW typ Power Supply Sensitivity +4 214 +14 +4 LSB max + VI6LSB typ Vpp =5V +5% NOTES "Temperature Ranges are as follows: K, L Versions: ~ 40C to + 85C B, C Versions: 49C + 88C T, U Versions: $5C to + 125C ?Total Unadjusted Error includes offset, full-scale and linearity errors. Sample tested at 25C by Product Assurance to ensure compliance. See Typical Performance Characteristics. Specifications subject to change without notice. -2- REV. APr AD7820 TIMING CHARACTERISTICS! (,,= +5:Ves(-+)=+5V; Vs ()= END =0V unless otherwise stated) Limit at Limit at Limit at 25C Tino | max Trains D max Parameter (All Versions) (K,L,B,C Versions) (T,U Versions) Units Conditions/Comments less 0 0 0 ns min CS TO RD/WR Setup Time tosH 0 0 0 ns min CS TORD/WR Hold Time trpy 70 90 100 ns max CS to Delay. Pull-Up Resistor 5k. terp 1.6 2.0 2.5 ps max Conversion Time (RD Mode) tacco? tcrp +20 terp +35 tcrp +50 ns max Data Access Time (RD Mode) tyr? 125 - - ns typ RD to INT Delay (RD Mode) 175 225 225 ns max ton 60 80 100 ns max Data Hold Time tp 500 600 600 ns min Delay Time between Conversions twr 600 600 600 ns min Write Pulse Width 50 50 50 jus max tap 600 700 700 ns min Delay Time between WR and RD Pulses tacc? 160 225 250 ns max Data Access Time (WRRD Mode, see Fig. 5b) try 140 200 225 ns max RD toINT Delay trrr2 700 - - ns typ WR toINT Delay 1000 1400 1700 ns max tacc?? 70 90 110 ns max Data Access Time (WR-RD Mode, see Fig. 5a) triwr2 100 130 150 ms max WR to INT Delay (Stand-Alone Operation) tp 50 65 75 ns max Data Access Time after INT (Stand-Alone Operation) NOTES 'Sample tested at 25C to ensure compliance. All input control signals are specified with tr=tf=20ns 2c. = S0pF. 3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. Specifications subject to change without notice. Test Circuits DBN 3k 100pF DGND L a. High-Zto Von 5V 3k. DBN 100pF Ci senw b. High-Zto Vo, Figure 1. Load Circuits for Data Access Time Test REV. A DBN 3kQ DGND b (10% to 90% of +5V) and timed from a voltage level of 1.6V. 10pF a. Vou to High-Z 5V 3k. DBN 10pF Leno b. Vo. to High-Z Figure 2. Load Circuits for Data Hold Time TestAD7820 ABSOLUTE MAXIMUM RATINGS* VpptoGND .......... 0000 ee eee OV, +7V Digital Input Voltage to GND (Pins 6-8, 13) 0 we ek 0,3V, Vop +0.3V Digital Output Voltage to GND (Pins 2-5, 9, 14-18) .......... -0.3V, Vpp +0.3V VREF (+) toGND .......... VREF (-),; Vpp +0.3V Vrer()toGND ............0-. OV, Vrer (+) VmtoGND............... 0.3V, Vpp +0.3V Operating Temperature Range Storage Temperature Range. ........ Lead Temperature (Soldering, 10secs) ........ + 300C Power Dissipation (Any Package) to +75C ..... 450mW Derates above +75C by .........0.2000- 6mW/C *Suresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above Commercial (K, L Versions) Industrial (B, C Versions) Extended (T, U Versions) CAUTION: 40C to + 85C 40C to + 85C 55C to + 125C those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted. WARNING! ar 1 ESD SENSITIVE DEVICE ORDERING GUIDE Total Temperature Unadjusted | Package Model! Range Error(Max) | Option AD7820KN 40Cto + 85C | + 1LSB N-20 AD7820LN 40Cto + 85C | +1/2LSB N-20 AD7820KP 40Cto + 85C | +1LSB P-20A AD7820LP -40Cto +85C | +1/2LSB P-20A AD7820KR 40Cto +85C | +1LSB R-20 AD7820LR 40Cto + 85C | +1/2LSB R-20 AD7820BQ 40C to +85C | +1LSB Q-20 AD7820CQ 40Cto + 85C | +1/2LSB Q-20 AD7820TQ 55C to + 125C | + 1LSB Q-20 AD7820UQ 55Cto + 125C | + 1/2LSB Q-20 AD7820TE 55C to + 125C | + 1LSB E-20A AD7820UE 55C to + 125C | + 1/2LSB E-20A NOTES 'To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet. For U.S. Standard Military Drawing (SMD), see DESC drawing #5962-88650. 2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R =SOIC. PIN CONFIGURATIONS DIP, SOIC LCCC PLCC VS BeBe va [7] [20] Yoo BRS y 6as> 2 32 7 20 48 312] [7 [20] [19 Deo | 2 13] NC ~ oB1 | 3 18] OFL oO DB2 4 18 OFL pp2 (4 he] OFL pee [* [7] 87 IMs DBa 5 17 DB7 {MSB) D ves [5 ap7sz0 [6] Bs _ AD7820 bes [5 AD7820 [17] DB? (MSB) _ TOP VIEW WRIRDY 6 TOP VIEW 16 DBS wrepv [6 TOP VIEW [16] pes WRRDY | 6} (Notto Scale} | 15] DBS MODE 7 (Not to Scale) 15 DBS MODE fF (Not to Scale) Hs] bes move [7 [14] bes AD 8 14 DBS w [a Fa} bes RO [8 13] cS 3 10 11 12 13 INT | 9 12] Vrer (+) lg e777 10} [11]] 12 | - eg~-~- rFavtT GND | 10 11] Vrer t~-) 4 b gEeitie NC=NO CONNECT > > ob t NC=NO CONNECT NC=NO CONNECT > > 4 REV. ANAA Vp = 4.78 1, | J terp- CONVERSION TIME- ps | z i Vop=5.25V - 100 -50 o T,- AMBIENT TEMPERATURE - C Conversion Time {RD Model) vs. Temperature 100 2.0 Vpo =5V Vase =5V 15 Ta= 25C tp=500ns a twa=600ns ! = 10 a z a 0.5 a 200 300 400 500 600 700 800 tan~ ns Accuracy vs. tap SNR- dB 1 2345 7 20 30 4050 70 100 INPUT FREQUENCY - kHz ENCODE RATE = 400kHz INPUT SIGNAL = 5V p-p MEASUREMENT BANDWIDTH = 80kHz 10 Signal-Noise Ratio vs. Input Frequency REV. A 12 2.0 | 4 " Vop=5V Vaer=5 ts eee, . = Ins e 10 5 3 tuo = 600ns z Voo=5.25V = * 2 > (9 5 2 > 1.0 z z & A < 3 8 - Vop=5V 2 a + Von =4.75V| 05 N 7 So PP ee 6 0 -100 50 0 50 100 150 200 300 400 500 600 700 Ta- AMBIENT TEMPERATURE - C. twa- ns. Power Supply Current vs. Temperature Accuracy vs. twr (not including reference ladder} 2.0 20 ] Vpp =5V Ta=25C Von=5V Vrer=5V 15 Ta= 25C 15 a twr=600ns 2 4 tap = 600ns 3 I 5 & 2 wo 10 10 5 E 3 Z N y =} 0.5 ~ 05 sw o 0 300 400 500 600 700 800 900 0 1 2 3 4 5 tpns suse =A Vrer~V Accuracy vs. tp Accuracy vs Vrer [Veer = Vaer(t+) Veer ()] 2.0 10 e Von =5V i S 8 Fe 15 2 iF Vv, =2.4V } Isounce Vout a Voo=4.75V i To & - 6 = 5 J 8 10 Le 4 ae 5 | g e Vpo =5 Von =5.25V 5 4 Pe tz z2 oa = = E Isieaxs Vour= 040 ha # \e AA 3 Z 05 4 u 2 Z 0 o 100 50 o 50 100 150 100 50 0 50 100 150 Ta AMBIENT TEMPERATURE - C T,~ AMBIENT TEMPERATURE C twr_, Internal Time Delay vs. Output Current vs. Temperature Temperature _5-AD7820 PIN FUNCTION DESCRIPTION PIN 1 Ne nub Ww 10 11 12 13 14 15 16 17 18 19 20 MNEMONIC DESCRIPTION Vin DBO DBl DB2 DB3 WR/RDY Mode GND Vrer ) VreK +) DB4 DBS DB6 DB7 OFL NC Vpp Analog Input. Range: Vrrr( ) to Veer +). Data Output. Three State Output, bit 0 (LSB) Data Output. Three State Output, bit 1 Data Output. Three State Output, bit 2 Data Output. Three State Output, bit 3 WRITE control input/READY status output. See Digital Interface section. Mode Selection Input. It determines whether the device operates in the WR-RD or RD mode. It is internally tied to GND through a 50,,A current source. See Digital Interface section. READ Input. RD must be low to access data from the part. See Digital Interface section. INTERRUPT Output. INT going low indicates that the conversion is complete. INT returns high on the rising edge of RD or CS. See Digital Interface section. Ground Lower limit of reference span. Range: GND<Vrer )=Vrer( +) Upper limit of reference span. Range: Veer )= Vrer( + )=Vpp Chip Select Input. CS, the decoded device address, must be low for RD or WR to be recognized by the converter. Data Output. Three State Output, bit 4 Data Output. Three State Output, bit 5 Data Output. Three State Output, bit 6 Data Output. Three State Output, bit 7 (MSB) Overflow Output. If the analog input is higher than (Vper( +) V2LSB), OFL will be low at the end of conversion. It is anon three state output which can be used to cascade 2 or more devices to increase resolution. No connection. Power supply voltage, + 5V CIRCUIT INFORMATION BASIC DESCRIPTION The AD7820 uses a half-flash conversion technique whereby two 4-bit flash A/D converters are used to achieve an 8-bit result. Each 4-bit flash ADC contains 15 comparators which compare the unknown input to a reference ladder to get a 4-bit result. For a full 8-bit reading to be realized, the upper 4-bit flash, the most significant (MS) flash, performs a conversion to provide the 4 most significant data bits. An internal DAC, driven by the 4 MSBs, then recreates an analog approximation of the input voltage. This analog result is subtracted from the input, and the difference is converted by the lower flash ADC, the least significant (LS) flash, to provide the 4 least significant bits of the output data. The MS flash ADC also has one additional comparator to detect input overrange. OPERATING SEQUENCE The operating sequence for the AD7820 in the WR-RD mode is shown in Figure 3. A set-up time of 500ns is required prior to the falling edge of WR. (This 500ns is required between reading data from the AD7820 and starting another conversion). When WR is low the input comparators track the analog input signal, Vin. On the rising edge of WR, the input signal is sampled and the result for the four most significant bits is latched. INT goes low approximately 700ns after the rising edge of WR. This indicates that conversion is complete and the data result is already in the output latch. RD going low then accesses the output data. If a faster conversion time is required, the RD line can be brought low 600ns after WR goes high. This latches the lower 4 bits of data and accesses the output data on DBO-DB7. y INT GOING LOW INDICATES WR THAT CONVERSION IS COMPLETE AND THAT THE DATA RESULTIS ALREADY IN THE OUTPUT 500n: LATCH AND CAN BE READ Vin tS SAMPLED SET-UP TIME REQUIRED AND THE 4MSBS BY THE INTERNAL COMPARATORS PRIOR TO DECISION IS LATCHED STARTING CONVERSION Vix |S TRACKED BY INTERNAL COMPARATORS RD BROUGHT LOW HERE LATCHES THE 4 LSBS INTO OUTPUT LATCH AND ACCESSES DATA ON DB0-DB7 Figure 3. Operating Sequence (WR-RD Mode) REV. ATF AD7820 DIGITAL INTERFACE The AD7820 has two basic interface modes which are determined by the status of the MODE pin. When this pin is low the converter is in the RD mode, with this pin high the AD7820 is set up for the WR-RD mode. RD Mode The timing diagram for the RD mode is shown in Figure 4. In the RD mode configuration, conversion is initiated by taking RD low. The RD line is then kept low until output data appears. It is very useful with microprocessors which can be forced into a WAIT state, with the microprocessor starting a conversion, waiting, and then reading data with a single READ instruction. In this mode, pin 6 of the AD7820 is configured as a status output, RDY. This RDY output can be used to drive the processor READY or WAIT input. It is an open drain output (no internal pull-up device) which goes low after the falling edge of CS and goes high impedance at the end of conversion. An INT line is also provided which goes low at the completion of conversion. INT returns high on the rising edge of CS or RD. cs / _m_o ee = Figure 4. RD Mode WR-RD Mode In the WR-RD mode, pin 6 is configured as the WRITE input for the AD7820. With CS low, conversion is initiated on the falling edge of WR. Two options exist for reading data from the converter. y 7 Figure 5a. WR-RD Mode (tap>tinri) REV. A In the first of these options the processor waits for the INT status line to go low before reading the data (see Figure 5a). INT typically goes low 700ns after the rising edge of WR. It indicates that conversion is complete and that the data result is in the output latch. With CS low, the data outputs (DB0-DB7) are activated when RD goes low. INT is reset by the rising edge of RD or CS. The alternative option can be used to shorten the conversion time. To achieve this, the status of the INT line is ignored and RD can be brought low 600ns after the rising edge of WR. In this case RD going low transfers the data result into the output latch and activates the data outputs (DB0-DB7). INT also goes low on the falling edge of RD and is reset on the rising edge of RD or CS. The timing for this interface is shown in Figure 5b. twr _ | 3 tesm =| f ft _/ tess t te 1 RD + f DB0-087 7 VALID - DATA + pee ome fb jo tacc:o| Figure 5b. WR-RD Mode (tap<ttt) The AD7820 can also be used in stand-alone operation in the WR-RD mode. CS and RD are tied low and a conversion is initiated by bringing WR low. Output data is valid typically 700ns after the rising edge of WR. The timing diagram for this mode is shown in Figure 6. DB0-DB7 Figure 6. WR-RD Mode Stand-Alone Operation, CS=RD=0AD7820 APPLYING THE AD7820 REFERENCE AND INPUT Vin +) J Vin The two reference inputs on the AD7820 are fully differential Vin(-) GND and define the zero to full-scale input range of the A/D converter. y AD7820 As a result, the span of the analog input can easily be varied +5V Vop since this range is equivalent to the voltage difference between | Cl Vaer (+) Vin( +) and Vin(). By reducing the reference span, Vprr(+)- O1mF 3-47HF Veee(-) Vrer( ), to less than 5V the sensivity of the converter can be J L ol increased (i.e., if Var = 2V then 1LSB=7.8mV). The input/refer- ence arrangement also facilitates ratiometric operation. . Figure 7a. Power Supply as Reference This reference flexibility also allows the input span to be offset from zero. The voltage at Vrer() sets the input level which produces a digital output of all zeroes. Therefore, although Vpy is not itself differential, it will have nearly differential-input capability in most measurement applications because of the Vin (+) Vin reference design. Figure 7 shows some of the configurations that Vin (=) se GND are possible. AD7820 +5V ? Voo INPUT CURRENT ~ Yosae Yer 2.5V Due to the novel conversion techniques employed by the AD7820, AD580 Vner{+) the analog input behaves somewhat differently than in conventional JL JL Vert) devices. The ADCs sampled-data comparators take varying vu ner amounts of input current depending on which cycle the conversion sm . . . . Figure 7b. External Reference 2.5V Full-Scale The equivalent input circuit of the AD7820 is shown in Figure 8a. When a conversion starts (WR low, WR-RD mode), all input switches close, and Vpy is connected to the most significant and least significant comparators. Therefore, Vpy is connected to thirty one 1pF input capacitors at the same time. Vin (+) _} Viru The input capacitors must charge to the input voltage through ov GND the on resistance of the analog switches (about 2KN to 5K). In AD7820 addition, about 12pF of input stray capacitance must be charged. +5V T T Voo For large source resistances, the analog input can be modelled O-1uF ATF Veer (+) as an RC network as shown in Figure 8b. As Rg increases, it 2.5V takes longer for the input capacitance to charge. L L Vin(-) . Vrer() In the RD mode, the time for which the input comparators 4 track the analog input is 600ns at the start of conversion. In the i QLLEXISTFROM. WR-RD mode the input comparators track Vpy for the duration V Vaut)TO GROUND. of the WR pulse. Since other factors cause this time to be at least 600ns, input time constants of 100ns can be accommodated Figure 7c. Input Not Referenced to GND without special consideration. Typical total input capacitance values of 45pF allow Rs to be 1.5kQ without lengthening WR to give Viny more time to settle. _g- REV. AAD7820 vl 12pF Ron Vin oT 1pF TOLS om LADDER s pF 15LSB COMPARATORS o 1pF TOMS 1pF LADDER $ Lb P e 16 MSB COMPARATORS Figure 8a. AD7820 Equivalent Input Circuit Rs 350 Vin Cs "yg Figure 8b. RC Network Model 32pF INPUT FILTERING It should be made clear that transients on the analog input signal, caused by charging current flowing into Vpy will not normally degrade the ADCs performance. In effect, the AD7820 does not look at the input when these transients occur. The comparators outputs are not latched while WR is low, so at least 600ns will be provided to charge the ADCs input capacitance. It is therefore not necessary to filter out these transients with an external capacitor at the Vny terminal. INHERENT SAMPLE-HOLD A major benefit of the AD7820s input structure is its ability to measure a variety of high speed signals without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed, the input must remain stable to at least Y4LSB throughout the conversion process if full accuracy is to be maintained. Consequently, for many high speed signals, this signal must be externally sampled and held stationary during the conversion. The AD7820 input comparators, by nature of their input switching inherently accomplish this sample-and-hold function. Although the conversion time for the AD7820 is 1.36, the time through which Vp, must be %LSB stable is much smaller. The AD7820 samples Viy only when WR is low. The value of Vpy approximately 100ns (internal propogation delay) after the rising edge of WR is the measured value. This value is then used in the least significant flash to generate the lower 4-bits of data. Input signals with slew rates typically below 200mV/ys can be converted without error. However, because of the input time constants, and charge injection through the opened comparator input switches, faster signals may cause errors. Still, the AD7820s loss in accuracy for a given increase in signal slope is far less than what would be witnessed in a conventional successive approximation device. A SAR type converter with a conversion time as fast as lus would still not be able to measure a 5V, 1kHz sine wave without the aid of an external sample-and-hold. The AD7820 with no such help, can typically measure 5V, 10kHz waveforms. : Applications +5V Vop INT | | RDY 0.1pF 47pF Vree Vrer (+) cs Vin-4] Vi, AD7820 RD vv Conn MODE DB7 Vari } GND DBO Figure 9a, 8-Bit Resolution REV. A OUTPUT CODE FULL SCALE TRANSITION 11111111 11111110 11111101 | | ? _FS | , ILSB=555 I / l 4 00000011 00000010 00000001 00000000 01LSB 2LSBS 3LSBS AIN, INPUT VOLTAGE (IN TERMS OF LSBS) FS FS -1LSB Figure 9b. Nominal Transfer Characteristic for 8-Bit Resolution CircuitAD7820 +5V Voo cs e- cs 0.1yF 47pF MODE WR 9 WR RO JG t AD7820 55 (| Vee J Veer (+) t 8 DB7 Vin ? Vin Vece(-) DBO DO-D? > 1k 5 GND OFL - 5kO (A +5V Ll MODE WR 7 Ko AD7820 ee] LCH Vaer (+) DB? Vin DBO Vaer() | GND OFL Vin (+4Vp, 3kHz max) +5V bos Figure 10. 9-Bit Resolution 25k -10- Vin cs AD7820* __ Vrer (+) INT Vop DB? | Veer () GND DBO MODE a TTT Vv *SAMPLE RATE IS 20kHz. Figure 11. Telcom A/D Converter REV. AAD7820 CLK ae Vina | Vins wr CS WR Vner GND +15V CS Ap7820 t Vop AD7224 RD RESET Vrer(-) Vout | Vo +5V Vo DB7 DB? t 0.1pF t 47 pF LDAC MODE DBO DBO y AGND Vaer]_ Vree (+) DGND Vss Vina V Vo = Vy; INB _ 5V REF IF Vina<Vrer Figure 12. 8-Bit Analog Multiplier SAMPLE PULSE Vn(ovsosv1 +10V +15V Vin WR +15V Vaer Vpo GND _ , __ RESET Vout - OV TO + 10V 1 cs __ _ AD7820 AD7224 RD Veer (-) cs WR pe7}-__N 87 TDAG wl Lawl. AGND | 0.1pF 47 pF | MODE DBO DBO L DGND L +5V4 Vecr(+) Vss V Figure 13. Fast Infinite Sample-and-Hold <H REV. A -11-AD7820 MECHANICAL INFORMATION OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-PIN CERAMIC! f 0.280 =0.008 (7,37 0.20) 2 4 ee oe eee | 1.000 + 0.010 _/ (25.40 +026) a 0.085 +0.009 bs {4.45) + bios 28a (2.16 0.23] 4 a Rae a A + +6. TYP 0.50 (1.27) TYP 0.900 0.005 (22.86 +0.13) TOL NON ACCUM 6.300 +0.010 {7.82 +0.25) aE ee 0.01078 (0257 30s)l 9 + 8.002 1.001 NOTES. i "LEAD NUMBER + WENTIRED BY OOT OF NOTCH GOLD OR TIN PLATED IN ACCORDANCE WITH Ma sae 0 REQUIREMENTS. 20-PIN CERDIP (SUFFIX Q) wala . u 20-PIN PLASTIC DIP (SUFFIX N) rere rrr rer rrr rrr 1.07 "a? 18), ts ars EReS 0.165 (3.683) Ma a8 | 0.125 2.178) 1 ea ' cet eas aaa toe tt 0.62 (0.5) @.016 (0.41) 7 NOTE Analog Devices reserves the right to ship ceramic packages in lieu of cerdip packages. -12- 6. usta 9.18 (457), .135_{3.429) || 0.125 (3.18), Vis 817, F fig as anal i 009 (0-23) Heal, y LE Is" 0 0.011 (0.28) 0.265 (6.477) 0.245 16.223) C892a-7.5-7/86 PRINTED IN U.S.A. REV. A