TE28F128J3A-150 - Intel - Datasheet.Directory

Intel StrataFlash

Memory (J3)

256-Mbit (x8/x16)

Datasheet

Product Features

Capitalizing on Intel’ s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3)

device provides 2X the bits in 1X the space, with new features for mainstream perf orman ce. Off er ed in 256-

Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-

per- cell storage tech nology to the flash market segment. B enefits include more den sity in less space , high-speed

interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future

devices.

Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes

advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components

are ideal for code and data appl i cations where high density and low cost are required. Examples include

networking, telecommunications, digital set top boxes, audio recording, and digital imaging.

By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from

existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash®

memory (28F640J5 and 28F320J5) devices.

J3 memory components deliver a new generation of forward-compa tible software support. By using the

Common Flash Interface (CFI) and the Sca lable Comma nd Set ( SCS ), cus tomers ca n take advantage of density

upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel®

0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device

provides the highest levels of quality and reliability .

■Performance

—1 10/115/ 120/150 ns Initial Access Speed

—125 ns Initial Access Speed (256 Mbit

density only)

—25 ns Asynchronous Page mode Reads

—30 ns Asynchronous Page mode Reads

(256Mbit density only)

—32-Byte Write Buffer

—6.8 µs per byte effective

programming time

■Software

—Program and Erase suspend support

—Flash Data Integrator (FDI), Common

Flash Interface (CFI) Compatible

■Security

—128-b it Protection Register

—64-bit Unique Device Identifier

—64-bit User Programmable OTP Cells

—Absolute Protection with VPEN = GND

—Individual Block Locking

—Block Erase/Program Lockout during

Power Transitions

■Architecture

—Multi-Level Cell Technology: High

Density at Low Cost

—High-Density Symmetrical 128-Kbyte

Blocks

—256 Mbit (256 Blocks) (0.18µm only)

—128 Mbit (128 Blocks)

—64 Mbit (64 Blocks)

—32 Mbit (32 Blocks)

■Quality and Reliability

—Operating Temperature:

-40 °C to +85 °C

—100K Minimum Erase Cycles per Block

—0.18 µm ETOX™ VII Process (J3C)

—0.25 µm ETOX™ VI Process (J3A)

■Packaging and Voltage

—56-Le ad TSOP Packa ge

—64-Ball Intel® Easy BGA Package

—Lead-free packages available

—48-Ball Intel® VF BGA Pa ck age ( 32 an d

64 Mbit) (x16 only)

—VCC = 2.7 V to 3.6 V

—VCCQ = 2.7 V to 3.6 V

Order Number: 290667-021

Marc h 2005

Notice: This document contains information on new products in production. The specifications are

subject to change without notice. Verify with your local Intel sales office that you have the latest

datasheet before finalizing a design.

2 Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRAN TIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANT ABILITY, OR INFRINGEMENT OF ANY PA TENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or lif e sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to th e m.

The 3 Volt Intel StrataFlash® Memory may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and ETOX are t rademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet 3

Contents

1.0 Introduction....................................................................................................................................7

1.1 Nomenclature .......................................................................................................................7

1.2 Conventions..........................................................................................................................7

2.0 Functional Overview .....................................................................................................................8

2.1 Block Diagram ......................................................................................................................9

2.2 Memory Map.......................................................................................................................10

3.0 Package Information...................................................................................................................11

3.1 56-Lead TSOP Package.....................................................................................................11

3.2 Easy BGA (J3) Package.....................................................................................................12

3.3 VF-BGA (J3) Package........................................................................................................13

4.0 Ballout and Signal Descriptions ................................................................................................14

4.1 Easy BGA Ballout (32/64/128/256 Mbit).............................................................................14

4.2 56-Lead TSOP (32/64/128/256 Mbit)..................................................................................15

4.3 VF BGA Ballout (32 and 64 Mbit) .......................................................................................15

4.4 Signal Descriptions.............................................................................................................16

5.0 Maximum Ratings and Operating Conditions...........................................................................18

5.1 Absolute Maximum Ratings................................................................................................18

5.2 Operating Conditions..........................................................................................................18

6.0 Electrical Specifications.............................................................................................................19

6.1 DC Current Characteristics.................................................................................................19

6.2 DC Voltage Characteristics.................................................................................................20

7.0 AC Characteristics ......................................................................................................................22

7.1 Read Operations.................................................................................................................22

7.2 Write Operations.................................................................................................................26

7.3 Block Erase, Program, and Lock-Bit Configuration Performance.......................................27

7.4 Reset Operation..................................................................................................................29

7.5 AC Test Conditions.................. ........... ........... .......... ........................................... ........... .....29

7.6 Capacitance........................................................................................................................30

8.0 Power and Reset Specifications................................................................................................31

8.1 Power-Up/Down Characteristics.........................................................................................31

8.2 Power Supply Decoupling...................................................................................................31

8.3 Reset Characteristics..........................................................................................................31

9.0 Bus Operations............................................................................................................................32

9.1 Bus Operations Overview...................................................................................................32

9.1.1 Bus Read Operation..............................................................................................33

9.1.2 Bus Write Operation ..............................................................................................33

9.1.3 Output Disable.......................................................................................................33

9.1.4 Standby..................................................................................................................34

9.1.5 Reset/Power-Down................................................................................................34

Contents

4 Datasheet

9.2 Device Commands .............................................................................................................35

10.0 Read Operations..........................................................................................................................37

10.1 Read Array............. ........... .......... ........... ........................................... .......... ........... .............37

10.1.1 Asynchronous Page Mode Read...........................................................................37

10.1.2 Enhanced Configuration Register (ECR)...............................................................38

10.2 Read Identifier Codes............................ ........................................... .......... ........... .............39

10.2.1 Read Status Register........................... ..................................................................39

10.3 Read Query/CFI................ .......... ........... ........... .......................................... ........... .............41

11.0 Programming Operations...........................................................................................................42

11.1 Byte/Word Program............................................................................................................42

11.2 Write to Buffer.....................................................................................................................42

11.3 Program Suspend....................... ........... ........... ..................................................................43

11.4 Program Resume........................ ..................................................................................... ...43

12.0 Erase Operations.........................................................................................................................44

12.1 Block Erase.........................................................................................................................44

12.2 Block Erase Suspend.........................................................................................................44

12.3 Erase Resume....................................................................................................................45

13.0 Security Modes............................................................................................................................46

13.1 Set Block Lock-Bit...............................................................................................................46

13.2 Clear Block Lock-Bits..........................................................................................................46

13.3 Protection Register Program ................. ........... .......................................... ........... ........... ..47

13.3.1 Reading the Protection Register............................................................................47

13.3.2 Programming the Protection Register....................................................................47

13.3.3 Locking the Protection Register.............................................................................47

13.4 Array Protection..................................................................................................................49

14.0 Special Modes..............................................................................................................................50

14.1 Set Read Configuration Register Command ......................................................................50

14.2 Status (STS).......................................................................................................................50

Appendix A Com m on Flash Interface.................................................................................................52

Appendix B Flow Charts......................................................................................................................59

Appendix C Desig n Considerations ...................................................................................................68

Appendix D Additional Inform ation ....................................................................................................70

Appendix E Ordering Information.......................................................................................................71

Datasheet 5

Contents

Revision History

Date of

Revision Version Description

07/07/99 -001 Original Version

08/03/99 -002 A0–A2 indicated on block diagram

09/07/99 -003 Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode

currents. Modified RP# on AC Waveform for Write Operations

12/16/99 -004

Changed Block Erase time and tAVWH

Removed all references to 5 V I/O operation

Corrected O rd e r in g In fo rm at io n , Valid Combinations entries

Changed Min program ti me to 211 µs

Add e d D U to Le a d D e sc riptio ns table

Changed Chip Scale Pa ckage to Ball Grid Array Package

Changed default read mode to page mode

Removed erase queuing from Figure 10, B lock Erase Flowchart

03/16/00 -005

Added Program Max time

Added Erase Max time

Added Max page mode read current

Moved tables to correspond with sections

Fixed typographical errors in ordering information and DC parameter table

Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2

Added recommended resister value for STS pin

Change operation temperature range

Removed note that rp# co uld go to 14 V

Removed VOL of 0.45 V; Removed VOH of 2. 4 V

Updated ICCR Typ values

Added Max lock-bit pro gram and lock times

Added note on max measurements

06/26/00 -006

Updated cove r sheet statement of 700 million units to one billion

Correc ted Table 10 to show corre c t maximum program times

Corrected error in Max block program time in section 6.7

Corre cted typical erase time in section 6.7

2/15/01 -007

Updated cover page to reflect 100K minimum erase cycles

Updated cover page to reflect 110 ns 32M read speed

Removed Set Rea d Configurat ion command from Table 4

Updated Table 8 to re flec t reserved bits are 1-7; not 2-7

Updated Tabl e 16 bit 2 definition from R to PSS

Changed VPENLK Max volta ge from 0.8 V to 2. 0 V, Section 6.4, DC

Characteristics

Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,

AC Characteristics–Read-Only Operations (1,2)

Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC

Characteristic s–Writ e Operations

Updated Max. Pr ogram Suspend Latency W16 (tWHRH1) from 30 to 75 µs,

Sec tion 6. 7, Block Erase, Program, and Lock- Bit Configuration Performance

(1,2,3)

04/13/01 -008 Revis ed Section 7.0, Ordering Information

Contents

6 Datasheet

07/27/01 -009

Adde d Figure 4, 3 Volt Intel StrataFlash® Memory VF BGA Package (32 Mbit)

Adde d Figure 5, 3 Volt Intel StrataFlash® Memory VF BGA Mechanical

Specifications

Updated Operating Tempe rature Range to Extended (Secti on 6.1 and Table 22)

Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns

Adde d parameter values for –40 °C operation to Lock-Bit and Suspend Latency

Updated VLKO an d VPENLK to 2.2 V

Removed Note #4, Section 6.4 and Sect ion 6.6

Minor text edits

10/31/01 -010

Adde d notes under lead descriptions for VF BGA Pa ckage

Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Char acteristics

Removed byte mode read current row un DC characteristics

Adde d ordering information for VF BGA Package

Minor text edits

03/21/02 -011

Changed datasheet to reflect the best known methods

Updated max value for Clear Block Lock-Bits time

Minor text edits

12/ 12/02 -012 Added nomenclature for J3C (0.18 µm) devices.

01/24/03 -013 A dde d 115 ns ac cess speed 6 4 Mb J 3C d evi ce. A dd ed 120 n s a cce ss spe ed 128

Mb J3C device. Added “TE” package designator for J3C TSOP package.

12/09/03 -014 R evised Asynchronous Pa ge Read description. Revi sed Write- to-Buffer flow

char t. Upda ted timing waveforms. Add ed 256-Mbit J3C pinout.

1/3/04 -015 Added 256Mbit device timings, device ID, and CFI information. Also corrected

VLKO spe cifi catio n.

1/23/04 -01 6 Corrected memory block count from 25 7 to 255.

1/23 /04 -016 Memor y block count fix.

5/19/04 -018 Restructured the datas heet layout.

7/7/ 04 -01 9 Added lead-free part numbers and 8-word page information.

11/23/04 -020

Adde d Note to DC V olt age Cha racter isti cs tabl e; “S p eed Bi n” to Read O perati ons

table; Corrected format for AC Waveform for Reset Operation figure; Co rrected

“R” and “8W” he adings in Enhanced Configuration Register table because they

were transposed; Added 802 and 803 to ordering information and corrected 56-

Lead T SOP combination number.

3/24/05 -02 1 Corre cted ordering informat ion.

Date of

Revision Version Description

256-Mbit J3 (x8/x16)

Datasheet 7

1.0 Introduction

This document describes the Intel StrataFlash® Memory (J3) device. It includes a description of

device features, operations, and specifications.

1.1 Nomenclature

AMIN: AMIN = A0 for x8

AMIN = A1 for x16

AMAX: 32 Mbit AMAX = A21

64 Mbit AMAX = A22

128 Mbit AMAX = A23

256 Mbit AMAX = A24

Block: A group of flash cells that share common erase circuitry and erase simultaneously

Clear: Indicates a logic zero (0)

CUI: Command User Interface

MLC: Multi-Level Cell

OTP: One Time Programmable

PLR: Protection Lock Register

PR: Protection Register

PRD Protection Register Data

Program: To write data to the flash array

RFU: Reserved for Future Use

Set: Indicates a logic one (1)

SR: Status Register

SRD: Status Register Data

VPEN: Refers to a signal or package connection name

VPEN:Refers to timing or voltage levels

WSM: Write State Machine

ECR: Extended Configuration Register

XSR: eX t ended Stat us Reg i st er

1.2 Conventions

0x: Hexadecimal prefix

0b: Binary prefix

k (noun): 1,000

M (noun): 1,000,000

Nibble 4 bits

Byte: 8 bits

Word: 16 bits

Kword: 1,024 words

Kb: 1,024 bits

KB: 1,024 bytes

Mb: 1,048,576 bits

MB: 1,048,576 bytes

Brackets: Square brackets ([]) will be used to designate group membership or to define a

group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]).

256-Mbit J3 (x8/x16)

8Datasheet

2.0 Functional Overview

The Intel StrataFlash® memory family contains high-density memories organized as 32 Mbytes or

16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords

(128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These

devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred-

twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixty-

four 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks.

A 128-bit Protection Register has multiple uses, including unique flash device identification.

The device’s optimized architecture and interface dramatically increases read performance by

supporting page-mode reads. This read mode is ideal for non-clock memory systems.

A Common Flash Interface (CFI) permits software algorithms to be used for entire families of

devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-

compatible software support for the specified flash device families. Flash vendors can standardize

their existing interfaces for long-term compatibility.

Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work

with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,

memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest

system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor and

internal operation of the device. A valid command sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM) automatically executes the algorithms and

timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second—

independent of other blocks. Each block can be independently erased 100,000 times. Block erase

suspend mode allows system software to suspend block erase to read or program data from any

other block. Similarly, program suspend allows system software to suspend programming (byte/

word program and write-to-buffer operations) to read data or execute code from any other block

that is not being suspended.

Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming

performance. By using the W rite Buf fer, data is programmed in buffer increments. This feature can

improve system program performance more than 20 times over non-Write Buffer writes.

Blocks are selectively and individually lockable in-system.Individual block locking uses block

lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations.

Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block

Lock-Bits commands).

The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration

operation is finished.

The STS (STATUS) output gives an additional indicator of WSM activity by providing both a

hardware signal of status (versus software polling) and status masking (interrupt masking for

background block erase, for example). Status indication using STS minimizes both CPU overhead

and system power consumption. When configured in level mode (default mode), it acts as a RY/

BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock-

bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is

256-Mbit J3 (x8/x16)

Datasheet 9

suspended (and programming is inactive), program is suspended, or the device is in reset/power-

down mode. Additionally, the configuration command allows the STS signal to be configured to

pulse on completion of programming and/or block erases.

Three CE signals are used to enable and disable the device. A unique CE logic design (see

Table 13, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for

multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-

chip miniature card or SIMM module.

The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit

mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit

operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A

device block diagram is shown in Figure 4 on page 14.

When the device is disabled (see Table 13 on page 33), with CEx at VIH and RP# at VIH, the

standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which

minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is

required from RP# going high until data outputs are valid. Likewise, the device has a wake time

(tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset

and the Status Register is cleared.

2.1 Block Diagram

Figure 1. 3 Volt Intel StrataFlash® Memory Block Diagram

32-Mbit: Thirty-two

64-Mbit: Sixty-four

128-Mbit: One-hundred

twenty-eight

128-Kbyte Blocks

Input Buffer

Output

Latch/Multiplexer

Y-Gating

Program/Erase

Voltage Switch

Data

Comparator

Status

Identifier

Data

I/O Logic

Address

Latch

Address

Counter

X-Decoder

Y-Decoder

In pu t Bu ff er

Output

Buffer

GND

VCC

VPEN

CE0

CE1

CE2

WE#

OE#

RP#

BYTE#

Command

User

Interface

A[MAX:MIN]

D[15:0]

VCC

Write Buffer

Write State

Machine

Multiplexer

Query

STS

VCCQ

Logic

A[2:0]

256-Mbit J3 (x8/x16)

10 Datasheet

2.2 Memory Map

Figure 2. Intel StrataFlash® Memory (J3) Memory Map

64-Kw ord Bloc k

Word Wide (x16) M ode

1FFFFF

1F0000

7FFFFF

7F0000

01FFFF

010000

00FFFF

000000

A[24-1] : 2 56 M bit

A [ 23-1] : 128 M bit

A [ 22-1] : 64 M bit

A [ 21-1] : 32 M bit

128- Kby t e Block

B yt e-W i de (x8) M o de

03FFFFF

03E0000

0FFFFFF

0FE0000

003FFFF

0020000

001FFFF

0000000

A[ 24-0] : 256 M bit

A [ 23- 0] : 128 M bit

A [ 22-0] : 64 M bit

A [ 21-0] : 32 M bit

32-Mbit64-Mbit

64-Kw ord Bloc k

3FFFFF

3F0000

128- Kby t e Block

07FFFFF

07E0000

127

128-Mbit

64-Kw ord Bloc k128- Kby t e Block

FFFFFF

FF0000

1FFFFFF

1FE0000 255 255

256-Mbit

256-Mbit J3 (x8/x16)

Datasheet 11

3.0 Package I n form ation

3.1 56-Lead TSOP Package

Figure 3. 56-Lead TSOP Package Drawing and Specifications

Table 1. 56-Lead TSOP Dimension Table

Millimeters Inches

Sym Min Nom Max Notes Min Nom Max Notes

Packa ge Height A 1.200 0.047

Standoff A10.050 0.002

Package Body Thickness A20.965 0.995 1.025 0.038 0.039 0.040

Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008

Lead Thickness c 0.100 0. 150 0.200 0.004 0.006 0.008

Packa ge Body Length D118.200 18.400 18.600 4 0.717 0.724 0.732 4

Packa ge Body Width E 13.800 14.000 14.200 4 0.543 0.551 0.559 4

Lead P itch e 0.500 0.0197

Terminal D imension D 19.800 20.00 20.200 0.780 0.787 0.795

Lead Tip Lengt h L 0.500 0.600 0.700 0. 020 0.024 0.028

Lead Count N 56 56

Lead Tip Angle ∅0° 3° 5° 0° 3° 5°

Seating Plane Coplanarity Y 0.100 0.004

Lead to Packag e Off s et Z 0.150 0.250 0.350 0.006 0.010 0.014

Detail A

Pin 1

Detail B

See Detail A

See Detail B

Seating

Plane

See Note 2

See Notes 1 and 3

256-Mbit J3 (x8/x16)

12 Datasheet

3.2 Easy BGA (J3) Package

NOTES:

1. For Daisy C hain Evalua tion Unit information refer to the Inte l Flash Memory Packaging Technology Web page at;

www.intel.com/design/packtech/index.htm

2. For Packaging Shipping Media information see www.intel.c om/des ign/packtech/index .htm

Figure 4. Intel StrataFlash® Memory (J3) Easy BGA Mechanical Specifications

Table 2. Easy BGA Package Dimensions

Millimeters Inches

Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.200 0.0472

Ball Height A1 0.250 0.0098

Package Body Thickness A2 0.780 0.0307

Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209

Package Body Width (32 Mb, 64 Mb, 128 Mb, 256 Mb) D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976

Package Body Length (32 Mb, 64 Mb, 128 Mb) E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157

Package Body Length (256 Mb) E 14.900 15.000 15.100 1 0.5866 0.5906 0.5945

Pitch [e] 1.000 0.0394

Ball (Lead) Count N 64 64

Seating Plane Coplanarity Y 0.100 0.0039

Corner to Ball A1 Distance Along D (32/64/128/256 Mb) S1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630

Corner to Ball A1 Distance Along E (32/64/128 Mb) S2 2.900 3. 000 3.100 1 0.1142 0.1181 0.1220

Corner to Ball A1 Distance Along E (256 Mb) S2 3.900 4. 000 4.100 1 0.1535 0.1575 0.1614

Seating

Plane

Top View - Ball side down Bottom View - B al l Side Up

Ball A1

Corner

Note: Dr awing not to scale

87654321

Ball A1

Corner

256-Mbit J3 (x8/x16)

Datasheet 13

3.3 VF-BGA (J3) Package

NOTES:

1. For Daisy Chain Evaluation Unit information r efer to t he Intel Flash Memory Packaging Technology Web

page at; www.intel.com/design/packtech/index.htm

2. For Pac k aging Shipping Media infor m ation refer to the Intel Flash Memory Packa ging Technol ogy Web page

at; www.intel.com/design/packtech/index.htm

Figure 5. Intel StrataFlash® Memory (J3) VF BGA Mechanical Specifications

Seating

Plane

Top V iew - Bum p Side Down Bottom View - Ball Side Up

Ball A1

Corner

Ball A1

Corner

87654321 87654321

Note: Drawing not to scale

Side View

M illimeters Inches

Symbol M in Nom Max

otes Min Nom Max

Pa ckage H eight A 1.000 0.0394

Ball H eig h t A

0.150 0.0059

Package Bod y Thickness A

0.665 0.0262

Ball (Lead) W idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167

D 7.186 7.286 7.386 1 0.2829 0.2868 0.2908

Pa ckage Body L ength E 10.750 10.850 10.950 1 0.4232 0.4272 0.4311

Pitc h [ e ] 0.7 50 0.0 295

Ball (Lead ) C o u n t N 48 48

Se ating Plan e Co planarity Y 0.100 0.0039

Co rn er to B all A 1 Dista nc e A lo n g D S

0.918 1.018 1.118 1 0.0361 0.0401 0.0440

Co rn er to B all A 1 Dista nc e A lo n g E S

3.450 3.550 3.650 1 0.1358 0.1398 0.1437

N ote: (1) Package dimensions are for reference only. These dimensions are estimates based on die size,

and are sub

ect to chan

D imensions Table

256-Mbit J3 (x8/x16)

14 Datasheet

4.0 Ballout and Signal Descriptions

Intel S trataFlash® memory is available in three package types. Each density of the J3C is supported

on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A 48-ball

VF BGA package is available on 32 and 64 Mbit devices. Figure 6, Figure 7, and Figure 8 show the

pinouts.

4.1 Easy BGA Ballout (32/64/128/256 Mbit)

NOTES:

1. Address A2 2 is only valid on 64-Mbi t densities and above, otherwise, it is a no co nnect (N C).

2. Address A2 3 is only valid on 128-Mbit densities and above, other wise, it is a no connect (NC).

3. Address A2 4 is only valid on 256-Mbit densities and above, other wise, it is a no connect (NC).

Figure 6. Intel StrataFlash® Memory Easy BGA Ballout (32/64/128/256 Mbit)

E asy BGA

Top Vie w- Ball side down

234567

CE2# RFU D13VSS D7 A24

256M

VSS

WE#

BYTE# OE#

STS

A4 A5 A11 RFURP# A16 A17RFU

A3 A7 A10 A15A12 A20 A21RFU

A2 VSS A9 A14CEO# A19 CE1#RFU

A1 A6 A8 A13VPEN A18 A22VCC

A23

128M A0 D2 D5VCCQ D14D6

D0 D10 D12D11 RFURFU

D8 D1 D9 D4D3 D15RFU

Easy BGA

Bot tom View- Ball side up

18234567

CE2#RFUD13 VSSD7A24

256M VSS

WE#

BYTE#OE#

STS

A4A5A11RFU RP#A16A17 RFU

A3A7A10A15 A12A20A21 RFU

A2VSSA9A14 CEO#A19CE1# RFU

A1A6A8A13 VPENA18A22 VCC

A23

128M

A0D2D5 VCCQD14 D6

D0D10D12 D11RFU RFU

D8D1D9D4 D3D15 RFU

VCC VCC

256-Mbit J3 (x8/x16)

Datasheet 15

4.2 56-Lead TSOP (32/64/128/256 Mbit)

NOTES:

1. A22 exis ts on 64-, 128- and 256-Mbit densities. O n 32-Mb it densities this signal is a no-connect (NC).

2. A23 exis ts on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC).

3. A24 exis ts on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC).

4. VCC = 5 V ± 10% for the 28F640J5/28 F320J5.

4.3 VF BGA Ballout (32 and 64 Mbit)

NOTES:

1. CE# is equivalent to CE0, and C E1 and CE2 are inter nally grounded.

2. A22 exi s ts on the 64 Mb density only. On the 32-Mbit density, this signal is a no-connect (NC).

3. STS not supported in this package.

4. x8 not sup ported in this package.

Figure 7. Intel StrataFlash® Memory 56-Lead TSOP (32/64/128/256 Mbit)

Highligh ts pinout changes

3 Volt Intel

StrataFlash

Memory

56-Lead TSOP

Standard Pinout

14 mm x 20 mm

Top View

OE#

STS

WE#

GND

CCQ

BYTE#

PEN

RP#

GND

(1)

32/64/128M

3 Volt Intel

StrataFlash

Memory

32/64/128M

3 Volt Intel

StrataFlash

Memory

(2)

(3)

28F320J5

OE#

STS

WE#

GND

CCQ

(4)

BYTE#

28F320J5

GND

PEN

RP#

(4)

28F160S3

RP#

GND

28F160S3

OE#

STS

WE#

GND

WP#

GND

BYTE#

Figure 8. Intel StrataFlash® Memory VF BGA Ballout (32 and 64 Mbit)

VF B GA 6x8

Top View - Ball Side Down

23456781

A12 A9 VPEN VCC A20 A8 A5

A11 WE# RP# A19 A18 A6 A3

A13 A10 A21 A7 A4 A2

D14D5D11D2 D8 CE#

D15 D6 D12 D3 D9 D0 VSS

D7 D13 D4 VCC D10 D1OE#

A22

A14

A15

A16

A17

VCCQ

VSS

VF B GA 6x8

Bottom View - Ball Side Up

23456781

A12A9VPENVCCA20A8A5

A11WE#RP#

A19

A18A6A3

A13

A10A21A7A4A2

D14D5D11

D2D8

CE#

D15D6

D12

D3D9D0VSS

D7D13D4VCCD10D1

OE#

A22

A14

A15

A16

A17

VCCQ

VSS

256-Mbit J3 (x8/x16)

16 Datasheet

4.4 Signal Descriptions

Table 3 describes active signals used.

Table 3. Signal Descriptions (Sheet 1 of 2)

Symbol Type Nam e an d Fu nc tio n

A0 Input BYT E-SE LECT ADDRE SS : Selects between high and low byte when the device is in x8 mode.

This add ress i s l atch ed du ring a x8 p rogr am cy cle. Not u sed i n x16 mo de (i. e. , t he A0 in put buf f er

is turned off when BYTE# is high).

A[MAX:1] Input

ADDRE SS INP UTS : Inputs for addresses during r ead and program operations. Addresses are

internally latched during a pro gram cycle.

32-Mb it: A[21:0]

64-Mb it: A[22:0]

128-Mbit: A[23:0]

256-Mbit: A[24:0]

D[7:0] Input/Output L OW-BYT E DATA BUS: Inputs dat a during buffer writes and progra mming, and inputs

commands du ring CU I writ es. Out pu ts ar ray, C FI, i de ntif ie r, or st at us dat a i n th e a ppro pr iate r ead

mode. Data is internally latched during write operations.

D[15:8] Input/Output HIGH-BYTE DATA BUS: Inputs data duri ng x16 buffer wri tes and progra mming operations.

O ut pu ts arra y, C FI , or id en ti fie r da ta in the app ro pr i at e read mo de ; no t us e d fo r Status Reg is te r

reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode

CE0,

CE1,

CE2 Input

CHIP ENAB LES: Activates the device’s control logic, input buffers, decoders, and sense

amplif ier s. Whe n the d evi ce i s de -sel ect ed (see Table 13 on p a ge 33), power re du ces to standby

levels.

All timing specifications are the same for these three signals. Device selection occurs with the

fir s t edge of CE0, CE 1, or CE2 that enables the device. Device deselection occurs wit h the first

edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33).

RP# Input

RESET/ POWER-DOWN: RP#-l o w resets internal aut omation and pu ts the devic e in power-

down mode. RP#-high enables normal operation. Exit from reset sets the devic e to read array

mode. When driven low, RP# inhibits wri te operations which provides data protection during

power t ransitions.

OE# Input OUTP UT ENAB LE: Activates the device’s outputs through the data buffers during a read cycle.

OE# is active low.

WE# Input WRITE ENA BLE : Controls writes to th e CUI, the Write Buffer, and array blocks. WE # is active

low. Addresses and data are latched on the rising edge of WE#.

STS Open Drain

Output

STATUS: Indicates the status of the internal state machine. When configured in level mode

(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to

indicate program and/or eras e completion . For alternate configurations of the STATUS signal,

see the Configurations command. STS is to be tied to VCCQ with a pull-up resi stor.

BYTE# Input

BYTE ENABLE: BYTE#- low places the device in x8 mode; data is input or output on D[ 7:0],

while D[15: 8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-

high places the device in x16 mode , and turns off the A0 inpu t buffer. Address A1 becomes the

lowest-order address bit.

VPEN Input ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasi ng arra y blocks , pro gramming dat a, or

configuring lock- bits.

With VPEN ≤ VPENLK, memor y contents cannot b e altered.

VCC Power CORE PO WER SUP PLY : Core ( l ogic ) so urce vo l t ag e. Wr i tes t o the fl ash ar ray ar e inhi b ite d

when VCC ≤ VLKO. Device operation at invalid Vcc voltages should not be attempted.

VCCQ Power I/O POWER SUPP LY: I/O Output-driver source voltage. This ball can be tied to VCC.

256-Mbit J3 (x8/x16)

Datasheet 17

GND Supply GROUND: Do not flo a t an y ground si gn a ls .

NC — NO CONNECT: Lead is not inter nally conne cted; it may be driven or float ed.

RFU — RESERVED for F UT URE USE : Balls designated as RFU are reserved by Intel for future device

functionality and enhancement.

Table 3. Signal Descriptions (Sheet 2 of 2)

Symbol Type Name and Function

256-Mbit J3 (x8/x16)

18 Datasheet

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings

This datasheet contains information on new products in production. The specifications are subject

to change without notice. Verify with your local Intel Sales of fice that you have the latest datasheet

before finalizing a design. Absolute maximum ratings are shown in Table 4.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

5.2 Operating Conditions

Table 4. Absolute Maximum Ratings

Parameter Maximum Rating

Temperatur e under Bias Ext ended –40 °C to +85 °C

S torage Temperature –65 °C to +125 °C

Voltage On Any signal –2.0 V to +5.0 V(1)

Output Short Circuit Current 100 mA(2)

NOTES:

1. All specified voltages are with r espect to G ND. Minimum DC voltage is –0.5 V on input/output signals and

–0.2 V on VCC and VPEN signals. During transitions, this level may undershoot to –2.0 V for periods <20

ns. Maximum DC voltage on input/output signals, VCC, and VPEN is VCC +0.5 V which, during transitions,

may overshoot to VCC +2.0 V for pe r i od s <2 0 ns .

2. Output shorted for no more than one second. No more th an one output shorted at a time.

Table 5. Temperature and VCC Operating Conditions

Symbol Parameter Min Max Unit Test Condition

TAOp erating Temperature –40 +85 °C Ambient Temperatur e

VCC VCC1 Supp ly Voltag e (2.7 V−3. 6 V) 2. 70 3.60 V —

VCCQ VCCQ Supply Voltage (2.7 V−3.6 V) 2.70 3.60 V —

256-Mbit J3 (x8/x16)

Datasheet 19

6.0 Electrical S pecifications

6.1 DC Current Characteristics

Table 6. DC Current Characteristics (Sheet 1 of 2)

VCCQ 2.7 - 3.6V

Test Conditions NotesVCC 2.7 - 3.6V

Symbol Parameter Typ Max Unit

ILI Inpu t an d VPEN Load Current ±1µAVCC = VCC Max; VCCQ = VCCQ Max

VIN = VCCQ or GN D 1

ILO Output Leakage Current ±10 µAVCC= VCC Max ; V CCQ = VCCQ Max

VIN = VCCQ or GN D 1

ICCS VCC Standby Current 50 120 µA

CMOS Inputs, VCC = VCC Max,

Device is di sabl ed (see Table 1 3, “Chip Enable

Tru th Table” on page 33),

RP# = VCCQ ± 0. 2 V 1,2,3

0.71 2 mA TTL Inputs, VCC = VCC Max,

Device is disabled (see Table 13), RP# = VIH

ICCD VCC Power -Down Current 50 120 µA RP# = GN D ± 0.2 V, IOUT (STS) = 0 mA

ICCR VCC Page Mode Read

Current

word

Page

15 20 mA

CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ

Max using standard 4 word page mode reads.

Device is enabled (see Table 13)

f = 5 MHz, IOUT = 0 mA

1,3

24 29 mA

CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ

Max using standard 4 word page mode reads.

Device is enabled (see Table 13)

f = 33 MHz , IOUT = 0 mA

word

Page

10 15 mA

• CM OS In pu ts, VCC = VCC Max, VCCQ =

VCCQ Max using standard 8 word page

mode reads.

• Device is enabled (see Ta bl e 13)

f = 5 MHz, IOUT = 0 mA

30 54 mA

• CM OS In pu ts, VCC = VCC Max, VCCQ =

VCCQ Max using standard 8 word page

mode reads.

• Device is enabled (see Ta bl e 13)

f = 33 MHz, IOUT = 0 mA

• Density: 128-, 64-, an d 32- Mbit

26 46 mA

• CM OS In pu ts, VCC = VCC Max, VCCQ =

VCCQ Max using standard 8 word page

mode reads.

• Device is enabled (see Ta bl e 13)

f = 33 MHz, IOUT = 0 mA

• Density: 256Mbit

ICCW VCC Program or Set Lock-

Bit Current 35 60 mA CMOS Input s , VPEN = VCC 1,4

40 70 mA TTL Inputs, VPEN = VCC

256-Mbit J3 (x8/x16)

20 Datasheet

6.2 DC Voltage Characteristics

ICCE VCC Block Erase or Clear

Block Lock-Bits Current 35 70 mA CMOS Inputs, VPEN = VCC 1,4

40 80 mA TTL Inputs, VPEN = VCC

ICCWS

ICCES

VCC Program Suspend or

Bloc k Er ase Suspend

Current 10 mA Device is enabled (see Tabl e 13)1,5

NOTES:

1. All currents are in RMS unless otherwise noted. These currents are valid for all product ver s ions (packages and

speeds). Contact Intel’s Application Suppor t Hotli ne or your local sales office for in formation about ty pical

specifications.

2. Includes S TS.

3. C M OS in p uts are ei th er VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.

4. Sampled, not 100% t ested.

5. ICCWS and ICCES are specified wit h the device sel ected. If the device is read or written while in erase suspend

mode, the device’ s current draw is ICCR and ICCWS

Table 7. DC Voltage Characteristics

Symbol Parameter Min Max Unit Test Conditions Notes

VIL Input Low Voltage –0.5 0.8 V 2, 6

VIH Input High Voltage 2.0 VCCQ

+ 0.5 V2,6

VOL Output Low Voltage 0.4 V VCCQ = VCCQ Min

IOL = 2 mA 1,2

0.2 V VCCQ = VCCQ Min

IOL = 100 µA

VOH Output High Voltage

0.85 ×

VCCQ VVCCQ = VCCQ Min

IOH = –2.5 mA 1,2

VCCQ

– 0.2 VVCCQ = VCCQ Min

IOH = –10 0 µA

VPENLK VPEN Lockout during Program,

Erase and Lock-Bit Operations 2.2 V 2,3,4,7

Table 6. DC Current Characteristics (Sheet 2 of 2)

VCCQ 2.7 - 3.6V

Test Conditions NotesVCC 2.7 - 3.6V

Symbol Parameter Typ Max Unit

256-Mbit J3 (x8/x16)

Datasheet 21

VPENH VPEN during Block Er ase,

Program, or Lock-Bit Operations 2.7 3.6 V 3,4

VLKO VCC Loc ko u t Voltage 2.0 V 5

NOTES:

1. Inc l ud es S TS.

2. Sampled, not 100% tested.

3. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK,

and not guaranteed in the r ange between VPENLK (max) and VPENH (min), and above VPENH

(max).

4. Typically, VPEN is conne c te d to VCC (2.7 V–3.6 V).

5. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and

not guaranteed in the range between VLK O (mi n) and VCC (min), and above VCC (max).

6. Inclu des all opera tional modes of the device including standby and power-up sequences.

7. VCC operating condition for standby has to meet typical operationg coditons.

Table 7. DC Voltage Characteristics

Symbol Parameter Min Max Unit Test Conditions Notes

256-Mbit J3 (x8/x16)

22 Datasheet

7.0 AC C h aracteristics

7.1 Read Operations

Table 8. Read Operations (Sheet 1 of 2)

Asynchronous

Specifications

(All units in ns unless

ot herwise noted)

VCC = 2.7 V–3.6 V (3)

VCCQ = 2.7 V–3.6 V (3 )

Notes

Speed

Bin -110 -115 -120 -125 -150

# Sym Parameter Density Min Max Min Max Min Max Min Max Min Max

R1 tAVAV Read/Write

Cycle Time

32 Mbit 110 1,2

64 Mbit 115 120 1,2

128 Mbit 120 150 1,2

256 Mbit 125 1,2

R2 tAVQV Address to

Output Delay

32 Mbit 110 1,2

64 Mbit 115 120 1,2

128 Mbit 120 150 1,2

256 Mbit 125 1,2

R3 tELQV CEX to Outp ut

Delay

32 Mbit 110 1,2

64 Mbit 115 120 1,2

128 Mbit 120 150 1,2

256 Mbit 125 1,2

R4 tGLQV OE# to Non-

Array Output

Delay 50 50 50 50 50 1,2,4

R5 tPHQV RP# High to

Output Delay

32 Mbit 150 1,2

64 Mbit 180 180 1,2

128 Mbit 210 210 1,2

256 Mbit 210

R6 tELQX CEX to Output in Low Z 0 0 0 0 0 1,2,5

R7 tGLQX OE# to Output in Low Z 0 0 0 0 0 1,2,5

R8 tEHQZ CEX High to Output in High

Z35 35 35 35 35 1,2,5

R9 tGHQZ OE# H igh to Output in High

Z15 15 15 15 15 1,2,5

R10 tOH Output Hold from Address,

CEX, or OE# Change,

Whichever Occurs First 0 0 0 0 0 1,2,5

R11 tELFL/

tELFH CEX Low to BYTE# High or

Low 10 10 10 10 10 1,2,5

256-Mbit J3 (x8/x16)

Datasheet 23

R12 tFLQV/

tFHQV BYTE # to Output Delay 1000 100 0 1000 1000 1000 1,2

R13 tFLQZ BYTE# to Output in High Z 1000 1000 1000 1000 1000 1,2,5

R14 tEHEL CEx High to CEx Low 0 0 0 0 0 1,2,5

R15 tAPA Page Address Ac cess Time 25 25 25 30 25 5, 6

R16 tGLQV OE# to Array Output Delay 25 25 25 25 25 4

NOTES:

CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is

defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13 ).

1. See AC Input/Output R eference Waveforms for the maximum allowable input slew

rate.

2. OE# may be del aye d up to t ELQV-tGLQV afte r t he fi r st e dge of CE0, C E1, or CE 2 that

enables the device (see Tabl e 13) without impact on tELQV.

3. See Figure 15, “Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6

V” on page 29 and Figur e 16, “Transient Equivalent Testing Load Circuit” on

page 30 for testing characteri stic s.

4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to

Status Register reads, query reads, or device identifier reads.

5. Sampled, not 100% tested.

6. For devices configured to standard word/byte r ead mode, R15 (tAPA) will equal R2

(tAVQV).

Figure 9. Single Word Asynchronous Read Waveform

Table 8. Read Operations (Sheet 2 of 2)

Asynchronous

Specifications

(All units in ns unless

otherwise noted)

VCC = 2.7 V–3.6 V (3)

VCCQ = 2.7 V–3.6 V (3)

Notes

Speed

Bin -110 -115 -120 -125 -150

# Sym Parameter Density Min Max Min Max Min Max Min Max Min Max

R11

R12 R13

R10

R16

R8R3

R2 R1

ddress [A]

CE x [ E]

OE# [G]

WE# [W]

Data [D/Q ]

BYTE#[F]

RP# [P]

256-Mbit J3 (x8/x16)

24 Datasheet

0606_16

NOTES:

1. CEX low is defined as the last edge of C E0, CE1, or CE2 that enables the device. CEX high is defined at the

first edge of CE0, CE1, or CE2 that di sables the device (see Table 13).

2. When reading the flash ar ray a faster tGLQV ( R16) app lies. For non- array reads, R4 applies (i.e.: Status

NOTE: CEX low is defi ned as t h e last ed ge o f CE 0, C E1, or CE2 that en abl es the de vic e. CEX high is d efin ed at

the first edge of CE0, CE1, or CE2 that disables the device (see Ta bl e 13 ).

Figure 10. 4-Word Page Mode Read Waveform

00 01 10 11

1 2 3 4

R10

R15

R10

R2 R1

[MAX:3] [A]

A[2:1] [A]

CEx [ E]

OE# [ G]

WE# [W]

D[15:0] [Q]

RP# [P]

256-Mbit J3 (x8/x16)

Datasheet 25

NOTES:

1. CEX low is de fined as the last edge of CE0, C E1, or CE2 that e nables the devic e. CEX high is defined at the

fi rst edge of CE0, CE1, or CE2 that d isables the device (see Table 13).

2. In this diagram, BYTE# is ass erted high.

Figure 11. 8-word Asyn ch ronous Page Mode Read

1 2 6 8

R10

R15

R10

R2 R1

[M AX :4] [A ]

A[3:1] [A]

CEx [E]

OE# [G]

WE# [W]

D[15: 0 ] [Q ]

RP# [ P]

BYTE#

256-Mbit J3 (x8/x16)

26 Datasheet

7.2 Write Operations

Table 9. Write Operations

Versions Valid for All

Speeds Unit Notes

# Symbol Parameter Min Max

W1 tPHWL (tPHEL) RP# Hi gh Recovery to WE# (CEX) Goi n g Lo w 1 µs 1,2,3

W2 tELWL (tWLEL)CE

X (WE#) Lo w to WE# (CEX) Going Low 0 ns 1,2,4

W3 tWP Write Puls e Width 70 ns 1,2,4

W4 tDVWH (tDVEH) Data Setup to WE# (CEX) Going High 50 ns 1,2,5

W5 tAVWH (tAVEH) Address Setup to WE# (CEX) Going High 55 ns 1,2,5

W6 tWHEH (tEHWH)CE

X (WE#) Hold from WE# (CEX) High 0 ns 1,2,

W7 tWHDX (tEHDX) Data Hold from WE# (CEX) High 0 ns 1,2,

W8 tWHAX (tEHAX) Address Hold from WE# (CEX) High 0 ns 1,2,

W9 tWPH Write Pulse Width High 30 ns 1,2,6

W11 tVPWH (tVPEH)V

PEN Se tup to WE# (CEX) Going High 0 ns 1,2,3

W12 tWHGL (tEHGL) Write R eco v er y be fo re Re ad 35 ns 1,2,7

W13 tWHRL (tEHRL)WE# (CE

X) High to S TS G o in g Lo w 500 ns 1,2,8

W15 tQVVL VPEN Hold from Valid SRD, STS Going High 0 ns 1,2,3,8,9

NOTES:

CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1,

or CE2 that disables the device (see Table 13).

1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the s ame as

duri ng r ea d -on ly op erat io ns . Re fe r to AC Characteristics–Read-Only Operations.

2. A write operation can be initiated and terminated with either CEX or WE#.

3. Sampled, not 100% t ested.

4. Write pulse width (tWP) is defined from CEX or WE# going low (whichev er goes low last ) to CEX or WE# going

high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

5. Refer to Table 14 for valid AIN and DIN for block erase, program, or lock-bit configuration.

6. Write pulse w idth high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CE X or WE#

going low (w hichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = t EHWL.

7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.

8. STS timin gs are based on STS configured in its RY/BY# def ault mode.

9. VPEN should be held at VPENH unti l determination of block er ase, program, or loc k -bit configuration success

(SR[1,3,4:5] = 0).

256-Mbit J3 (x8/x16)

Datasheet 27

7.3 Block Erase, Program, and Lock-Bit Configuration

Performance

Table 10. Conf iguration Performance

# Sym Parameter Typ Max(8) Unit Notes

W16 Write Buffer Byte Program Time

(Time to Program 32 bytes/16 words) 218 654 µs 1,2,3,4,5,6,7

W16 tWHQV3

tEHQV3 Byte Prog ram Time (Using Word/Byte Program Comman d) 210 630 µs 1,2,3,4

Bloc k Pr ogram Time (Using Write t o Buffer Command) 0.8 2.4 sec 1,2,3,4

W16 tWHQV4

tEHQV4 Block Erase Time 1.0 5.0 sec 1,2,3,4

W16 tWHQV5

tEHQV5 Set Lock -Bit Time 64 75/85 µs 1,2,3,4,9

W16 tWHQV6

tEHQV6 Clear Block Lock-B its Time 0.5 0.70/1. 4 sec 1,2,3,4,10

W16 tWHRH1

tEHRH1 Program Suspend Latency Time to Read 25 75/90 µs 1,2,3,9

W16 tWHRH

tEHRH Erase Suspend Latency Time to Read 26 35/40 µs 1,2,3,9

NOTES:

1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corr esponding loc k -bits are

not set. Subject to change based on device characterization.

2. These pe rformance numbers are valid for all speed versions.

3. Sampled but not 100% tested.

4. Excludes system-level overhead.

5. These values ar e valid when the buffer is full, and the start address is aligned on a 32 -byte boundary.

6. Effective per-byte program time (tWHQV1, tEHQV1) is 6.8 µs/byte (typical).

7. Effective per- word program time (t WHQV2, tEHQV2) is 13. 6 µs / w ord (typical ) .

8. Max values are measured at worst case temperature and VCC corner after 100k cycles (except as

noted).

9. Max values are expressed at -25 °C/ -40 °C.

10.Max values are expresse d at 25 °C/ -40 °C.

256-Mbit J3 (x8/x16)

28 Datasheet

Figure 12. Asy nc hronous Write Waveform

Figure 13. Asynchronous Write to Read Waveform

W11

W13

W7W4

W9W9W3W3W2

W8W5

ADDRE SS [ A]

CEx (WE#) [E ( W) ]

WE# ( CEx) [W (E)]

OE# [G]

DATA [D/Q]

STS[R]

RP# [ P]

VPEN [ V]

W11

W7W4

W12

W3W3W2

W8W5

Address [A]

CE # [ E]

WE# [W]

OE# [G]

Data [D/Q]

RST#/ RP# [P ]

VPEN [ V]

256-Mbit J3 (x8/x16)

Datasheet 29

7.4 Reset Operation

NOTE: STS is s hown in its default mode (RY/BY#).

7.5 AC Test Conditions

NOTE: AC te st inputs are driv en at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and

out put timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.

Figure 14. AC Waveform for Reset Operation

RP# (P)

STS (R )

Table 11. Reset Specifications

# Sym Parameter Min Max Unit Notes

P1 tPLPH RP# Pulse Low Time

(If RP# is ti ed to VCC, this specification is not

applicable) 35 µs 1,2

P2 tPHRH RP# High to Reset during Block Erase, Program, or

Lock-Bit Configuration 100 ns 1,3

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, program, or lock -bit configurati on operation is not

executing then the minimum requir ed RP# P ulse Low Time is 100 ns.

3. A reset ti me, tPHQV, is requi red from the latter of STS (in RY/BY# mode) or RP # going high until

outpu ts are valid.

Figure 15. Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 V

Outpu

Test PointsInput V

CCQ

0.0

CCQ

256-Mbit J3 (x8/x16)

30 Datasheet

NOTE: CL Inclu des Jig C apacit ance.

7.6 Capacitance

TA = +25 °C, f = 1 MHz

Figure 16. Transient Equivalent Testing Load Circuit

Device

Under Test Ou

= 3.3 k

Ω

1N914

1.3V

Test Configuration CL (pF)

VCCQ = VCC = 2.7 V−3.6 V 30

Symbol Parameter(1) Type Max Unit Condition

CIN Input Capacitance 6 8 pF VIN = 0. 0 V

COUT Output Capacitance 8 12 pF VOUT = 0.0 V

NOTES:

1. Sampled, not 100% tested.

256-Mbit J3 (x8/x16)

Datasheet 31

8.0 Power and Reset S pecifications

This section provides an overview of system level considerations for the Intel StrataFlash®

memory family device. This section provides a brief description of power-up, power-down,

decoupling and reset design considerations.

8.1 Power-Up/Down Characteristics

In order to prevent any condition that may result in a spurious write or erase operation, it is

recommended to power-up and power-down VCC and VCCQ together. It is also recommended to

power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly

before VCC.

8.2 Power Supply Decoupling

When the device is enabled, many internal conditions change. Circuits are energized, charge pumps

are switched on, and internal voltage nodes are ramped. All of this internal activities produce

transient signals. The magnitude of the transient signals depends on the device and system loading.

To minimize the ef fect of these tr ansient signals, a 0.1 µF ceramic capacitor is required across each

VCC/VSS and VCCQ signal. Capacitors should be placed as close as possible to device

connections.

Additionally , for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between

VCC and VSS at the power supply connection. This 4.7 µF capacitor should help overcome

voltage slumps caused by PCB (printed circuit board) trace inductance.

8.3 Reset Characteristics

By holding the flash device in reset during power-up and power-down transitions, invalid bus

conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset,

internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return

from reset, a certain amount of time is required before the flash device is able to perform normal

operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is

driven low during a program or erase operation, the program or erase operation will be aborted and

the memory contents at the aborted block or address are no longer valid. See Figure 14, “AC

Waveform for Reset Operation” on page 29 for detailed information regarding reset timings.

256-Mbit J3 (x8/x16)

32 Datasheet

9.0 Bus Operations

This section provides an overview of device bus operations. The on-chip Write State Machine

(WSM) manages all erase and program algorithms. The system CPU provides control of all in-

system read, write, and erase operations of the device via the system bus.

Device commands are written to the CUI to control all of the flash memory device’s operations.

The CUI does not occupy an addressable memory location; it’s the mechanism through which the

flash device is controlled.

9.1 Bus Operations Overview

The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash

memory conform to standard microprocessor bus cycles.

Table 12. Bus Operations

Mode RP# CE[2:0](1) OE#(2) WE#(2) Address VPEN Data(3) STS

(default

mode) Notes

Read Array VIH Enabled VIL VIH XX D

OUT High Z(7) 4,5,6

Output Disable VIH Enabled VIH VIH X X High Z X

Standby VIH Disabled X X X X High Z X

Reset/Power-Down

Mode VIL X X X X X High Z High Z(7)

Read Identifier Codes VIH Enabled VIL VIH See

Table 17 X Note 8 High Z(7)

Read Q uery VIH Enabled VIL VIH See

Table

10.3 X Note 9 High Z(7)

Read Status (WSM off) VIH Enabled VIL VIH XX D

OUT

Read Status (WSM on) VIH Enabled VIL VIH XX

D7 = DOUT

D[15:8] = High Z

D[6:0] = High Z

Write VIH Enabled VIH VIL XV

PENH DIN X 6,10,11

NOTES:

1. See Table 13 on page 33 for valid C E configurations.

2. OE# and WE# should never be enabled simultaneously.

3. D refers to D[7:0] if BYTE# is lo w and D[ 15:0] if BYTE# is high.

4. Refer to DC Characteristics. When VPEN ≤ VPENLK, memory contents can be read, but not altered.

5. X can be VIL or VIH for control and address signals, and VPENLK or VPENH for VPEN. Se e DC Characteristics for VPENLK and

VPENH voltages.

6. In default mode, STS is VOL when the W SM is exec utin g int ern al blo ck erase , p rogr am, or loc k- bit co nf ig urat io n algor i thms. It

is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or

reset/power-down mode.

7. High Z will be VOH with an ex ternal pull-up resistor.

8. See Section 10.2, “Read Identifier Codes” on page 39 for read identifier code data.

9. See Sect ion 10.3, “Read Query/C FI” on page 41 for read query data.

10.Command writ es i nvolvi ng bloc k erase , prog r am, or l ock-b it confi gur a tion ar e relia bly exec uted w hen VPEN = VPENH and VCC

is within specification.

256-Mbit J3 (x8/x16)

Datasheet 33

9.1.1 Bus Read Operation

To perform a bus read operation, CEx (refer to Table 13 on page 33) and OE# must be asserted.

CEx is the device-select control; when active, it enables the flash memory device. OE# is the data-

output control; when active, the addressed flash memory data is driven onto the I/O bus. For all

read states, WE# and RP# must be de-asserted. See Section 7.1, “Read Operations” on page 22.

Refer to Section 10.0, “Read Operations” on page 37 for details on reading from the flash array,

and re fe r t o Section 14.0, “Special Modes” on page 50 for details regarding all other available read

states.

9.1.2 Bus Write Operation

Writing commands to the Command User Interface enables various modes of operation, including

the reading of array data, CFI data, identifier codes, inspection and clearing of the Status Register,

and, when VPEN = VPENH, block erasure, program, and lock-bit configuration.

The Block Erase command requires appropriate command data and an address within the block to

be erased. The Byte/Word Program command requires the command and address of the location to

be written. Set Block Lock-Bit commands require the command and block within the device to be

locked. The Clear Block Lock-Bits command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when the device is enabled

and WE# is active. The address and data needed to execute a command are latched on the rising

edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 13 on

page 33). Standard microprocessor write timings are used.

9.1.3 Output Disable

With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled. Output

signals D[15:0] are placed in a high-impedance state.

Table 13. Chip Enable Truth Ta ble

CE2 CE1 CE0 DEVICE

VIL VIL VIL Enabled

VIL VIL VIH Disabled

VIL VIH VIL Disabled

VIL VIH VIH Disabled

VIH VIL VIL Enabled

VIH VIL VIH Enabled

VIH VIH VIL Enabled

VIH VIH VIH Disabled

NOTE: For single-chip applications, CE2 and CE1 can be connected to VIL.

256-Mbit J3 (x8/x16)

34 Datasheet

9.1.4 Standby

CE0, CE1, and CE2 can disable the device (see Table 13 on page 33) and place it in standby mode.

This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are

placed in a high-impedance state independent of OE#. If deselected during block erase, program, or

lock-bit configuration, the WSM continues functioning, and consuming active power until the

operation completes.

9.1.5 Reset/Power-Down

RP# at VIL initiates the reset/power-down mode.

In read mod es, RP#-low desel ects the me mory , plac es output dri vers in a high- impedance sta te, and

turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is

required after return from reset mode until initial memory access outputs are valid. After this wake-

up interval, normal operation is restored. The CUI is reset to read array mode and S tatus Register is

set to 0x80.

During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In

default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the

reset operation is complete. Memory contents being altered are no longer valid; the data may be

partially corrupted after a program or partially altered after an erase or lock-bit configuration. T ime

tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash memory. Automated flash memories provide

status information when accessed during block erase, program, or lock-bit configuration modes. If

a CPU reset occurs with no flash memory reset, proper initialization may not occur because the

flash memory may be providing status information instead of array data. Intel StrataFlash®

memory family devices allow proper initialization following a system reset through the use of the

RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system

CPU.

256-Mbit J3 (x8/x16)

Datasheet 35

9.2 Device Commands

When the VPEN voltage ≤ VPENLK, only read operations from the Status Register, CFI, identifier

codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program,

and lock-bit configuration operations. Device operations are selected by writing specific

commands into the CUI. Table 14, “Command Bus-Cycle Definitions” on page 35 defines these

commands.

Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)

Command

Scal able o r

Basic

Command

Set(2)

Bus

Cycles

Req’d.

Fi rst Bus Cycle Second Bus Cycle

Notes

Oper(3) Addr(4) Data(5,6) Oper(3) Addr(4) Data(5,6)

Read Array SCS/BCS 1 Write X 0xFF 1

Read Identifier Codes SCS/BCS ≥ 2 Write X 0X90 Read IA ID 1,7

Read Query SCS ≥ 2 Write X 0x98 Read QA QD 1

Read Status Register SCS/BCS 2 Write X 0x70 Read X SRD 1,8

Cl ea r Status R e gi ster SCS/BC S 1 Write X 0 x 50 1

Write to Buffer SCS/BCS > 2 Write BA 0xE8 Write BA N 1,9, 10,

Word/Byte Program SCS/BCS 2 Write X 0x40 or

0x10 Write PA PD 1,12,13

Block Erase SCS/BCS 2 Write BA 0x20 Write BA 0xD0 1,11,12

Bloc k Er ase, Program

Suspend SCS/BCS 1 Write X 0xB0 1,12,14

Bloc k Er ase, Program

Resume SCS/BCS 1 Write X 0xD0 1,12

Configuration SCS 2 Write X 0xB8 Write X CC 1

Set Block Lock-Bit SCS 2 Write X 0x60 Write BA 0x01 1

256-Mbit J3 (x8/x16)

36 Datasheet

Clear Blo ck Lock-Bits SCS 2 Write X 0x60 Write X 0xD0 1,15

Protec tion Progra m 2 Wri te X 0xC0 Write PA PD 1

NOTES:

1. Commands other than those shown above are rese rved by Intel for future device implementations and should not be used.

2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command S et. The Scalable

Command Set (S CS) is also re ferred to as the Intel Extended Command Set.

3. Bus operat ions are defined in Table 12.

4. X = Any valid address within t he device.

BA = Addr e s s w it hi n th e block .

IA = Identifier Code Address: see Table 17.

QA = Query database Address.

PA = Address of memory location to be programmed.

RCD = Data to be written to the read configuration register . This data is presented to the device on A[16:1]; all other address

inputs are ignored.

5. ID = Data read from Identifi er Codes.

QD = Data re ad from Q uery database.

SRD = Data read from St atus Register. See Table 18 for a description of the Status Register bi ts.

PD = Data to be progr ammed at location PA. Data is latched on the rising edge of WE#.

CC = Configuration Code.

6. The upper byte of the data bus ( D[15:8]) during command writes is a “D on’t Care” in x16 operation.

7. Followi ng the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. S ee

Section 10.2 for read identifier code data.

8. If the WSM is runni ng, only D7 is valid; D [15:8] and D[6:0] float, which p laces them in a high-impedance state.

9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.

10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count a rgument. Count ranges on

thi s device for byte mode are N = 00H to N = 1FH and for word mode are N = 0x00 to N = 0x0 F. The third and consecutive

bus cycles, as determ ined by N, are for writi ng data into th e Write Buffer. Th e Confirm command (0xD0) is expected after

exactly N + 1 write cycles; any other command at that poin t in the sequence aborts the write to buffer operation. See Figure

18, “Writ e to Buffer Fl owcha r t” on page 5 9 for additional information

11.The write to buffer or erase oper ation does not begin until a Confi rm command (0xD0) is issued.

12.Attempts to issue a block erase or program to a locked block.

13.Either 0x40 or 0x10 are recognized by the WSM as the byte/word program setup.

14.Program suspends can be issued after either the Wr ite-to-Buffer or Word/Byte-Program operation is initiated.

15.The clear block lock-bits operation simultaneously clears al l block lock-bits.

Table 14. Command Bus-Cycle Definitions (Sheet 2 of 2)

Command

Scalable or

Basic

Command

Set(2)

Bus

Cycles

Req’d.

First Bus Cycle Second Bus Cycle

Notes

Oper(3) Addr(4) Data(5,6) Oper(3) Addr(4) Data(5,6)

256-Mbit J3 (x8/x16)

Datasheet 37

10.0 Read Operations

The device supports four types of read modes: Read Array, Read Identifier, Read Status, and CFI

query. Upon power-up or return from reset, the device defaults to read array mode. To change the

device’s read mode, the appropriate read-mode command must be written to the device. (See

Section 9.2, “Device Commands” on page 35.) See Section 14.0, “Special Modes” on page 50 for

details regarding read status, read ID, and CFI query modes.

Upon initial device power-up or after exit from reset/power-down mode, the device automatically

resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read

Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control signals dictate the

data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be

enabled (see Table 13, “Chip Enable Truth Table” on page 33), and OE# must be driven active to

obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled

(see Table 13), select the memory device. OE# is the data output (D[15:0]) control and, when

active, drives the selected memory data onto the I/O bus. WE# must be at VIH.

10.1 Read Array

Upon initial device power-up and after exit from reset/power-down mode, the device defaults to

read array mode. The device defaults to four-word asynchronous read page mode. The Read Array

command also causes the device to enter read array mode. The device remains enabled for reads

until another command is written. If the internal WSM has started a block erase, program, or lock-

bit configuration, the device will not recognize the Read Array command until the WSM completes

its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read

Array command functions independently of the VPEN voltage.

10.1.1 Asynchronous Page Mode Read

There are two Asynchronous Page mode configurations that are available depending on the user’s

system design requirements:

•Four-Word Page mode: This is the default mode on power-up or reset. Array data can be

sensed up to four words (8 Bytes) at a time.

•Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a time. This

mode must be enabled on power-up or reset by using the command sequence found in

Table 14, “Command Bus-Cycle Definitions” on page 35. Address bits A[3:1] determine

which word is output during a read operation, and A[3:0] determine which byte is output for a

x8 bus width.

After the initial access delay, the first word out of the page buff er corresponds to the initial address.

In Four-W ord Page mode, address bits A[2:1] determine which word is output from the page buffer

for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus

width. Subsequent reads from the device come from the page buffer. These reads are output on

D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0]

(Four-Word Page mode) or A[3:0] (Eight-Word Page mode) are the only address bits that change.

Data can be read from the page buffer multiple times, and in any order. In Four-Word Page Mode,

if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is

toggled, the device will sense and load new data into the page buffer. Asynchronous Page Mode is

the default read mode on power-up or reset.

256-Mbit J3 (x8/x16)

38 Datasheet

To perform a page mode read after any other operation, the Read Array command must be issued to

read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used

to access register information. During register access, only one word is loaded into the page buffer.

10.1.2 Enhanced Configuration Register (ECR)

The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed to

by the Set Enhanced Configuration Register command, and can select between Four-Word Page

mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when

RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set

Enhanced Configuration Register command. The Set Enhanced Configuration Register command

is written along with the configuration register value, which is placed on the lower 16 bits of the

address bus A[15:0]. This is followed by a second write that confirms the operation and again

presents the enhanced configuration register data on the address bus. After executing this

command, the device returns to Read Array mode. The ECR is shown in Table 15, “Enhanced

Configuration Register” on page 38.

Note: For forward compatibility reasons, if the 8-word Asynchronous Page mode is to be used on J3C, a

Clear Status Register command must be issued after issuing the Set Enhanced Configuration

Definition” on page 38 for further details.

NOTE: Any reserved bits should be set to 0.

NOTE: X = Any valid address within the device. ECD = Enhan ced Configuratio n Register Data.

Table 15. Enhanced Configuration Register

Res. Reserved

RR8WRRRRRRRRRRRRR

ECR

.15 ECR

.14 ECR

.13 ECR

.12 ECR

.11 ECR

.10 ECR

.9 ECR

.8 ECR

.7 ECR

.6 ECR

.5 ECR

.4 ECR

.3 ECR

.2 ECR

.1 ECR

BITS DESCRIPTION NOTES

ECR[15:14] Reserved Reser v ed fo r Fu tu r e Use . Se t to 0 unti l fu r th er

notice.

ECR[13] • “1” = 8W ord Page mode

• “0 ” = 4Word Page mode

ECR[12:0] Reserved Reserv ed fo r Fu tu r e Use . Se t to 0 unti l fu r th er

notice.

Table 16. J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition

Command Bus

Cycles

Req’d.

First Bus Cycle Second Bus Cycle Third Bus Cycle

Oper Addr(1) Data Oper Addr(1) Data Oper Addr(1) Data

Set Enhanced

Configuration Regi ster

(Set ECR) 3 Write ECD 0x60 Write ECD 0x04 Write X 0x50

256-Mbit J3 (x8/x16)

Datasheet 39

10.2 Read Identifier Codes

The Read identifier codes operation outputs the manufacturer code, device-code, and the block

lock configuration codes for each block (See Section 9.2, “Device Commands” on page 35 for

details on issuing the Read Device Identifier command). Page-mode reads are not supported in this

read mode. To terminate the operation, write another valid command. Like the Read Array

command, the Read Identifier Codes command functions independently of the VPEN voltage. This

command is valid only when the WSM is off or the device is suspended. Following the Read

Identifier Codes command, the following information can be read.

10.2.1 Read Status Register

The Status Register may be read to determine when a block erase, program, or lock-bit

configuration is complete and whether the operation completed successfully. It may be read only

after the specified time W12 (see Table 9, “Write Operations” on page 26). After writing this

command, all subsequent read operations output data from the Status Register until another valid

command is written. Page-mode reads are not supported in this read mode. The Status Register

contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables

the device (see Table 13, “Chip Enable Truth Table” on page 33). OE# must toggle to VIH or the

device must be disabled before further reads to update the Status Register latch. The Read Status

During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid

until the Write State Machine completes or suspends the operation. Device I/O signals D[6:0] and

D[15:8] are placed in a high-impedance state. When the operation completes or suspends (check

SR.7), all contents of the Status Register are valid when read.

Table 17. Read Identifier Codes

Code Address(1) Data

Manufacture Code 00000 (00) 89

Device Code 32-Mbit 00001 (00) 16

64-Mbit 0 0001 (00) 17

128-Mbit 00001 (00) 18

256-Mbit 00001 (00) 1D

Block Lock Configuration X0002(2)

• Block Is Unlocked D0 = 0

• Block Is Locked D0 = 1

• Reserv ed for Future Use D[7:1]

NOTES:

1. A0 is not used in either x8 or x16 modes when obtaining the identifier

codes. The low est order address line is A1. Data is always p resented

on the low byte in x16 mode (upper byt e contains 00h).

2. X selects the specifi c block’s lock configuration code.

3. D[7:1 ] are invalid and should be ignored.

256-Mbit J3 (x8/x16)

40 Datasheet

Table 18. Status Register Definitions

WSMS ESS ECLBS PSLBS VPENS PSS DPS R

bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit 1 bit 0

High Z

When

Busy? Status Register Bits Notes

Yes

SR.7 = WRITE STATE MACHINE STAT US

1 = Ready

0 = Bus y

SR.6 = ERASE SUS PEND STATUS

1 = Block Erase Suspended

0 = Block Erase in Progress/C ompleted

SR.5 = ERASE AND CLEAR LOCK-BITS STAT U S

1 = Error in Block Erasure or Clear Lock-Bits

0 = Succe ssful Bl ock Erase or Clear Lock-Bits

SR.4 = PROGRAM AND SET LOCK-BIT STATUS

1 = Program Error / Error in Setting Lock-Bit

0 = Succe ssful Program/Set Block Lock Bit

SR.3 = PROGRAM M ING VOLTAGE STATUS

1 = Low Programming Voltage Detected, Operation

Aborted

0 = Prog r a m m in g Voltage OK

SR.2 = PROGRAM SUSPEND STATUS

1 = Progr am suspended

0 = Progr am in progress/completed

SR.1 = DEVICE PROTECT STATUS

1 = Block Lock-Bit Detected, Operation Abort

0 = Unlo c k

SR0 = RESERVED FOR FUTURE ENHANCEMENTS

Check ST S or SR.7 to determi ne blo ck erase,

program, or lock-bit configuration completion.

SR[6:0] are not dr iven while SR .7 = “0.”

If both SR.5 and SR.4 are “1”s after a block erase or

lock-bit confi guration attempt, an improper

command sequence was ent ered.

SR.3 does not provide a continuous programming

voltage level indication. The WSM interrogates and

indicates the programming vol tage level only after

Block E rase, Program, Set Block Lock-Bit, or Clear

Block Lock-Bits command sequences.

SR.1 does not provide a continuous indication of

block lock-bit values. The WSM interrogates the

block lock-bits only after Block Erase, Program, or

Lock-Bit configuration command sequences. It

informs the system, depending on the attempted

operation, if the block lock-bit is set. Read the block

lock configuration codes using the Read I dentifier

Codes command to determine block lock-bit s tatus.

SR0 is reser v ed for futur e use and should be

masked when polling the Status Register.

Table 19. Extended Status Register Definitions

WBS Reserved

bit 7 Bits 6 -- 0

High Z

When

Busy? Status Register Bits Notes

Yes

XSR.7 = WRITE BUFFER STATUS

1 = Write buffer available

0 = Write buffer not available

XSR.6–XSR0 = RESERVED FOR FUTURE

ENHANCEMENTS

Aft er a Buffer- Wri te co mm a n d, XSR. 7 = 1 indicat es

that a Write Buffer is available.

SR[6: 0] are reserved for future use and should be

masked when polling t he Status Register.

256-Mbit J3 (x8/x16)

Datasheet 41

10.3 Read Query/CFI

The query register contains an assortment of flash product information such as block size, density,

allowable command sets, electrical specifications and other product information. The data

contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any

information from the query register, execute the Read Query Register command. See Section 9.2,

“Device Commands” on page 35 for details on issuing the CFI Query command. Refer to

Appendix A, “Query Structure Overview” on page 53 for a detailed explanation of the CFI register .

Information contained in this register can only be accessed by executing a single-word read.

256-Mbit J3 (x8/x16)

42 Datasheet

11.0 Programming Operations

The device supports two different programming methods: word programming, and write-buffer

programming. Successful programming requires the addressed block to be unlocked. An attempt to

program a locked block will result in the operation aborting, and SR.1 and SR.4 being set,

indicating a programming error. The following sections describe device programming in detail.

11.1 Byte/Word Program

Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup

(standard 0x40 or alternate 0x10) is written followed by a second write that specifies the address

and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program

and program verify algorithms internally. After the program sequence is written, the device

automatically outputs SRD when read (see Figure 20, “Byte/Word Program Flowchart” on

page 61). The CPU can detect the completion of the program event by analyzing the STS signal or

SR.7.

When program is complete, SR.4 should be checked. If a program error is detected, the Status

successfully program to “0”s. The CUI remains in Read Status Register mode until it receives

another command.

Reliable byte/word programming can only occur when VCC and VPEN are valid. If a byte/word

program is attempted while VPEN ≤ VPENLK, SR.4 and SR.3 will be set. Successful byte/word

programs require that the corresponding block lock-bit be cleared. If a byte/word program is

attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.

11.2 Write to Buffer

To program the flash device, a Write to Buffer command sequence is initiated. A variable number

of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the

Write to Buffer Setup command is issued along with the Block Address (see Figure 18, “Write to

Buffer Flowchart” on page 59). At this point, the eXtended Status Register (XSR, see Table 19)

information is loaded and XSR.7 reverts to “buffer available” status. If XSR.7 = 0, the write buffer

is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup

command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is

ready for loading.

Next, a word/byte count is given to the part with the Block Address. On the next write, a device

start address is given along with the write buffer data. Subsequent writes provide additional device

addresses and data, depending on the count. All subsequent addresses must lie within the start

address plus the count.

Internally, this device programs many flash cells in parallel. Because of this parallel programming,

maximum programming performance and lower power are obtained by aligning the start address at

the beginning of a write buffer boundary (i.e., A[4:0] of the start address = 0).

256-Mbit J3 (x8/x16)

Datasheet 43

After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM

(Write State Machine) to begin copying the buffer data to the flash array. If a command other than

Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated

and SR.5 and SR.4 will be set. For additional buffer writes, issue another Write to Buffer Setup

command and check XSR.7.

If an error occurs while writing, the device will stop writing, and SR.4 will be set to indicate a

program failure. The internal WSM verify only detects errors for “1”s that do not successfully

program to “0”s. If a program error is detected, the Status Register should be cleared. Any time

SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an erase), the device will

not accept any more Write to Buffer commands. Additionally, if the user attempts to program past

an erase block boundary with a Write to Buffer command, the device will abort the write to buffer

operation. This will generate an “Invalid Command/Sequence” error and SR.5 and SR.4 will be set.

Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted

while VPEN ≤ VPENLK, SR.4 and SR.3 will be set. Buffered write attempts with invalid VCC and

VPEN voltages produce spurious results and should not be attempted. Finally, successful

programming requires that the corresponding block lock-bit be reset. If a buffered write is

attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.

11.3 Program Suspend

The Program Suspend command allows program interruption to read data in other flash memory

locations. Once the programming process starts (either by initiating a write to buffer or byte/word

program operation), writing the Program Suspend command requests that the WSM suspend the

program sequence at a predetermined point in the algorithm. The device continues to output SRD

when read after the Program Suspend command is written. Polling SR.7 can determine when the

programming operation has been suspended. When SR.7 = 1, SR.2 should also be set, indicating

that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to

VOH. Specification tWHRH1 defines the program suspend latency.

At this point, a Read Array command can be written to read data from locations other than that

which is suspended. The only other valid commands while programming is suspended are Read

Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a

Program Resume command is written, the WSM will continue the programming process. SR.2 and

SR.7 will automatically clear and STS in RY/BY# mode will return to VOL. After the Program

Resume command is written, the device automatically outputs SRD when read. VPEN must remain

at VPENH and VCC must remain at valid VCC levels (the same VPEN and VCC levels used for

programming) while in program suspend mode. Refer to Figure 21, “Program Suspend/Resume

Flowchart” on page 62.

11.4 Program Resume

To resume (i.e., continue) a program suspend operation, execute the Program Resume command.

The Resume command can be written to any device address. When a program operation is nested

within an erase suspend operation and the Program Suspend command is issued, the device will

suspend the program operation. When the Resume command is issued, the device will resume and

complete the program operation. Once the nested program operation is completed, an additional

Resume command is required to complete the block erase operation. The device supports a

maximum suspend/resume of two nested routines. See Figure 21, “Program Suspend/Resume

Flowchart” on page 62).

256-Mbit J3 (x8/x16)

44 Datasheet

12.0 Erase Operati ons

Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once

a block is erased, all bits within that block will read as a logic level one. To determine the status of

a block erase, poll the Status Register and analyze the bits. This following section describes block

erase operations in detail.

12.1 Block Erase

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is

first written, followed by an block erase confirm. This command sequence requires an appropriate

address within the block to be erased (erase changes all block data to FFH). Block preconditioning,

erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle

block erase sequence is written, the device automatically outputs SRD when read (see Figure 22,

“Block Erase Flowchart” on page 63). The CPU can detect block erase completion by analyzing

the output of the STS signal or SR.7. Toggle OE#, CE0, CE1, or CE2 to update the Status Register.

When the block erase is complete, SR.5 should be checked. If a block erase error is detected, the

Status Register should be cleared before system software attempts corrective actions. The CUI

remains in Read Status Register mode until a new command is issued.

This two-step command sequence of setup followed by execution ensures that block contents are

not accidentally erased. An invalid Block Erase command sequence will result in both SR.4 and

SR.5 being set. Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH.

If block erase is attempted while VPEN ≤ VPENLK, SR.3 and SR.5 will be set. Successful block

erase requires that the corresponding block lock-bit be cleared. If block erase is attempted when the

corresponding block lock-bit is set, SR.1 and SR.5 will be set.

12.2 Block Erase Suspend

The Block Erase Suspend command allows block-erase interruption to read or program data in

another block of memory. Once the block erase process starts, writing the Block Erase Suspend

comma nd r eq ues ts tha t t he WSM susp end the bloc k er ase se q uen ce at a pr edete rm in ed p oi nt in th e

algorithm. The device outputs SRD when read after the Block Erase Suspend command is written.

Polling SR.7 then SR.6 can determine when the block erase operation has been suspended (both

will be set). In default mode, STS will also transition to VOH. Specification tWHRH defines the

block erase suspend latency.

At this point, a Read Array command can be written to read data from blocks other than that which

is suspended. A program command sequence can also be issued during erase suspend to program

data in other blocks. During a program operation with block erase suspended, SR.7 will return to

“0” and STS output (in default mode) will transition to VOL. However, SR.6 will remain “1” to

indicate block erase suspend status. Using the Program Suspend command, a program operation

can also be suspended. Resuming a suspended programming operation by issuing the Program

Resume command allows continuing of the suspended programming operation. To resume the

suspended erase, the user must wait for the programming operation to complete before issuing the

Block Erase Resume command.

256-Mbit J3 (x8/x16)

Datasheet 45

The only other valid commands while block erase is suspended are Read Query, Read Status

command is written to the flash memory, the WSM will continue the block erase process. SR.6 and

SR.7 will automatically clear and STS (in default mode) will return to VOL. After the Erase

Resume command is written, the device automatically outputs SRD when read (see Figure 23,

“Block Erase Suspend/Resume Flowchart” on page 64). VPEN must remain at VPENH (the same

VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until

program operations initiated during block erase suspend have completed.

12.3 Erase Resume

To resume (i.e., continue) an erase suspend operation, execute the Erase Resume command. The

Resume command can be written to any device address. When a program operation is nested

within an erase suspend operation and the Program Suspend command is issued, the device will

suspend the program operation. When the Resume command is issued, the device will resume the

program operations first. Once the nested program operation is completed, an additional Resume

command is required to complete the block erase operation. The device supports a maximum

suspend/resume of two nested routines. See Figure 22, “Block Erase Flowchart” on page 63.

256-Mbit J3 (x8/x16)

46 Datasheet

13.0 Security Modes

This device offers both hardware and software security features. Block lock operations, PRs, and

VPEN allow the user to implement various levels of data protection. The following section

describes security features in detail.

Other security features are available that are not described in this datasheet. Please contact your

local Intel Field Representative for more information.

13.1 Set Block Lock-Bit

A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program

and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command.

This command is invalid while the WSM is running or the device is suspended.

Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with

appropriate block address is followed by either the set block lock-bit confirm (and an address

within the block to be locked). The WSM then controls the set lock-bit algorithm. After the

sequence is written, the device automatically outputs Status Register data when read (see Figure 24

on page 65). The CPU can detect the completion of the set lock-bit event by analyzing the STS

signal output or SR.7.

When the set lock-bit operation is complete, SR.4 should be checked. If an error is detected, the

Status Register should be cleared. The CUI will remain in Read Status Register mode until a new

command is issued.

This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally

set. An invalid Set Block Lock-Bit command will result in SR.4 and SR.5 being set. Also, reliable

operations occur only when VCC and VPEN are valid. With VPEN ≤ VPENLK, lock-bit contents are

protected against alteration.

13.2 Clear Block Lock-Bits

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock-

bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while

the WSM is running or the device is suspended.

Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup

is first written. The device automatically outputs Status Register data when read (see Figure 25 on

page 66). The CPU can detect completion of the clear block lock-bits event by analyzing the STS

signal output or SR.7.

When the operation is complete, SR.5 should be checked. If a clear block lock-bit error is detected,

the Status Register should be cleared. The CUI will remain in Read Status Register mode until

another command is issued.

256-Mbit J3 (x8/x16)

Datasheet 47

This two-step sequence of setup followed by execution ensures that block lock-bits are not

accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR.4 and

SR.5 being set. Also, a reliable clear block lock-bits operation can only occur when VCC and VPEN

are valid. If a clear block lock-bits operation is attempted while VPEN ≤ VPENLK, SR.3 and SR.5

will be set.

If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range,

block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required

to initialize block lock-bit contents to known values.

13.3 Protection Register Program

The Intel StrataFlash® memory (J3) includes a 128-bit Protection Register (PR) that can be used to

increase the security of a system design. For example, the number contained in the PR can be used

to “mate” the flash component with other system components such as the CPU or ASIC, preventing

device substitution.

The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at

the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank

for customer designers to program as desired. Once the customer segment is programmed, it can be

locked to prevent further programming.

13.3.1 Readi ng the Protection Register

The Protection Register is read in the identification read mode. The device is switched to this mode

by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses

shown in Table 8 or Table 21 retrieve the specified information. To return to read array mode, write

the Read Array command (0xFF).

13.3.2 Programming the Protection Register

Protection Register bits are programmed using the two-cycle Protection Program command. The

64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time

for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next

write to the device will latch in address and data and program the specified location. The allowable

addresses are shown in Table 8 or Table 21. See Figure 26, “Protection Register Programming

Flowchart” on page 67

Any attempt to address Protection Program commands outside the defined PR address space will

result in a Status Register error (SR.4 will be set). Attempting to program a locked PR segment will

result in a Status Register error (SR.4 and SR.1 will be set).

13.3.3 Locking the Protection Register

The user-programmable segment of the Protection Register is lockable by programming Bit 1 of

the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique

device number. Bit 1 is set using the Protection Program command to program “0xFFFD” to the

PLR. After these bits have been programmed, no further changes can be made to the values stored

in the Protection Register. Protection Program commands to a locked section will result in a Status

256-Mbit J3 (x8/x16)

48 Datasheet

NOTE: A0 is not used in x16 mode when accessing the Protection R egister map (See Table 8 for x16

addressing). For x8 mode A0 is used (See Table 21 for x8 addressing).

Figure 17. Protection Register Memory Map

0x88

0x85

64-bit Segment

(User-Programmable)

0x84

0x81

0x80 Lock Register 0

64-bit Segment

(Factory-Programmed)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

128-Bit Protection Register 0

Word

Address A[23:1]: 128 Mbit A[21:1]: 32 Mbit

A[22:1]: 64 MbitA[24:1]: 256 Mbit

Table 20. Word-Wide Protection Register Addressing

WordUseA8A7A6A5A4A3A2A1

LOCKBoth10000000

0Factory10000001

1Factory10000010

2Factory10000011

3Factory10000100

4User10000101

5User10000110

6User10000111

7User10001000

Table 21. Byte-Wide Protection Register Addressing (Sheet 1 of 2)

ByteUseA8A7A6A5A4A3A2A1A0

LOCKBoth100000000

LOCKBoth100000001

0Factory100000010

1Factory100000011

2Factory100000100

3Factory100000101

4Factory100000110

5Factory100000111

256-Mbit J3 (x8/x16)

Datasheet 49

13.4 Array Protection

The VPEN signal is a hardware mechanism to prohibit array alteration. When the VPEN voltage is

below the VPENLK voltage, array contents cannot be altered. To ensure a proper erase or program

operation, VPEN must be set to a valid voltage level. To determine the status of an erase or program

operation, poll the Status Register and analyze the bits.

6Factory100001000

7Factory100001001

8User100001010

9User100001011

AUser100001100

BUser100001101

CUser100001110

DUser100001111

EUser100010000

FUser100010001

NOTE: All add r ess li ne s n ot sp eci fi ed in t he ab ove table must b e 0 whe n a cces sin g th e P rot ect ion R egist er,

i.e.g., A[MAX:9] = 0.

Table 21. Byte-Wide Protection Register Addressing (Sheet 2 of 2)

256-Mbit J3 (x8/x16)

50 Datasheet

14.0 S pe c ia l Modes

This section describes how to read the status, ID, and CFI registers. This section also details how to

configure the STS signal.

14.1 Set Read Configuration Register Command

This command is no longer supported on J3A or J3C. The J3A device will ignore this command,

while the J3C device will result in an invalid command sequence (SR.4 and SR.5 =1).

14.2 Status (STS)

The Status (STS) signal can be configured to different states using the Configuration command.

Once the STS signal has been configured, it remains in that configuration until another

configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/

BY# operation where R Y/BY# low indicates that the WSM is busy . RY/BY# high indicates that the

state machine is ready for a new operation or suspended. Table 22, “STS Configuration Coding

Definitions” on page 50 displays the possible STS configurations.

To reconfigure the Status (STS) signal to other modes, the Configuration command is given

followed by the desired configuration code. The three alternate configurations are all pulse mode

for use as a system interrupt as described below. For these configurations, bit 0 controls Erase

Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00

configuration code with the Configuration command resets the STS signal to the default RY/BY#

level mode. The possible configurations and their usage are described in Table 22, “STS

Configuration Coding Definitions” on page 50. The Configuration command may only be given

when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration

code will result in both SR.4 and SR.5 being set. When configured in one of the pulse modes, the

STS signal pulses low with a typical pulse width of 250 ns.

Table 22. STS Configuration Coding Definitions

D7 D6 D5 D4 D3 D2 D1 D0

Reserved

Pulse on

Program

Complete

(1)

Puls e on

Erase

Complete

(1)

D[1:0] = STS Configuration Codes Notes

00 = default, level mode;

device ready indication Used to control HOLD to a memory controller to prevent accessing a

flash memory subsystem while any flash device's WSM is busy.

01 = pulse on Erase Complete Used to generate a system interrupt pulse when any flash device in

an array has completed a block erase. Helpful for reformatting blocks

after file system free space reclamation or “cleanup.”

256-Mbit J3 (x8/x16)

Datasheet 51

10 = pulse on Program Complete Used to generate a system interrupt pulse when any flash device in

an array has completed a program operation. Provides highest

performance for servicing continuous buffer write operations.

11 = pulse on Erase or Program

Complete Used to generate system interrupts to trigger servicing of flash arrays

when either erase or program operations are completed, when a

common interrupt service routine is desired.

NOTES:

1. When con figured in one of the pulse modes, STS pulses low with a typical puls e width of 250 ns.

2. An invalid configuration code will r esult in both SR .4 and SR .5 being set.

Table 22. ST S Configuration Coding Definitions

D7 D6 D5 D4 D3 D2 D1 D0

Reserved

Pulse on

Program

Complete

(1)

Pulse on

Erase

Complete

(1)

D[1:0] = STS Configuration Codes Notes

256-Mbit J3 (x8/x16)

52 Datasheet

Appendix A Common Flash Interface

The Common Flash Interface (CFI) specification outlines device and host system software

interrogation handshake which allows specific vendor-specified software algorithms to be used for

entire families of devices. This allows device independent, JEDEC ID-independent, and forward-

and backward-compatible software support for the specified flash device families. It allows flash

vendors to standardize their existing interfaces for long-term compatibility.

This appendix defines the data structure or “database” returned by the Common Flash Interface

(CFI) Query command. System software should parse this structure to gain critical information

such as block size, density, x8/x16, and electrical specifications. Once this information has been

obtained, the software will know which command sets to use to enable flash writes, block erases,

and otherwise control the flash component. The Query command is part of an overall specification

for multiple command set and control interface descriptions called Common Flash Interface, or

CFI.

A.1 Query Structure Output

The Query “database” allows system software to gain information for controlling the flash

component. This section describes the device’ s CF I-compliant interface that allows the host system

to access Query data.

Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical

offset value is the address relative to the maximum bus width supported by the device. On this

family of devices, the Query table device starting address is a 10h, which is a word address for x16

devices.

For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,

appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H

data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (D[7:0]) and 0x00 (00h)

in the high byte (D[15:8]).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always

“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is

shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

256-Mbit J3 (x8/x16)

Datasheet 53

A.2 Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)

Query structure or “database.” The structure sub-sections and address locations are summarized

below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for

a full description of CFI commands.

The following sections describe the Query structure sub-sections in detail.

Table 23. Summary of Query Structure Output as a Function of De vice and Mod e

Device

Type/

Mode

Query s t art l ocati on in

maximum device bus

width addresses

Quer y data with maximum

device bus width addressing Query data with byte

addressing

Hex

Offset Hex

Code ASCII

Value Hex

Offset Hex

Code ASCII

Value

x16 device 10 h 10: 0051 “Q” 20: 51 “Q”

x16 mode 11: 0052 “R” 21: 00 “Null”

12: 0059 “Y” 22: 52 “R”

x16 device 20: 51 “Q”

x8 mode N/A(1) N/A(1) 21: 51 “Q”

22: 52 “R”

NOTE:

1. The s ystem must drive the lowest order addresses to access all the device' s array data when the device is

configure d in x8 mode. Ther efore, word addressing, where these lower ad dresses are not toggled by the

system, is "Not Applicable" for x8-config ured devices.

Table 24. Example of Query Structure Output of a x16- and x8-Capable Device

Word Addressing Byte Addressing

Offset Hex Code Va lue Offset Hex Code Value

A15–A0 D15–D0A7–A0 D7–D0

0010h 0051 “Q” 20h 51 “Q”

0011h 0052 “R” 21h 51 “Q”

0012h 0059 “Y” 22h 52 “R”

0013h P_IDLO PrVendor 23h 52 “R”

0014h P_IDHI ID # 24h 59 “ Y”

0015h PLO PrVendor 25h 59 “Y”

0016h PHI TblAdr 26h P_IDLO PrVendor

0017h A_IDLO AltVendor 27h P_IDLO ID #

0018h A_IDHI ID # 28 h P_IDHI ID #

... ... ... ... ... ...

256-Mbit J3 (x8/x16)

54 Datasheet

A.3 Block Status Register

The bl oc k sta tus re g is ter ind ica t es wh et he r an era se o pe ra tio n com pl ete d succ es sf ully or whethe r a

given block is locked or can be accessed for flash program/erase operations.

A.4 CFI Query Identification String

The CFI Query Identification String provides verification that the component supports the

Common Flash Interface specification. It also indicates the specification version and supported

vendor-specified command set(s).

Table 25. Query Structure

Offset Sub-Section Name Description Notes

00h Manufacturer Code 1

01h Device Code 1

(BA+2)h(2) Block Status Register Block-Specific Information 1,2

04-0Fh Reserved Reserved for Vendor-Specific Information 1

10h CFI Query Identification String Reserved for Vendor- Specific Information 1

1Bh System Interfac e Informati on Command S et ID and Vendor Data Offset 1

27h Device Geom etry De finition Flash Device Layout 1

P(3) Primary Intel-Specific Extended

Query Table Vendor-Defined Additional Informat ion

S pecific to the Primary Vendor Algorithm 1,3

NOTES:

1. Refer to the Query Structure Output section and offset 28h for t he detailed definition of offset

address as a function of device bus width and mode.

2. BA = Block Address beginning location (i.e. , 02000h is block 2’s beginning loc ation when the

block size is 128 Kbyt e).

3. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.

Table 26. Block Status Register

Offset Length Description Address Value

(BA+2)h(1) 1 Block Loc k Status Reg ister BA+2: --00 or --01

BSR.0 B lock Lock Status

0 = Unlocked

1 = Locked BA+2: (bit 0): 0 or 1

BSR 1–7: Reserved for Future Use BA+2: (bit 1–7): 0

NOTE:

1. BA = The begi nning locat ion of a Bl ock Addr ess (i.e ., 008 000h i s block 1 ’s (64 -KB blo ck) begin ning l ocati on

in word mode).

Table 27. CFI Identification (Sheet 1 of 2)

Offset Length Description Add. Hex

Code Value

10h 3 Query-unique ASCII string “QRY” 10 --51 “Q”

11: --52 “R”

12: --59 “Y”

13h 2 Primary vendor command set and control interface ID code. 13: --01

16- bit ID code for v endor-specif ied algorithms 14: --00

15h 2 Extended Query Table primary algorith m address 15: --31

16: --00

17h 2 Alternate vendor command set and control inter face ID code. 17: --00

256-Mbit J3 (x8/x16)

Datasheet 55

A.5 System Interface Information

The following device information can optimize system interface software.

A.6 Device Geometry Definition

This field provides critical details of the flash device geometry.

0000h means no second vendor-specified algorithm exists 18: --00

19h 2 Secondary al gorithm Exten ded Query Table address. 19: --00

0000h means none exists 1A: --00

Table 27. CFI Identification (Sheet 2 of 2)

Offset Length Description Add. Hex

Code Value

Table 28. System Interface Information

Offset Length Description Add. Hex

Code Value

1Bh 1 VCC logic su pply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts 1B: --27 2.7 V

1Ch 1 VCC logic supply maximum pro gram/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts 1C: --36 3.6 V

1Dh 1 VPP [programming] supply minimum program/erase volt age

bits 0–3 BCD 100 mV

bits 4–7 HEX volts 1D: --00 0.0 V

1Eh 1 VPP [programming] supply maximum program /erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts 1E: --00 0.0 V

1Fh 1 “n” such that typical single word program time-out = 2n µs 1F: --08 256 µs

20h 1 “n” su ch that typical max. buffer write time- out = 2n µs 20: --08 256 µs

21h 1 “n” su ch that typical block erase time-out = 2n ms 21: --0A 1 s

22h 1 “n” such that typical full chip erase time -out = 2n ms 22: --00 NA

23h 1 “n” such that maximum word program time -out = 2n times

typical 23: --04 2 ms

24h 1 “n” such that maximum buffer write time-out = 2n times typi cal 24 : --04 2 ms

25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --04 16 s

26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: - -00 NA

Table 29. Device Geometry Definition (Sheet 1 of 2)

Offset Length Description Code See Table

Below

27h 1 “n” such that device size = 2n in number of bytes 27:

28h 2 Flas h device interf ace: x8 async x16 async x8/x16 async 28: --02 x8/

x16

28:00,29:00 28:01,29:00 28:02,29:00 29: --00

2Ah 2 “n” such that maximum number of bytes in write buffer = 2n2A: --05 32

2B: --00

256-Mbit J3 (x8/x16)

56 Datasheet

Device Geometry Definition

A.7 Primary-Vendor Specific Extended Query Table

Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query

table specifies this and other similar information.

2Ch 1

Number of erase block regions within device:

1. x = 0 means no erase bl ocking; the device eras es in “bulk”

2. x sp ecifies the number of device or partition regions wi th one or

mo re contig uous sa m e - s iz e er ase blo ck s

3. Symmetrically blocked partitions have one blocking region

4. Part ition size = (total blocks) x (individual block size)

2C: --01 1

2Dh 4

Erase Block Region 1 Information 2D:

bit s 0–15 = y, y+1 = number of ide ntical-size er ase blocks 2E:

bit s 16–31 = z, region er ase block(s) si ze are z x 256 bytes 2F:

30:

Table 29. Device Geometry Definition (Sheet 2 of 2)

Offset Length Description Code See T able

Below

Address 32 Mbit 64 Mbit 128 Mbit 256Mbit

27: --16 --17 --18 --19

28: --02 --02 --02 --02

29: --00 --00 --00 -00

2A: --05 --05 --05 -05

2B: --00 --00 --00 -00

2C: --01 --01 --01 -01

2D: --1F --3F --7F -FF

2E: --00 --00 --00 --00

2F: --00 --00 --00 --00

30: --02 --02 --02 --02

Table 30. Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Offset(1)

P = 31h Length Description

(Optional Fl as h Fe atures an d C om m a nd s) Add. Hex

Code Value

(P+0)h 3 Primary extended query table 31: --50 “P”

(P+1)h Unique AS CII string “PRI” 32: --5 2 “R”

(P+2)h 33: --49 “I”

(P+3)h 1 Major version number, ASCII 34: --31 “1”

(P+4)h 1 Minor version number, ASCII 35: --31 “1”

256-Mbit J3 (x8/x16)

Datasheet 57

(P+5)h

(P+6)h

(P+7)h

(P+8)h

Optional feature and command support (1=yes, 0=no) 36: --0A

bits 9–31 are reser ve d; und ef in ed b it s ar e “0. ” If bi t 31 i s 37: --00

“1” t hen ano ther 31 b it fi eld of optiona l feat ures follow s at 38: --00

the end of the bit-30 field. 39: --00

bit 0 Chip erase supported bit 0 = 0 No

bit 1 Suspend erase supported bit 1 = 1 Yes

bit 2 Suspend program supported bit 2 = 1 Yes

bit 3 Legacy lock/unlock supported bit 3 = 1(1) Yes(1)

bit 4 Queued erase supported bit 4 = 0 No

bit 5 Instant Individual block locking supported bit 5 = 0 No

bit 6 Protection bits supported bit 6 = 1 Yes

bit 7 Page-mode read supported bit 7 = 1 Yes

bit 8 Synchronous re ad supported bit 8 = 0 No

(P+9)h 1

Sup ported functions after suspend: read Array, Status,

Query

Other su pported opera tions are:

bits 1–7 reserved; undefined bits are “0”

3A: --01

bit 0 Program supp orted after era s e suspend bit 0 = 1 Yes

(P+A)h

(P+B)h 2

Block status register mask 3B: --01

bits 2–15 are Reserved; undefined bits are “0” 3C: --00

bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes

bit 1 Block Lock-Down Bi t Status active bit 1 = 0 No

(P+C)h 1

VCC logic supply highest performance pr ogram/erase

voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

3D: --33 3. 3 V

(P+D)h 1 VPP optimum program/e rase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts 3E: --00 0.0 V

NOTE:

1. Futu re devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a

va lu e of “0.”

Table 30. Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Offset(1)

P = 31h Length Description

(Optional Flash Features and Commands) Add. Hex

Code Value

256-Mbit J3 (x8/x16)

58 Datasheet

Table 31. Protection Register Information

Offset(1)

P = 31h Length Description

(Optional Flash Features and Commands) Add. Hex

Code Value

(P+E)h 1 Number of Protection register fields in JEDEC ID space.

“00h ,” indicates tha t 256 protection bytes are available 3F: --01 01

(P+F)h

(P+10)h

(P+11)h

(P+12)h

Protection Field 1: Protection Description

This field describes user-available One Time Programmable

(OTP) P rot ectio n Regi st er b yte s. S ome ar e pre - progr a mmed

with device-unique serial numbers. Others are user-

prog rammable . Bit s 0- 15 po int to the P rotec tion Regist er l ock

byte, the section’s first byte. The following bytes are factory

pre-programmed and user-programmable.

bit s 0-7 = Lock/bytes JEDEC-plane physical low address

bit s 8-15 = Lock/bytes JEDEC-pla ne physical high address

bits 16-23 = “n” such that 2n = factory pre-programmed bytes

bit s 24-31 = “n” such that 2n = user-progr ammable bytes

40:

41:

42:

43:

--80

--00

--03

80h

00h

8bytes

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

Table 32. Burst Read Information

Offset(1)

P = 31h Length Description

(Opt io na l Fla s h Fe at ur e s an d Com m a nds) Add. Hex

Code Value

(P+13)h 1

Page Mode Read capability

bits 0–7 = “n” such that 2n HEX value represents the number

of read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read page buffer.

44: --03 8 byte

(P+14)h 1 Number of synchronous mode read configur ation fields that

follow. 00h indicates no burst capability. 45: --00 0

(P+15)h Reserved for future use 46:

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

256-Mbit J3 (x8/x16)

Datasheet 59

Appendix B Flow Charts

Figure 18. Write to Buffer Flowchart

Start

Setup

- Writ e 0x E8

- Bloc k Ad dres s

Ch eck B u ffer Statu s

- Perf orm read operation

- R ead Ready Stat us on s ignal SR7

SR 7 = 1?

Word Count

- Address = bloc k address

- D at a = w ord c ount m inus 1

(Valid range = 0x00 t o 0x 1F )

Confirm

- Writ e 0x D 0

- Bloc k address

End

Yes

SR 7 = 1? No

Load Buffer

- F ill wr ite buf f er up t o word c ount

- Address = within buffer range

- D at a = user dat a

Read Statu s

R egister ( SR)

Full Status Register

Check

(if des ired)

256-Mbit J3 (x8/x16)

60 Datasheet

0606_07A

Figure 19. Status Register Flowchart

Start

SR 7 = '1'

SR 2 = '1'

SR 4 = '1'

SR 3 = '1'

SR 1 = '1'

Yes

SR 6 = '1' Yes

SR 5 = '1'

Error

C om m and S equenc e

Yes

Error

Erase F ailure

Error

Progr am F ailure

- Set by W SM

- R eset b y use r

- See C l ea r Statu s

R eg i ster

Command

- Set/ R eset

by WSM

SR 4 = '1' Yes

End

Command Cycle

- I s sue St at us R egist er C om m and

- Address = any dev ic e addres s

- D at a = 0x 70

Er ase Su spen d

See Susp end / Resum e Flowc har t

Pr og r am Susp en d

See Sus pen d/ R es um e F l owchart

Error

PEN

< V

PENLK

Error

Block Locked

Data Cycle

- R ead St a tu s Re gis t er SR [7: 0]

256-Mbit J3 (x8/x16)

Datasheet 61

Figure 20. Byte/Word Pro gram Flowcha r t

Start

Write 40H,

Address

Write Data and

Address

Read S tatus

SR.7 =

Full Status

Check if Desired

Byte/Word

P rogr a m C o mp lete

Read S tatus

(See Above)

Voltage Range Error

Dev ice Protect Error

Programming Error

Byte/Word

Program

Successful

SR.3 =

SR.1 =

SR.4 =

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

1. Toggling OE# (low t o high t o low ) updat es the st atus regist er . This

can be done in place of issuing t he Read Status R egist er comm and.

Rep eat for subsequent pr ogr a mm ing operations.

SR full sta t us c heck can be done af t er eac h pr ogr am oper at ion, or

af t er a s equence of pr ogr am m ing oper at ions.

Write FFH af t er the last program oper at ion t o place device in read

array mode.

Bus

Operation

Standby

Toggling O E# ( low to high to low ) updates the st atus regist er . This can

be done in place of issuing the Read St at us R egist er com m and.

Rep eat for subsequent pr ogr a mm ing operations.

SR.4, SR .3 and SR.1 ar e only cleared by t he C lear Status R egist er

com mand in cases where multiple locations are progr ammed before

f ull status is checked.

I f an er r or is det ec t ed, c lear t he s t atus register bef ore at tempting retry

or other er r or r ec overy.

Command

Setup Byte /

Word Program

Byte/Word

Program

Comments

Data = 40H

Addr = Location to Be Program m ed

Data = Data to Be Programmed

Addr = Location to Be Program m ed

Chec k SR . 7

1 = WSM Ready

0 = WSM Busy

Command Comments

Chec k SR . 3

1 = Progr am ming to Voltage Er r or

Detect

Chec k SR . 4

1 = Progr am ming Er r or

Read

(N ote 1) Status Register Data

Standby

Chec k SR . 1

1 = D evice Prot ect Det ect

RP# = V

, Block Lock-Bit Is Set

Only required for sy stems

implemeting lock-bit configuration.

256-Mbit J3 (x8/x16)

62 Datasheet

0606_08

Figure 21. Program Suspend/Resume Flowchart

Start

Write B0H

Read Status Register

SR. 7 =

SR. 2 = Programming Compl eted

Write D0H

Programming Resumed

Write FFH

Read Array Data

Bus

Operation Command Comments

Write Program

Suspend Data = B0H

Addr = X

Read Stat us R egister Data

Addr = X

Standby Check SR.7

1 - WSM Ready

0 = WSM Busy

Standby Check SR.6

1 = Programming Suspended

0 = Programming C ompleted

Read Read array locations other

than t hat being program m ed.

Write FFH

Read Data Array

Done Reading

Yes

Write Read A rray Data = FFH

Addr = X

Write Program

Resume Data = D0H

Addr = X

256-Mbit J3 (x8/x16)

Datasheet 63

0606_09

Figure 22. Block Erase Flowchart

Start

Read

Status Register

SR.7 =

Er ase Flash

Block(s) Complete

Ful l Status

Che c k if De sired

Suspend Erase

I s su e S ingle Block Erase

Comm and 20H, B loc k

Address

Suspend

Er ase Loop

Write Confirm D0H

Block Address

Yes

Bus

Operation Command Comments

Write Erase Block Data = 20H

Addr = Block Address

Wr ite (N ot e 1) Erase

Confirm Data = D0H

Addr = X

Read

Status r egis ter data

With the device enabled,

OE# lo w updat es S R

Addr = X

Standby Check SR .7

1 = WS M Ready

0 = WS M Busy

1. The Erase C onfirm byte must follow Erase Setup.

Thi s device does not support er ase queuing. Pl eas e s ee

Applicat ion note AP-646 For software erase queuing

compatibility.

Ful l st a t us check can be don e af t e r al l er ase and wri te

sequences com plete. Write FFH af ter the last operation to

r eset th e devi ce t o re ad ar r a y mode.

256-Mbit J3 (x8/x16)

64 Datasheet

0606_10

Figure 23. Block Erase Suspend/Resume Flowchart

Start

Write B0H

Read Status Register

SR.7 =

SR.6 = Blo ck Erase Co mpleted

Read or Program?

Done?

Write D0H

Block Erase R esumed

Write FFH

Read Array Data

Program

Loop

R ead Array

Data

Read

Yes

Bus

Operation Command Comments

Write Erase Suspend Data = B0H

Addr = X

Read Status Register Data

Addr = X

Standby C hec k SR .7

1 - WSM Ready

0 = WSM Busy

Standby C hec k SR .6

1 = Block Erase Sus pended

0 = Block Erase Complet ed

Write Erase Resume Data = D0H

Addr = X

256-Mbit J3 (x8/x16)

Datasheet 65

Figure 24. Set Block Lock- Bit Flowchart

Start

Write 60H,

Block Address

Write 01H,

Block Address

Read Status Register

SR.7 =

Full Status

Ch eck if D esired

Set Lock-Bi t Comple te

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Command

Set Blo ck Lo ck- B i t

Setup

Comments

Data = 60H

Addr =Block Address

Read Status Register

Data (See Above)

Voltage Range ErrorSR.3 = 1

Command Sequence

Error

SR.4,5 = 1

Set Lock-Bit ErrorSR.4 = 1

Set Lock-Bit

Successful

Bus

Operation

Standby

Command Comments

Check SR.3

1 = Program ming Voltage Error

Detect

SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register

command, in cases where multiple lock-bits are set before full status is

checked.

If an e rror is detected, clear th e st a tus register before a ttemptin g re try

or oth er erro r rec o very.

Standby Check SR.4, 5

Bo th 1 = Comm and Se quence

Error

Standby Check SR.4

1 = Set Lock-Bit Error

Write Set Block Lock- B i t

Confirm Data = 01H

Addr = Block Addr ess

Standby

Re peat f or subsequent loc k-bit operations.

Fu l l stat us che ck can be done afte r each l ock-bit set op erat i on or af ter

a sequen ce of lock-bit set operation s.

Write FFH after the last lock- bit set operation to place device in read

array mode.

Check S R.7

1 = WSM Ready

0 = WSM Busy

Read Sta tus Re gis t er Data

256-Mbit J3 (x8/x16)

66 Datasheet

Figure 25. Clear Lock-Bit Flowchart

Start

Write 60H

Wr ite D0H

Read Status Register

SR.7 =

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

Write FFH after the clear lock-bits operation to place device in read

array mode.

Bus

Operation

Standby

SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register

command.

If an error is detected, clear the status register before attemp ting retry

or other error recove ry.

Command

Clear Block

Lock-Bits Setup

Clear Block or

Lock-Bits Confirm

Comments

Data = 60H

Addr = X

Data = D0H

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Command Comments

Check SR.3

1 = Programming Voltage Error

Detect

Read Status Register

Data (See Above)

Voltage Range ErrorSR.3 = 1

Command Sequence

Error

SR.4,5 = 1

Clear Block Lock-B its

Error

SR.5 = 1

Read Status Regi ster Da ta

Standby Check SR.4, 5

Both 1 = Command Sequence

Error

Standby Check SR.5

1 = Clear Bl ock Lock- Bits Error

Clear Block Lock-Bits

Successful

256-Mbit J3 (x8/x16)

Datasheet 67

Figure 26. Protection Register Programming Flowchart

Start

Write C0H

(Protection Reg.

Program Setup)

Write Protect. Regist er

Address/Data

Read Status Register

SR.7 = 1?

Full Status

Check if Desired

Program Complete

Read Status Register

Data (See Above)

PEN

Range Er ror

Protecti on Register

Programming Error

Attempted Program to

Locked Regist er -

Aborted

Progra m Successf ul

SR.3, S R .4 =

SR.1, S R .4 =

FULL STATUS CHECK PROCEDURE

B us O pera tio n

Write

Standby

Protection Program operations can only be addressed within the protection

error.

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Write FFH after the last program operation to reset device to read array mode.

B us O pera tio n

Standby

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases of multiple protection register program operations before full status is

checked.

If an error is detected, clear the status register before attempting retry or other

error recovery.

Yes

1, 1

0,1

1,1

Command

Pr ot e ction Program

Setup

Pr ot e ction Program

Comments

Da ta = C0H

Data = Data to Program

Addr = Location to Program

Ch eck SR .7

1 = WSM Ready

0 = WSM Busy

Command Comments

SR.1 SR.3 SR.4

0 1 1 V

PEN

Low

0 0 1 Prot. Reg.

Prog. Error

1 0 1 Registe r

Loc k e d:

Aborted

Read Status Register Data Toggle

CE# or OE# to Update Status

Re gister Data

Standby

256-Mbit J3 (x8/x16)

68 Datasheet

Appendix C Design Consider ations

C.1 Three-Line Output Control

The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1,

CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:

a. Lowest possible memory power dissipation.

b. Complete assurance that data bus contention will not occur.

To use these control inputs efficiently, an address decoder should enable the device (see Table 13)

while OE# should be connected to all memory devices and the system’s READ# control line. This

assures that only selected memory devices have active outputs while de-selected memory devices

are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent

unintended writes during system power transitions. POWERGOOD should also toggle during

system reset.

C.2 STS and Block Erase, Program, and Lock-Bit Configuration

Polling

STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a

hardware method of detecting block erase, program, and lock-bit configuration completion. It is

recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions

low after block erase, program, or lock-bit configuration commands and returns to High Z when

the WSM has finished executing the internal algorithm. For alternate configurations of the STS

signal, see the Configuration command.

STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.

STS, in default mode, is also High Z when the device is in block erase suspend (with programming

inactive), program suspend, or in reset/power-down mode.

C.3 Input Signal Transitions—Reducing Overshoots and

Undershoots When Using Buffers or Transceivers

As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory

devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory

specifications. (See “DC Voltage Characteristics” on page 20.) Many buffer/transceiver vendors

now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.

Internal output-damping resistors diminish the nominal output drive currents, while still leaving

sufficient drive capability for most applications. These internal output-damping resistors help

reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-

drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When

considering a buffer/transceiver interface design to flash, devices with internal output-damping

resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For

additional information, please refer to AP-647, 5 Volt Intel StrataFlash® Memory Design Guide

(Order Number: 292205).

256-Mbit J3 (x8/x16)

Datasheet 69

C.4 VCC, VPEN, RP# Transitions

Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of

the specified operating ranges, or RP# ≠ VIH. If RP# transitions to VIL during block erase,

program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of

tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device

will enter reset/power-down mode. The aborted operation may leave data partially corrupted after

programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase

and lock-bit configuration commands must be repeated after normal operation is restored. Device

power-off or RP# = VIL clears the Status Register.

The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or

CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/

power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN

during VCC transitions.

After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK,

the CUI must be placed in read array mode via the Read Array command if subsequent access to

the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.

C.5 Power Dissipation

When designing portable systems, designers must consider battery power consumption not only

during device operation, but also for data retention during system idle time. Flash memory’s

nonvolatility increases usable battery life because data is retained when system power is removed.

256-Mbit J3 (x8/x16)

70 Datasheet

Appendix D Additional Information

Order Number Document/Tool

298130 Intel® S trataFlash™ Memory (J3); 28F256J3, 28F128J3, 28F640J3, 28F320J3

Specification Upd a te

298136 Intel® Persistent Stor age Manager (IPSM) User’s Guide Software Manual

297833 Intel® Flas h Data Inte gra tor (FDI) User’s Gu ide Softwar e Manual

290737 Intel StrataFlash® Synchronous Me mory (K 3/K18); 28F640K3, 28F640K18,

28F128K3, 28F128K18, 28F256K3, 28F256K18

292280 AP-73 2 3 Volt Inte l StrataFlash ® Memory J3 to K3/K18 Migration Guide

292237 AP-68 9 Usin g Intel® Persistent Storage Manager

290606 5 Volt Intel® S trataFlash™ MemoryI28F320J5 and 28F640J5 datashee t

297859 AP-677 Intel® StrataFl ash™ Memory Technol ogy

292222 AP-664 D esigning Intel® StrataFlash™ Memory into Intel® Architecture

292221 AP-66 3 Usin g the Intel® StrataFlash™ Memory Write Buffer

292218 AP-660 Migration Gu ide to 3 Volt Intel® St rataFlash™ Memory

292204 AP-646 Common Flash Interface (CFI) and Command Sets

253418 Intel® Wireless Communications and Computing Pa ckage User’s Guid e

1. Please c all the Inte l Literatur e Center at (800) 5 48-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Vis it Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.

3. For the most current i nformation on Intel StrataFlash memory, visit our webs ite at http://

developer.intel.com/design/flash/isf.

256-Mbit J3 (x8/x16)

Datasheet 71

Appendix E Ordering Information

NOTE:

1. Speeds are for eithe r the standard asynchron ous read access times or fo r the first access of a page-mode read sequence.

VALID COMBINATIONS

P C 2 8 F 2 5 6 J 3 C - 1 2

Pr oduct li n e des i gn ator

for all Intel

Fla sh

products

Ac cess Speed (ns)

256 Mbit = 125

128 Mbit = 150, 120

64 Mbit = 120, 115

32 Mbit = 110

Product Family

J = In te l

StrataFlash memory,

2 bits-per-cell

D evice Densit y

256 = x8/x16 (256 Mbit)

128 = x8/x1 6 (128 Mbit)

640 = x8/x16 (64 Mbit)

320 = x8/x16 (32 Mbit)

Voltage (V

PEN

)

3 = 3 V/3 V

A = Intel

0.2 5

micron lithogr aphy

C = Intel® 0.18

micron lithogr aphy

Package

E = 56-Lead TSOP (J3A, 802)

TE= 56-Lead TSOP (J3C, 803)

JS = Pb-Fre e 56-TS OP

RC = 64-Ball Easy BGA

GE = 48-Ball VF BGA

PC = 64-Ball Pb-Free

Easy BGA

56-Lead TSOP 64-Ball Easy BGA 48- Ball V F BGA

E28F320J3A-110 RC28F320J3A-110 GE28F320J3A-110

E28F640J3A-120 RC28F640J3A-120 GE28F320J3C-110

E28F128J3A-150 RC28F128J3A-150 GE28F640J3C-115

TE28F320J3C-110 RC28F320J3C-110 GE28F640J3C-120

TE28F640J3C-115 RC28F640J3C-115

TE28F640J3C-120 RC28F640J3C-120

TE28F128J3C-120 RC28F128J3C-120

TE28F128J3C-150 RC28F128J3C-150

TE28F256J3C-125 RC28F256J3C-125

56-Lead Pb-Free TSOP 64-Ball Pb-Free Easy BGA

JS28F256J3C125 PC28F256J3C125

JS28F128J3C120 PC28F128J3C120

JS28F640J3C115 PC28F640J3C115

JS28F320J3C110 PC28F320J3C110

256-Mbit J3 (x8/x16)

72 Datasheet