INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT280 9-bit odd/even parity generator/checker Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74HC/HCT280 transmission or data retrieval systems. Both even and odd parity outputs are available for generating or checking even or odd parity up to 9 bits. FEATURES * Word-length easily expanded by cascading * Similar pin configuration to the "180" for easy system up-grading The even parity output (E) is HIGH when an even number of data inputs (I0 to I8) are HIGH. The odd parity output (0) is HIGH when an odd number of data inputs are HIGH. * Generates either odd or even parity for nine data bits * Output capability: standard Expansion to larger word sizes is accomplished by tying the even outputs (E) of up to nine parallel devices to the data inputs of the final stage. For a single-chip 16-bit even/odd parity generator/checker, see PC74HC/HCT7080. * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. APPLICATIONS * 25-line parity generator/checker * 81-line parity generator/checker The 74HC/HCT280 are 9-bit parity generators or checkers commonly used to detect errors in high-speed data QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V In to E 17 18 ns In to O 20 22 ns 3.5 3.5 pF 65 65 pF CI input capacitance CPD power dissipationcapacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". December 1990 2 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74HC/HCT280 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 8, 9, 10, 11, 12, 13, 1, 2, 4 I0 to I8 data inputs 5, 6 E, O parity outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74HC/HCT280 FUNCTION TABLE INPUTS OUTPUTS number of HIGH data inputs (I0 to I8) E O even odd H L L H Note 1. H = HIGH voltage level L = LOW voltage level Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74HC/HCT280 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Out put capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay In to E 55 20 16 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay In to O 63 23 18 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74HC/HCT280 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT In 1.0 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay In to E 21 42 53 63 ns 4.5 Fig.6 tPHL/ tPLH propagation delay In to O 26 45 56 68 ns 4.5 Fig.6 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74HC/HCT280 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the data input (In) to parity outputs (E, O) propagation delays and the output transition time. APPLICATION INFORMATION For a single-chip 16-bit even/odd parity generator/checker, see PC74HC/HCT7080. Fig.7 Cascaded 17-bit odd/even parity generator/checker. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7