 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DSwitching Rates up to 32 MHz
DOperates From Single 3.3-V Supply
DUltra-Low Power Dissipation . . . 27 mW Typ
DOpen-Circuit, Short-Circuit, and Terminated
Fail-Safe
D0.3-V to 5.5-V Common-Mode Range With
±200-mV Sensitivity
DAccepts 5-V Logic Inputs With 3.3-V VCC
DInput Hysteresis . . . 50 mV Typ
D235 mW With Four Receivers at 32 MHz
DPin-to-Pin Compatible With AM26C32,
AM26LS32, and MB570
description/ordering information
The AM26LV32, BiCMOS, quadruple, differential line receiver with 3-state outputs is designed to be similar to
TIA/EIA-422-B and ITU Recommendation V.11 receivers with reduced common-mode voltage range due to
reduced supply voltage.
The device is optimized for balanced bus transmission at switching rates up to 32 MHz. The enable function
is common to all four receivers and offers a choice of active-high or active-low inputs. The 3-state outputs permit
connection directly to a bus-organized system. Each device features receiver high input impedance and input
hysteresis for increased noise immunity, and input sensitivity of ±200 mV over a common-mode input voltage
range from −0.3 V to 5.5 V. When the inputs are open circuited, the outputs are in the high logic state. This device
is designed using the Texas Instruments (TI) proprietary LinIMPACT-C60 technology, facilitating ultra-low
power consumption without sacrificing speed.
This device offers optimum performance when used with the AM26LV31 quadruple line drivers.
The AM26LV32C is characterized for operation from 0°C to 70°C. The AM26LV32I is characterized for operation
from −45°C to 85°C.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
AM26LV32CDG4
DTape and reel AM26LV32CDR AM26LV32C
0°C to 70°C
D
Tape and reel
AM26LV32CDRG4
AM26LV32C
0C to 70 C
NS
Tube AM26LV32CNS
26LV32
NS Tape and reel AM26LV32CNSR 26LV32
SOP – D
Tube
AM26LV32ID
AM26LV32I
−40°C to 85°C
SOP – D
Tube
AM26LV32IDR
AM26LV32I
−40
°
C to 85
°
C
SOP – NS
Tube AM26LV32INS
26LV32I
SOP – NS
Tape and reel AM26LV32INSR
26LV32I
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
  !" # $%&" !#  '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinIMPACT-C60 and TI are trademarks of Texas Instruments.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
D OR NS
PACKAGE
(TOP VIEW)
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
(each receiver)
DIFFERENTIAL
ENABLES
OUTPUT
DIFFERENTIAL
INPUT G G
OUTPUT
VID 0.2 V H
XX
LH
H
0.2 V < VID < 0.2 V H
XX
L?
?
VID 0.2 V H
XX
LL
L
Open, shorted, or
terminatedH
XX
LH
H
X L H Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
See application information attached.
logic symbol
4Y
3Y
2Y
1Y
13
11
5
3
4B
4A
3B
3A
2B
2A
1B
1A
G
G
15
14
9
10
7
6
1
2
12
4EN
1
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
4Y
3Y
2Y
1Y
13
11
5
3
4B
4A
3B
3A
2B
2A
1B
1A
G
G
15
14
9
10
7
6
1
2
12
4
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
schematics of equivalent inputs and outputs
Enable
G, G
VCC
TYPICAL OF ALL OUTPUTS (Y)
Y
VCC
GND GND
EQUIVALENT OF EACH
ENABLE INPUT (G, G)
A, B
VCC
GND
EQUIVALENT OF EACH INPUT (A, B)
7.2 k
15 k1.5 k
7.2 k
1.5 k100
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) 0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (A or B inputs) 4 V to 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage range 0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO 0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum output current, IO ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
High-level input voltage, VIH(EN) 2 V
Low-level input voltage, VIL(EN) 0.8 V
Common-mode input voltage, VIC −0.3 5.5 V
Differential input voltage, VID ±5.8
High-level output current, IOH −5 mA
Low-level output current, IOL 5 mA
Operating free-air temperature, TA
AM26LV32C 0 70
°C
Operating free-air temperature, T
AAM26LV32I −40 85 °
C
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended supply-voltage and operating free-air temperature
ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIT+ Differential input high-threshold voltage 0.2 V
VIT− Differential input low-threshold voltage −0.2 V
VIK Enable input clamp voltage II = −18 mA −0.8 −1.5 V
VOH High-level output voltage VID = 200 mV, IOH = −5 mA 2.4 3.2 V
VOL Low-level output voltage VID = −200 mV, IOL = 5 mA 0.17 0.5 V
IOZ High-impedance-state output current VO = 0 to VCC ±50 µA
IIH(E) High-level enable input current VCC = 0 or 3 V, VI = 5.5 V 10
IIL(E) Low-level enable input current VCC = 3.6 V, VI = 0 V −10 µA
rIInput resistance 7 12 k
IIInput current VI = 5.5 V or −0.3 V, All other inputs GND ±700 µA
ICC Supply current VI(E) = VCC or GND, No load, line inputs open 8 17 mA
Cpd Power dissipation capacitanceOne channel 150 pF
All typical values are at VCC = 3.3 V and TA = 25°C.
Cpd determines the no-load dynamic current: IS = Cpd × VCC × f + ICC.
switching characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output
See Figure 1
8 16 20
tPHL Propagation delay time, high- to low-level output See Figure 1 8 16 20 ns
ttTransistion time (tr or tf)See Figure 1 5 ns
tPZH Output-enable time to high level See Figure 2 17 40 ns
tPZL Output-enable time to low level See Figure 3 10 40 ns
tPHZ Output-disable time from high level See Figure 2 20 40 ns
tPLZ Output-disable time from low level See Figure 3 16 40 ns
tsk(p)§Pulse skew 4 6 ns
tsk(o)Pulse skew 4 6 ns
tsk(pp)#Pulse skew (device to device) 6 9 ns
§tsk(p) is |tPLH − tPHL| of each channel of the same device.
tsk(o) is the maximum difference in propagation delay times between any two channels of the same device switching in the same direction.
#tsk(pp) is the maximum difference in propagation delay times between any two channels of any two devices switching in the same direction.
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50 50
Generator
(see Note B)
VCC
CL = 15 pF
(see Note A) tPLH tPHL
90% 90%
50% 50%
10% 10%
trtf
A
B
Input
Output
2 V
1 V
VOH
VOL
A
BYVO
GG
(see Note C)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 , PRR = 10 MHz, tr and tf (10% to 90%)
2 ns, 50% duty cycle.
C. To test the active-low enable G, ground G and apply an inverted waveform G.
Figure 1. tPLH and tPHL Test Circuit and Voltage Waveforms
50%
Input
tPZH tPHZ
VOH
50%
50%
Voff 0
0 V
VCC
Output
Generator
(see Note B) 50
RL = 2 kCL = 15 pF
(see Note A)
VCC
(see Note C)
VID = 1 V A
B
YVO
G
G
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 , PRR = 10 MHz, tr and tf (10% to 90%)
2 ns, 50% duty cycle.
C. To test the active-low enable G, ground G and apply an inverted waveform G.
VOH − 0.3 V
Figure 2. tPZH and tPHZ Test Circuit and Voltage Waveforms
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50%
Input
tPZL tPLZ
50%
50%
VOL
0 V
VCC
Output
Generator
(see Note B) 50
RL = 2 k
CL = 15 pF
(see Note A)
VCC
(see Note C)
VID = 1 V
VCC
Voff VCC
A
B
Y
G
G
VO
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: ZO = 50 , PRR = 10 MHz, tr and tf (10% to 90%)
2 ns, 50% duty cycle.
C. To test the active-low enable G, ground G and apply an inverted waveform G.
VOL + 0.3 V
Figure 3. tPZL and tPLZ Test Circuit and Voltage Waveforms
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
fail-safe conditions
The AM26LV32 quadruple differential line receiver is designed to function properly when appropriately
connected to active drivers. Applications do not always have ideal situations where all bits are being used, the
receiver inputs are never left floating, and fault conditions don’t exist. In actuality, most applications have the
capability t o either place the drivers in a high-impedance mode or power down the drivers altogether, and cables
may be purposely (or inadvertently) disconnected, both of which lead to floating receiver inputs. Furthermore,
even though measures are taken to avoid fault conditions like a short between the dif ferential signals, this does
occur. The AM26LV32 has an internal fail-safe circuitry which prevents the device from putting an unknown
voltage signal at the receiver outputs. In the following three cases, a high-state is produced at the respective
output:
1. Open fail-safe − Unused input pins are left open. Do not tie unused pins to ground or any other
voltage. Internal circuitry places the output in the high state.
2. 100-ohm terminated fail-safe − Disconnected cables, drivers in high-impedance state, or
powered-down drivers will not cause the AM26LV32 to malfunction. The outputs will remain in
a high state under these conditions. When the drivers are either turned-off or placed into the
high-impedance state, the receiver input may still be able to pick up noise due to the cable acting
as an antenna. To avoid having a large differential voltage being generated, the use of
twisted-pair cable will induce the noise as a common-mode signal and will be rejected.
3. Shorted fail-safe − Fault conditions that short the dif ferential input pairs together will not cause
incorrect data at the outputs. A differential voltage (VID) of 0 V will force a high state at the
outputs. Shorted fail-safe, however, is not supported across the recommended common-mode
input voltage (VIC) range. An unwanted state can be induced to all outputs when an input is
shorted and is biased with a voltage between −0.3 V and 5.5 V. The shorted fail-safe circuitry
will function properly when an input is shorted, but with no external common-mode voltage
applied.
fail-safe precautions
The internal fail-safe circuitry was designed such that the input common-mode (VIC) and differential
(VID)voltages must be observed. In order to ensure the outputs of unused or inactive receivers remain in a high
state when the inputs are open-circuited, shorted, or terminated, extra precaution must be taken on the active
signal. In applications where the drivers are placed in a high-impedance mode or are powered-down, it is
recommended that for 1, 2, or 3 active receiver inputs, the low-level input voltage (VIL) should be greater than
0.4 V. As in all data transmission applications, it is necessary to provide a return ground path between the two
remote grounds (driver and receiver ground references) to avoid ground differences. Table 1 and Figures 4
through 7 are examples of active input voltages with their respective waveforms and the effect each have on
unused or inactive outputs. Note that the active receivers behave as expected, regardless of the input levels.
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 1. Active Receiver Inputs vs Outputs
1, 2, OR 3
ACTIVE INPUTS SEE
FIGURE
1, 2, OR 3
ACTIVE OUTPUTS
3, 2, OR 1 UNUSED
OR INACTIVE
VILVID VIC
FIGURE
ACTIVE OUTPUTS
OR INACTIVE
OUTPUTS
900 mV 200 mV 1 V 4Known state High state
−100 mV 200 mV 0 V 5Known state ?
600 mV 800 mV 1 V 6Known state High state
0800 mV 400 mV 7Known state ?
Measured with respect to ground.
VID = 200 mV
VIC = 1V
VIL = 900 mV
Produces a High State at
Unused or Inactive Outputs
0V
Figure 4. Waveform One
VID = 200 mV
VIL = −100 mV
An Unknown State is Produced
at Unused or Inactive Outputs
VIC = 0V
Figure 5. Waveform Two
VIC = 1V
VIL = 600 mV
Produces a High State at
Unused or Inactive Outputs
0V
VID = 800 mV
Figure 6. Waveform Three
VIL = 0V 0V
VID = 800 mV
VIC = 400 mV
An Unknown State is Produced
at Unused or Inactive Outputs
Figure 7. Waveform Four
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
In most applications, it is not customary to have a common-mode input close to ground and to have a differential
voltage larger than 2 V. Since the common-mode input voltage is typically around 1.5 V, a 2-V VID would result
in a VIL of 0.5 V, thus satisfying the recommended VIL level of greater than 0.4 V.
Figure 8 plots seven dif ferent input threshold curves from a variety of production lots and shows how the fail-safe
circuitry behaves with the input common-mode voltage levels. These input threshold curves are representative
samples of production devices. The curves specifically illustrate a typical range of input threshold variation. The
AM26LV32 i s specified with ±200 mV of input sensitivity to account for the variance in input threshold. Each data
point represents the input’s ability to produce a known state at the output for a given VIC and VID. Applying a
differential voltage at or above a certain point on a curve would produce a known state at the output. Applying
a dif ferential voltage less than a certain point on a curve would activate the fail-safe circuit and the output would
be in a high state. For example, inspecting the top input threshold curve reveals that for a VIC + 1.6 V, VID yields
around 87 mV. Applying 90 mV of d i fferential voltage to this particular production lot generates a known receiver
output voltage. Applying a VID of 80 mV activates the input fail-safe circuitry and the receiver output is placed
in the high state. Texas Instruments specifies the input threshold at ±200 mV, since normal process variations
affect this parameter. Note that at common-mode input voltages around 0.2 V, the input differential voltages are
low compared to their respective data points. This phenomenon points to the fact that the inputs are very
sensitive to small dif ferential voltages around 0.2 V VIC. It is recommended that VIC levels be kept greater than
0.5 V to avoid this increased sensitivity at VIC [ 0.2 V. In most applications, since VIC typically is 1.5 V, the
fail-safe circuitry functions properly to provide a high state at the receiver output.
−0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4−1
0
10
20
30
40
50
60
70
80
90
100
VID Differential Voltage − mV
VIC − Common-Mode Input Voltage − V
Not
Recommended
Most
Applications
Increased Receiver Input Sensitivity
Figure 8. VIC Versus VID Receiver Sensitivity Levels
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 9 represents a typical application where two receivers are not used. In this case, there is no need to worry
about the output voltages of the unused receivers since they are not connected in the system architecture.
System
Connector AM26LV32
Unused Circuit
RT
RT
Figure 9. Typical Application with Unused Receivers
Figure 10 shows a common application where one or more drivers are either disabled or powered down. To
ensure the inactive receiver outputs are in a high state, the active receiver inputs must have VIL > 0.4 V and VIC >
0.5 V.
System
Connector AM26LV32
Connector
Driver
Enable
Disable or
Power Off
Cable
RT
RT
RT
RT
Figure 10. Typical Application Where Two or More Drivers are Disabled
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 11 is an alternative application design to replace the application in Figure 10. This design uses two
AM26LV32 devices, instead of one. However, this design does not require the input levels be monitored to
ensure the outputs are in the correct state, only that they comply to the RS-232 standard.
System
Connector AM26LV32
Connector
Driver
Enable
Disable or
Power Off
Cable
AM26LV32
RT
RT
RT
RT
Unused Circuit
Unused Circuit
Figure 11. Alternative Solution for Figure 10
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figures 12 and 13 show typical applications where a disconnected cable occurs. Figure 12 illustrates a typical
application where a cable is disconnected. Similar to Figure 10, the active input levels must be monitored to
make sure the inactive receiver outputs are in a high state. An alternative solution is shown in Figure 13.
System
Connector AM26LV32
Connector
Driver
Cable
Unplugged
Cable
RT
RT
RT
RT
Figure 12. Typical Application Where Two or More Drivers are Disconnected
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 13 i s a n alternative solution so the receiver inputs do not have to be monitored. This solution also requires
the use of two AM26LV32 devices, instead of one.
System
Connector AM26LV32
Connector
Driver
Cable
Unplugged
Cable
RT
RT
Unused Circuit
RT
RT
Unused Circuit
AM26LV32
Figure 13. Alternative Solution to Figure 12
 
     
SLLS202E − M AY 1995 − REVISED JUNE 2005
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
When designing a system using the AM26LV32, the device provides a robust solution where fail-safe and fault
conditions are of concern. The RS-422-like inputs accept common-mode input levels from −0.3 V to 5.5 V with
a specified sensitivity of ±200mV. As previously shown, care must be taken with active input levels since they
can affect the outputs of unused or inactive bits. However, most applications meet or exceed the requirements
to allow the device to perform properly.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
AM26LV32CD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CDE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CDRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CNSLE OBSOLETE SO NS 16 TBD Call TI Call TI
AM26LV32CNSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CNSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32CNSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32ID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32IDE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32IDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32IDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32IDRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32INS ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32INSE4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32INSG4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32INSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32INSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
AM26LV32INSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
AM26LV32CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LV32CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LV32CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
AM26LV32IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LV32INSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AM26LV32CDR SOIC D 16 2500 333.2 345.9 28.6
AM26LV32CDR SOIC D 16 2500 367.0 367.0 38.0
AM26LV32CNSR SO NS 16 2000 367.0 367.0 38.0
AM26LV32IDR SOIC D 16 2500 333.2 345.9 28.6
AM26LV32INSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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