fax id: 3600 Crystal Oscillator Topics Introduction XTALIN XTALOUT R A PLL-based frequency synthesizer uses a reference input to generate output clocks. The reference can be provided by a quartz crystal or an external clock source. The accuracy and stability of the output clocks in a PLL-based frequency synthesizer are directly proportional to those of the reference. Thus, it is important to provide a stable, accurate, and appropriate reference input. This application note describes the recommended reference inputs for Cypress's PLL-based frequency synthesizers, and concludes with an error budget analysis. G Co Ci Please note that this application note applies only to Cypress Frequency Synthesizers and not to Cypress Clock Buffers. INTERNAL TO DEVICE Please note that this application note does not apply to the ICD6233 (one-time programmable clock oscillator), the CY2305/8/9 Zero Delay Buffers or the CY7B991/2 and CY7B9910/20 (RoboClock and RoboClock Jr.). For applications assistance on CY7B991/2 and CY7B9910/20, see the application note "Everything You Need to Know About CY7B991/2 (RoboClock) But Were Afraid to Ask." For application assistance on the CY2305/8/9, refer to the application notes Figure 2. On-Chip Crystal Oscillator Circuitry C1 L1 R1 Cypress's PLL-Based Frequency Synthesizers Figure 1 shows the block diagram of a typical PLL-based frequency synthesizer. Note that the reference input to all PLLs comes from an on-chip crystal oscillator, which is the architecture of all Cypress clock generators. Co The equivalent circuit of a Quartz crystal is shown in Figure 3. Co is the shunt or static capacitance of the crystal. R1 is the motional resistance, L1 is the motional inductance, and C1 is the motional capacitance of the crystal. R1, L1 and C1 are determined by the mechanical properties of the crystal (they are in the motional arm of the crystal and their circuit effects only exist when the crystal is oscillating). The effective reactance curve of the crystal is shown in Figure 4. Are res a of p on anc aralle l e fs Frequency Capacitive Reactance Figure 2 shows the circuitry of the on-chip crystal oscillator (a.k.a. Pierce oscillator), which is formed by components R, G, Ci and Co, where G is a linear inverter. For this circuit to produce an electrical clock, a quartz crystal needs to be connected between the XTALIN and XTALOUT pins. Inductive Figure 3. Equivalent Circuit of a Quartz Crystal crystal bandwidth Figure 4. Crystal Reactance v/s Frequency XTALIN XTALOUT REFERENCE CRYSTAL OSCILLATOR OUTPUTS PLLs DIVIDERS INTERNAL TO DEVICE Figure 1. Typical PLL-based Frequency Synthesizer Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Crystal Oscillator Topics Cload = Capacitive loading rating of crystal When connected as a feedback element in a oscillator circuit that has a no phase shift (O), the crystal oscillates at the series resonating frequency (fs) given by 1 f s = -------------------------2 L 1 C 1 CL = Capacitive loading seen by crystal in oscillator circuit. If a series resonant crystal (which is simply a crystal whose rated frequency is fs) is used in a Pierce oscillator circuit, the frequency of oscillation will be higher than the rated frequency by about 0.02% or 200 ppm. The actual value of frequency can be calculated from Equation 2. Eq. 1 A Pierce oscillator has a 180 phase shift on the amplifier and needs another 180 phase shift from the feedback element. The feedback element in this case is a crystal along with a capacitive load, and the frequency of oscillation of the crystal (and oscillator circuit) is in the "area of parallel resonance". The actual value of the crystal oscillator parallel resonating frequency is dependent on the capacitive loading seen by the crystal and is given by C1 fp = f s ----------------------------- + 1 2 ( C + C ) 0 L Crystals Recommended for Cypress Clock Generators Figure 5 shows the required connection of a crystal to an on-chip oscillator of a PLL-based frequency synthesizer. For best results, a fundamental mode, parallel resonant crystal should be used. The load capacitance of this crystal (Cload) must match the load capacitance of the oscillator circuitry (CL), as seen by the crystal. As shown in Figure 5, under normal AC conditions, Co will be in series with Ci2. Thus, Eq. 2 C 0 C i2 C L = -----------------------C 0 + C i2 where CL = Capacitive loading seen by the crystal. For example, a 14.318 MHz parallel resonant crystal tuned to a Cload = 18 pF will oscillate at 14.318 MHz (not including tolerance) when it is placed in a Pierce oscillator (parallel oscillator) circuit which offers a capacitive loading CL=18 pF. If the capacitive loading seen by the crystal in the Pierce oscillator circuit were different from the rated Cload, the change in frequency from the rated frequency is given in Equation 3. C f -f 1 1 p ( ra ted ) p ( actual ) 1 ---------------------------------------------------------- = ------- ------------------------------- - -------------------------- 2 C + C f ( C + C ) p ( rated ) lo ad 0 L 0 Eq. 4 CL = 17 pF. However, if parasitics are accounted for, C oeq C i2eq C L = ---------------------------------C oeq + C i2eq Eq. 5 where C oeq = C o + 2pF , C i2eq = C i2 + 2pF which results in CL = 18 pF. Hence, fundamental mode, parallel-resonant crystals with Cload = 17 to 18 pF should be used for best results with Cypress clock generators. If the Cload of the crystal does not equal 17 or 18 pF, the output frequency will be somewhat different from the target. Also, since capacitors Ci2 and Co are Eq. 3 fp(rated) = frequency rating of crystal fp(actual) = actual frequency of oscillation in oscillator circuit Recommended if Cload > 18 pF Cload CRYSTAL Die Clock Rb Cext G2 G1 XTALIN Parasitic Capacitance 2 pF XTALOUT Ci2=34 pF Co=34 pF INTERNAL TO DEVICE Figure 5. Using a Crystal as Reference 2 Parasitic Capacitance 2 pF Crystal Oscillator Topics on-chip, no additional external components are required for operation, provided a crystal with matched Cload is used. of the device. For Cypress's on-chip oscillator, using a series resonant crystal will typically add a 500 ppm (.05%) error on the output frequencies. For some applications, such as time keeping, choosing the right crystal type is crucial. For example, a 50 ppm error in the reference frequency produces a real time clocking error of 2 minutes per month. Thus, the user must ensure that proper crystals are used with Cypress clock generators. A Patch for Crystals with an Unmatched Cload As shown in Figure 5, Cypress recommends the addition of an external capacitor, Cext, on or close to the XTALOUT pin to compensate for a C load > 18 pF. Co and Cext are in parallel, which, under AC conditions, are in series with Ci2. Solving the following equation for Cext, which accounts for parasitics, C i2eq (C oeq + C ext ) C L = --------------------------------------------------------C i2eq + (C oeq + C ext ) Special Case: 32.768 kHz Crystal The CY2291 and CY2295 offer internal parallel resonant oscillation circuitry that can produce a 32.768-kHz signal, which is commonly used as a real time clock. Since the internal circuitry does not have a biasing resistor on-chip, a 10-M resistor must be placed in parallel to the 32.768-kHz crystal, as shown in Figure 6. Performing the calculations based on Equation 4 and Equation 5 results in a crystal requirement of Cload = 12 to 13 pF. If the crystal has Cload > 13 pF, then a Cext, as calculated from Equation 6, is needed. If the Cload of the crystal is less than 12 or 13 pF, a capacitor cannot be placed in series with the 32XIN or 32XOUT pin, as explained before. Eq. 6 gives the value of the external capacitor required. For a crystal with Cload=20 pF, Cext = 9 pF would be required. Note that for Cload < 17 pF, solving Equation 7 (does not account for parasitics) for Cext results in a negative capacitance value. C i2 (C o + C ext ) C L = ---------------------------------------------C i2 + ( C o + C ext ) Using an External Signal Source Eq. 7 Thus, there is no patch available, and the user needs to instead use a crystal with Cload = 17 to 18 pF. Using a capacitor in series with the XTALIN or XTALOUT pin will redue the Cload seen by the crystal, but will cause start-up problems. This is because the crystal needs to have a DC voltage across it to start oscillations. And if a capacitor is used in series with the XTALIN and XTALOUT pins, this capacitor will block any DC voltage normally applied to the crystal on start-up. Frequently, a frequency synthesizer is driven by an external signal source rather than a crystal. In this case, the external clock should be driven in on the XTALIN pin, and the XTALOUT pin must be left floating. Cypress also recommends using a small coupling capacitor in series with the signal, as shown in Figure 7. Such a capacitor provides the benefits of reduced loading of the signal source and restoration of duty cycle, as explained below. Using a Series Resonant Crystal Reduced Loading In general, using a series resonant crystal with a parallel resonant circuit will introduce an error on the output frequencies As shown in Figure 7, the two internal capacitors are each 34 pF. Without the coupling capacitor Ci1, the frequency source is effectively driving Ceff=34 pF (not accounting for parasit- 32.768 kHz CRYSTAL Recommended if Cload > 13 pF Cload = 12 or 13 pF 10 M C ext TO 32K OUTPUT G2 G1 32XIN Parasitic Capacitance 2 pF 32XOUT Ci2=20 pF Co=20 pF INTERNAL TO DEVICE Figure 6. Using a 32.768 kHz Crystal 3 Parasitic Capacitance 2 pF Crystal Oscillator Topics To PLL Rb Ci1 Ceff XTALOUT XTALIN Vi2 Vin G1 Vi1 Frequency Source (5 Volt) G2 22 pF Vout Ci2=34 pF Co=34 pF Parasitic Capacitance 2 pF Parasitic Capacitance 2 pF INTERNAL TO DEVICE Figure 7. Using an External Driver as Reference Coupling Capacitor Value ics), where Ceff is the effective load capacitance seen by the driver. Ceff is reduced by the addition of Ci1 in series with C i2. Now, Eq. 8 For Vi1=5Vpp applied to a Cypress device, a capacitor value of Cil=22 to 24 pF, placed as close to the XTALIN pin as possible, is recommended. Using Ci1=22 to 24 pF provides 2Vpp around an average DC level of VDD/2 at XTALIN, as well as reduced loading and restored duty cycle. For example, Ci1=22 pF and Ci2=34 pF results in Ceff=13.4 pF. In this case, Ceff is reduced by 62%, which results in reduced loading of the frequency source, reduced power supply noise, and thus improved signal transition times. Cypress clock generators require Vi2=2Vpp. Thus for 5V input signal (Vi1=5Vpp), Vi2=2Vpp, and Ci2=34 pF, solving Equation 8 results in Ci1 22 pF. Accounting for parasitics by substituting Ci2eq=36 pF for Ci2=34 pF, the result is Ci1=24 pF. While the load is reduced, so is the amplitude of the signal at XTALIN according to the following equation: For a 3.3V input signal (Vi1=3.3Vpp), Vi2=2Vpp, and C i2=34 pF, solving Equation 8 results in C i1 52 pF. Accounting for parasitics results in Ci1 55 pF. C i1 V i2 = V i1 -----------------------C i1 + C i2 General Error Budget Analysis C i1 C i2 C eff = -----------------------C i1 + C i2 Eq. 9 As in any good design, an error budget should be calculated. Several sources of error must be taken into account. Using the same numbers, as in the example above, and setting the input voltage Vi1=5Vpp results in Vi2 = 2Vpp. However, the reduction in amplitude is not a problem since the linear inverter, G1, helps bias and re-amplify the signal. Specifically, the DC level of Vin equals the DC level of Vout, and thus the DC level is biased to VDD/2 (CMOS threshold level). Furthermore, the amplifier circuit, consisting of G1 and feedback resistor Rb, results in an AC gain of the signal. * Reference source frequency tolerance (ppm); specified by manufacturer of reference * Reference source temperature stability (ppm); specified by manufacturer of reference * Crystal Oscillator process variation (ppm); specified by clock chip manufacturer * Crystal Oscillator supply voltage and temperature stability (ppm); specified by clock chip manufacturer Restoration of Duty Cycle Typically a waveform at XTALOUT, with a duty cycle of 35-65%, can have the duty cycle restored close to 50%. This restoration can be seen on the output of G2, in Figure 7, which is typically the XBUF pin on most devices. The following example uses typical error values for crystals and Cypress clock devices. Both the matched characteristics of G1 and G2, and the R-C components work to restore the duty cycle, the mechanism being an AC gain and their effect on DC biasing, as previously mentioned. However, duty cycle regulation is reduced by G1 saturating near VDD or ground. To keep G1 in the linear region, Ci1 should not be too large. A smaller Ci1 reduces signal amplitude, thus improving linearity. 4 Crystal Oscillator Topics Example: Addition of Relevant Sources of Error Source of Error Error in ppm Reference Source, Crystal Frequency tolerance 50 ppm Temperature stability 30 ppm Crystal Oscillator in Cypress Clock Generator Process Variation 20 ppm Voltage and Temperature stability 05 ppm Total 105 ppm Summary In summary, Cypress recommends the following for our clock generators. For designs that use a crystal for the input reference, the crystal should be parallel resonant, and have Cload = 17 to 18 pF. If Cload > 18 pF, then use an external capacitor, as shown in Figure 5, with Cext calculated from Equation 6. If Cload < 17 pF, then instead use a crystal with Cload = 17 to 18 pF. For designs using the 32.768-kHz circuitry, a parallel resonant crystal with Cload = 12 to 13 pF must be used. A 10-M biasing resistor must be placed in parallel with the crystal. 5V designs using an external clock source must AC couple the clock input with a 22- to 24-pF capacitor in series with the clock source. 3.3V designs should use a 52- to 55-pF coupling capacitor instead. For layout recommendations on Cypress clock devices, please read the application notes: "Jitter in PLL-Based Systems: Causes, Effects, and Solutions," and "Layout and Termination Techniques for Cypress Clock Generators" and, if available, the application note corresponding to the specific device. (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.