Functional Description
21324-DSH-001-C Mindspeed Technologies®15
Mindspeed Proprietary and Confidential
2.1.3 High-Speed Outputs
The high-spe e d differential outpu ts afte r eq ua liza tio n ar e mad e available on the SDO/SDO pins. The output swing
and common-mode is compat ible with the GS2974/GS2974A, GS1574/GS1574A and GS9074A.
2.1.4 Adaptive Equalization Selection
In typical operation, the adaptive equalization is enabled with EQ_BYP = Lo w; however, with EQ_BYP = High, the
adaptive equalization and DC rest or e circ uit is bypassed and the input is fed directly to the output.
2.1.5 Output Mute and Signal Detect
When configured as an inpu t by forcing a voltage on SD/MUTE = High (Vdd), the output of the M21324 will be
inhibited at logic low (outputs muted). When SD/MUTE = Low (Vss), the output is never muted and the
programmable cable length based mute function is disab led.
When tied to a high-impedance input or left floating, t he program mable inhibi t based on cab le length is enab led and
the pin is defined as an L OS outp ut (logic). I n the event o f an LO S, the output is muted. The inh ibit thre sh old is set
with an analog voltage applied to the THRESH input pin, this threshold will depend on cable type (e.g. Belden
1694A or 8281). To achieve maximu m cable length equalization, the THRESH pin should b e left open. Decouplin g
capacitors should be used between the THRESH pin and GND.
2.1.6 Equalizer Detailed Description
The basic equalizer design consists of interlaced stages of gain and equalization to maximize both the overall
equalization gain as well as the input sensitivity for maximum performance with minimum jitter. In order to achieve
maximum distance at 270 Mbps, 1485 Mbps and 2970 Mbps with Belden 1694A, the overall equalizer block has
over 50 dB of broadband signal boost and maintains an input se nsitivity of approximately 10 mV. Using a high-
performance silicon process, high gain-bandwidth products are achieved allowing for high-performance, wide
dynamic range design with minimum power dissipation.
Since signals are launched with different SMPTE specified rise and fall times which can vary substantially
(especially at the receive end after going though a wide dynamic range of valid cable lengths) the equalization
routine determines both the bit r ate and the r esultant signal HF at tenuation as opposed to just looking at the launch
edge rates . By det ermining both sets of conditions , it is p ossible to optimiz e the equaliz er for the diff erent rates . F or
example, the M21324 maintains the same maximum cable length as optimized SD only equalizers. An SD signal
through a short cable can have the same edge rate as a HD signal thro ugh a long cable; yet, both conditions
require different levels of equalization as well as different optimiz ed inverse-transfer functions. The advanced
equalization techn ology can make the d istinction between the two cases for optimal performance. This also leads
to proper mute threshold (THRESH) that is independent of the bit rate.
In order to accommodate both the SMPTE worst case equalizer pathological patterns as well as some customer
derived worst case DC offset patterns, a high-gain slicer is included in the signal path to correct for any eye-
crossing wander due to AC coupling of the input. Figure 2-2 shows the test setup used by Mindspeed to evaluate
the performance of the M21324.