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MAX547
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
________________________________________________________________
Maxim Integrated Products
1
441234404142
43
5
21 24 26
25 27 28
22 2319 20
8
9
10
11
12
13
14
15
16
17 29
30
31
32
33
34
35
36
37
38
A1
D11 VOUTD
VSS
REFCD
AGNDCD
AGNDEF
REFEF
VSS
VOUTE
VOUTF
D12
D9
D10
D7
D8
D5
D6
D3
D4
VOUTH
VDD
REFGH
AGNDGH
GND
LDGH
LDEF
D0
D1
D2
A2
WR
CS
LDCD
LDAB
AGNDAB
REFAB
VDD
VOUTA 739 VOUTG
VOUTB
6
18
VOUTC
A0
CLR
MAX547
PLCC
TOP VIEW
VOUTH
VDD
REFGH
AGNDGH
GND
D0
D1
D2
VOUTG
LDEF
LDGH
VOUTA
VDD
REFAB
AGNDAB
LDAB
WR
A2
A1
VOUTB
CS
LDCD
VOUTD
VSS
AGNDEF
REFCD
AGNDCD
CLR
VOUTC
REFEF
VSS
VOUTF
VOUTE
D12
D11
D7
D10
D9
D8
A0
D6
D5
D3
D4
PLASTIC FP
22
21
20
19
18
17
16
15
14
13
12
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
11
10
9
8
7
6
5
4
3
2
1
MAX547
19-0257; Rev 3; 12/95
_________________General Description
The MAX547 contains eight 13-bit, voltage-output digital-to-
analog converters (DACs). On-chip precision output ampli-
fiers provide the voltage outputs. The MAX547 operates
from a ±5V supply. Bipolar output voltages with up to ±4.5V
voltage swing can be achieved with no external compo-
nents. The MAX547 has four separate reference inputs;
each is connected to two DACs, providing different full-
scale output voltages for every DAC pair.
The MAX547 features double-buffered interface logic with a
13-bit parallel data bus. Each DAC has an input latch and a
DAC latch. Data in the DAC latch sets the output voltage. The
eight input latches are addressed with three address lines.
Data is loaded to the input latch with a single write instruction.
An asynchronous load (–
L
—
D
—
_
–) input transfers data from the
input latch to the DAC latch. The four –
L
—
D
—
_
–inputs each control
two DACs, and all DAC latches can be updated simultane-
ously by asserting all –
L
—
D
—
_
–pins. An asynchronous clear (–
C
—
L
—
R
–)
input resets the output of all eight DACs to AGND_. Asserting
–
C
—
L
—
R
–resets both the DAC and the input latch to bipolar zero
(1000hex). On power-up, reset circuitry performs the same
function as –
C
—
L
—
R
–. All logic inputs are TTL/CMOS compatible.
The MAX547 is available in 44-pin plastic quad flat pack
and 44-pin PLCC packages.
________________________Applications
Automatic Test Equipment
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Arbitrary Function Generators
Industrial Process Controls
Avionics Equipment
_____________________________Features
♦Full 13-Bit Performance without Adjustments
♦8 DACs in One Package
♦Buffered Voltage Outputs
♦Calibrated Linearity
♦Guaranteed Monotonic to 13 Bits
♦±5V Supply Operation
♦Unipolar or Bipolar Outputs Swing to ±4.5V
♦Fast Output Settling (5µs to ±
1
⁄
2
LSB)
♦Double-Buffered Digital Inputs
♦Asynchronous Load Inputs Load Pairs of DAC Latches
♦Asynchronous
–
C
—
L
—
R
–
Input Resets DACs to Analog
Ground
♦Power-On Reset Circuit Resets DACs to Analog Ground
♦Microprocessor and TTL/CMOS Compatible
________________Ordering Information
Ordering Information continued at end of data sheet.
*Contact factory for dice specifications.
MAX547ACQH
MAX547BCQH
MAX547ACMH 0°C to +70°C
0°C to +70°C
0°C to +70°C 44 PLCC
44 PLCC
44 Plastic FP
MAX547BCMH 0°C to +70°C 44 Plastic FP
MAX547BC/D 0°C to +70°C Dice*
_______________________________________________________________Pin Configurations
±2
±4
±2
±4
±4
PART TEMP. RANGE
PIN-PACKAGE INL
(LSBs)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, RL= 10kΩ, CL= 50pF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rat-
ings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
VSS to GND...............................................................-6V to +0.3V
Digital Input Voltage to GND......................-0.3V to (VDD + 0.3V)
REF_ ..........................................(AGND_ - 0.3V) to (VDD + 0.3V)
AGND_ .............................................(VSS - 0.3V) to (VDD + 0.3V)
VOUT_ ........................................................................VDD to VSS
Maximum Current into REF_ Pin.......................................±10mA
Maximum Current into Any Other Signal Pin....................±50mA
Continuous Power Dissipation (TA= +70°C)
PLCC (derate 13.33mW/°C above +70°C)...................1067mW
Plastic FP (derate 11.11mW/°C above +70°C )..............889mW
Operating Temperature Ranges
MAX547–C–H.........................................................0°C to +70°C
MAX547–E–H......................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
CONDITIONS
nV-s5Digital Crosstalk
nV-s5Digital Feedthrough
µs5Output Settling Time
V/µs3Voltage-Output Slew Rate
kΩ5RREFReference Input Resistance
V
AGND–VDD
REFReference Input Range
%/%
±0.0025
PSRRPower-Supply Rejection Ratio ±0.0025
Bits13NResolution
LSBBipolar Zero-Code Error ±5 ±20
±0.5 ±2 LSB
±0.5 ±4
INLRelative Accuracy
LSB±1DNLDifferential Nonlinearity
UNITSMIN TYP MAXSYMBOLPARAMETER
To ±1⁄2LSB of full scale (Note 4)
Each REF– pin (Note 3)
(Notes 2, 3)
MAX547A
MAX547B
∆Gain/∆VSS (Note 1)
Guaranteed monotonic
∆Gain/∆VDD (Note 1)
LSB0.3Load Regulation RL = ∞to 10kΩ
LSBGain Error ±1 ±8
STATIC PERFORMANCE—ANALOG SECTION
V
VSS + 0.5
Minimum Output Voltage
V
VDD - 0.5
Maximum Output Voltage
pF10CIN
Input Capacitance
µA1.0IIN
Input Current
V0.8VIL
Input Voltage Low
V2.4VIH
Input Voltage High
(Note 5)
VIN = 0V or VDD
ANALOG OUTPUT
REFERENCE INPUT (Note 2)
DYNAMIC PERFORMANCE—ANALOG SECTION
DIGITAL INPUTS (VDD = 5V ±5%)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
_______________________________________________________________________________________ 3
Note 1: PSRR is tested by changing the respective supply voltage by ±5%.
Note 2: For best performance, REF_ should be greater than AGND_ + 2V and less than VDD - 0.6V. The device operates with
reference inputs outside this range, but performance may degrade. For further information on the reference, see the
Reference and Analog-Ground Inputs
section in the
Detailed Description
.
Note 3: Reference input resistance is code dependent. See
Reference and Analog-Ground Inputs
section in the
Detailed
Description
.
Note 4: Typical settling time with 1000pF capacitive load is 10µs.
Note 5: Guaranteed by design. Not production tested.
Note 6: Guaranteed by supply-rejection test.
TIMING CHARACTERISTICS
(VDD = +5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= TMIN to TMAX, unless otherwise noted.)
14 44
11 40TA= TMIN to TMAX mAISS
Negative Supply Current
CONDITIONS
mAIDD
Positive Supply Current
V-5.25 -4.75VSS
Negative Supply Range
V4.75 5.25VDD
Positive Supply Range
UNITS
MIN TYP MAX
SYMBOLPARAMETER
(Note 6)
(Note 6)
CONDITIONS
ns
0
t6
–
C
—
S
–High to –
W
—
R
– High
ns
0
t5
–
C
—
S
–Low to –
W
—
R
– Low
ns
100
t4
–
C
—
L
—
R
–Pulse Width Low
ns
50
t3
–
L
—
D
—
–
–Pulse Width Low
ns
50
t2
–
W
—
R
– Pulse Width Low
ns
50
t1
–
C
—
S
–Pulse Width Low
UNITSMIN TYP MAXSYMBOLPARAMETER
ns
50
t7
Data Valid to –
W
—
R
–Setup ns
0
t8
Data Valid to –
W
—
R
–Hold ns
10
t9
Address Valid to –
W
—
R
–Setup ns
0
t10
Address Valid to –
W
—
R
–Hold
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, RL= 10kΩ, CL= 50pF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
TA= TMIN to TMAX
POWER SUPPLIES
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
4 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(VDD = 5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= +25°C, unless otherwise noted.)
-36
-30
-24
-18
-12
-6
0
6
0.1 1 10 100 1000 10,000
REFERENCE INPUT SMALL-SIGNAL
FREQUENCY RESPONSE
MAX547-Fg TOC-1
FREQUENCY (kHz)
RELATIVE OUTPUT (dB)
SINE WAVE AT REF–
2V ±100mV
CODE ALL 1s
-20
-15
-10
-5
0
5
10
15
20
-60 -40 -20 0 20 40 60 80 100 120 140
SUPPLY CURRENT
vs. TEMPERATURE
MAX547-Fg TOC-2
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
IDD
ISS
0
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
1 10 100 1000
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
MAX547-Fg TOC-3
FREQUENCY (kHz)
THD + NOISE (%)
REF– = 4Vp-p
INPUT CODE = ALL 1s
0
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
1 10 100 1000
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
MAX547-Fg TOC-4
FREQUENCY (kHz)
THD + NOISE (%)
REF– = 2Vp-p
INPUT CODE = ALL 1s
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.1 1 10 100 1000
REFERENCE FEEDTHROUGH
MAX547-Fg TOC-7
FREQUENCY (kHz)
RELATIVE OUTPUT (dB)
SINE WAVE AT REF_
2V ±2V
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0
1024
2048
3072
4096
5120
6144
7168
8191
RELATIVE ACCURACY
vs. DIGITAL INPUT CODE
MAX547-Fg TOC-5
DIGITAL INPUT CODE (DECIMAL)
RELATIVE ACCURACY (LSB)
-22
-18
-14
-10
-6
-2
0
2
0.1 1 10 100 1000 10,000
REFERENCE INPUT LARGE-SIGNAL
FREQUENCY RESPONSE
MAX547-Fg TOC-6
FREQUENCY (kHz)
RELATIVE OUTPUT (dB)
SINE WAVE AT REF_
2V ±2V
CODE ALL 1s
1
10
100
1000
0.01 0.1 1 10 100
SETTLING TIME
vs. LOAD CAPACITANCE
MAX547-Fg TOC-9
LOAD CAPACITANCE (nF)
SETTLING TIME (µs)
-2
-1
0
1
2
3
01234
5
RELATIVE ACCURACY vs.
REFERENCE VOLTAGE
MAX547-Fg TOC-11
REFERENCE VOLTAGE (V)
RELATIVE ACCURACY (LSB)
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
110
100 1000
FULL-SCALE ERROR
vs. LOAD RESISTANCE
MAX547-Fg TOC-8
LOAD RESISTANCE (kΩ)
ERROR (LSB)
NEGATIVE
FULL-SCALE
POSITIVE
FULL-SCALE
REF_ = 4.096V
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
_______________________________________________________________________________________
5
POSITIVE SETTLING TIME TO FULL-SCALE STEP
(ALL BITS OFF TO ALL BITS ON)
DIGITAL
INPUTS
(5V/div)
OUTPUT
(1mV/div)
2µs/div
REF– = 4.096V, CL = 100pF, RL = 5kΩ
NEGATIVE SETTLING TIME TO FULL-SCALE STEP
(ALL BITS ON TO ALL BITS OFF)
DIGITAL
INPUTS
(5V/div)
OUTPUT
(1mV/div)
2µs/div
REF– = 4.096V, CL = 100pF, RL = 5kΩ
DYNAMIC RESPONSE
(ALL BITS OFF, ON, OFF)
DIGITAL
INPUTS
(5V/div)
OUTPUT
(2V/div)
2µs/div
REF– = 4.096V, CL = 100pF, RL = 5kΩ
DIGITAL FEEDTHROUGH
(GLITCH IMPULSE)
200ns/div
+5V
0V
10mV
0V
-10mV
TOP: DIGITAL TRANSITION ON ALL DATA BITS
BOTTOM: DAC OUTPUT WITH WR HIGH 10mV/div
____________________________Typical Operating Characteristics (continued)
(VDD = 5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= +25°C, unless otherwise noted.)
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX547-Fg TOC-10
FREQUENCY (kHz)
PSRR (dB)
VSS VDD
VDD = VSS = 5V ±200mV
NO LOAD
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
6 _______________________________________________________________________________________
PLCC NAME
1–
C
—
L
—
R
–Clear Input (active low). Driving this asynchronous input low sets the content of all latches to
1000hex. All DAC outputs are reset to AGND_.
3 REFCD Reference Voltage Input for DAC C and DAC D. Bypass to AGNDCD with a 0.1µF to 1µF capacitor.
2AGNDCD Analog Ground for DAC C and DAC D
7 VOUTB DAC B Output Voltage
6 VOUTC DAC C Output Voltage
5 VOUTD DAC D Output Voltage
4, 42 VSS Negative Power Supply, -5V (2 pins). Connect both pins to the supply voltage. Bypass each pin
to the system analog ground with a 0.1µF to 1µF capacitor.
FLAT
PACK
PIN
39
41
40
1
44
43
42, 36
FUNCTION
8 VOUTA DAC A Output Voltage2
9, 37 VDD Positive Power Supply, 5V (2 pins). Connect both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1µF to 1µF capacitor.
3, 31
10 REFAB Reference Voltage Input for DAC A and DAC B. Bypass to AGNDAB with a 0.1µF to 1µF capacitor.4
11 AGNDAB Analog Ground for DAC A and DAC B5
12 –
L
—
D
—
A
—
B
–Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
A and B to the respective DAC latches.
6
13 –
L
—
D
—
C
—
D
–Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
C and D to the respective DAC latches.
7
14 –
C
—
S
–Chip Select (active low)8
15 –
W
—
R
–Write Input (active low). –
W
—
R
–, along with –
C
—
S
–, loads data into the DAC input latch selected by A0–A2.
9
ADJACENT-CHANNEL CROSSTALK
A: DIGITAL INPUTS, DAC A, DATA BITS from ALL Os to OAAAhex
B: OUTPUT, DAC B
500ns/div
REF– = 4.096V, CL = 50pF, RL = 10kΩ
A
5V/div
B
5mV/div
ADJACENT-CHANNEL CROSSTALK
A: DIGITAL INPUTS, DAC A, DATA BITS from OAAAhex to ALL Os
B: OUTPUT, DAC B
500ns/div
REF– = 4.096V, CL = 50pF, RL = 10kΩ
A:
5V/div
B:
5mV/div
______________________________________________________________Pin Description
____________________________Typical Operating Characteristics (continued)
(VDD = 5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= +25°C, unless otherwise noted.)
Analog Ground for DAC E and DAC F
_______________Detailed Description
Analog Section
The MAX547 contains eight 13-bit, voltage-output
DACs. These DACs are “inverted” R-2R ladder net-
works that convert 13-bit digital inputs into equivalent
analog output voltages, in proportion to the applied ref-
erence voltages. The MAX547 has one reference input
(REF_) and one analog-ground input (AGND_) for each
pair of DACs. The four REF_ inputs allow different full-
scale output voltages for each DAC pair, and the four
AGND_ inputs allow different offset voltages for each
DAC pair.
The DAC ladder outputs are buffered with op amps that
operate with a gain of two. The inverting node of the
amplifier is connected to the respective reference
input, resulting in bipolar output voltages from -REF_ to
4095/4096 REF_. Figure 1 shows the simplified DAC
circuit.
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
_______________________________________________________________________________________ 7
_________________________________________________Pin Description (continued)
FLAT
PACK
PLCC NAME FUNCTION
36 REFGH Reference Voltage Input for DAC G and DAC H. Bypass to AGNDGH with a 0.1µF to 1µF capacitor.30
16 A2 Address Bit 2
38 VOUTH DAC H Output Voltage
33 –
L
—
D
—
G
—
H
–Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
G and H to the respective DAC latches.
32
35 AGNDGH Analog Ground for DAC G and DAC H
34 GND Digital Ground
PIN
10
27
29
28
41 VOUTE DAC E Output Voltage35
39 VOUTG DAC G Output Voltage33
40 VOUTF DAC F Output Voltage34
44 AGNDEF38
Figure 1. DAC Simplified Circuit Diagram
2R 2R
R
D0 D10 D11 D12
RR
RR
OUT
REF–
AGND–
2R 2R 2R
VDAC
43 REFEF Reference Voltage Input for DAC E and DAC F. Bypass to AGNDEF with a 0.1µF to 1µF capaci-37
32 –
L
—
D
—
E
—
F
–Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
E and F to the respective DAC latches.
26
17 A1 Address Bit 111
18 A0 Address Bit 0
19–31 D12–D0 Data Bits 12–013–25
12
Reference and Analog-Ground Inputs
The REF_ inputs can range between AGND_ and VDD.
However, the DAC outputs will operate to VDD - 0.6V
and VSS + 0.6V, due to the output amplifiers’ voltage-
swing limitations. The AGND_ inputs can be offset by
any voltage within the supply rails. The offset-voltage
potential must be lower than the reference-voltage
potential. For more information, refer to the
Digital Code
and
Analog Output Voltage
section in the
Applications
Information.
The input impedance of the REF_ inputs is code depen-
dent. It is at its lowest value (5kΩmin) when the input
code of the referring DAC pair is 0 1010 1010 1010
(0AAAhex). Its maximum value, typically 50kΩ, occurs
when the code is 0000hex. When all reference inputs are
driven from the same source, the minimum load imped-
ance is 1.25kΩ. Since the input impedance at REF_ is
code dependent, load regulation of the reference used is
important. For more information, see
Reference
Selection
in the
Applications Information
section.
The input capacitance at REF_ is also code dependent,
and typically varies from 125pF to 300pF. Its minimum
value occurs when the code of the referring DAC pair is
set to all 0s. It is at its maximum value with all 1s on both
DACs.
Output Buffer Amplifiers
The MAX547’s voltage outputs are internally buffered
by precision gain-of-two amplifiers with a typical slew
rate of 3V/µs. With a full-scale transition at its output,
the typical settling time to ±1⁄2LSB is 5µs when loaded
with 10kΩin parallel with 50pF, or 6µs when loaded
with 10kΩin parallel with 100pF.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and
CMOS logic. The MAX547 interfaces with microproces-
sors using a data bus at least 13 bits wide. The inter-
face is double buffered, allowing simultaneous update
of all DACs. There are two latches for each DAC (see
Functional Diagram
): an input latch that receives data
from the data bus, and a DAC latch that receives data
from the input latch. Address lines A0, A1, and A2
select which DAC’s input latch receives data from the
data bus, as shown in Table 1. Transfer data from the
input latches to the DAC latches by asserting the asyn-
chronous LD_ signal. Each DAC’s analog output
reflects the data held in its DAC latch. All control inputs
are level triggered.
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch and LD_ transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low, and
the DAC latch is transparent when LD_ is low. The
address lines (A0, A1, A2) must be valid throughout the
time CS and WR are low (Figure 3). Otherwise, the data
can be inadvertently written to the wrong DAC. Data is
latched within the input latch when either CS or WR is
high. Taking LD_ high latches data into the DAC latches.
If LD_ is brought low when WR and CS are low, it must
be held low for t3or longer after WR and CS are high
(Figure 3).
Pulling the asynchronous CLR input low sets all DAC
outputs to a nominal 0V, regardless of the state of CS,
WR, and LD_. Taking CLR high latches 1000hex into
all input latches and DAC latches.
Table 1. MAX547 DAC Addressing
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
8 _______________________________________________________________________________________
TO INPUT LATCH OF DAC H
TO INPUT LATCH OF DAC G
TO INPUT LATCH OF DAC F
TO INPUT LATCH OF DAC E
TO INPUT LATCH OF DAC D
TO INPUT LATCH OF DAC C
TO INPUT LATCH OF DAC B
TO INPUT LATCH OF DAC A
TO DAC LATCHES OF DAC G AND DAC H
TO DAC LATCHES OF DAC E AND DAC G
TO DAC LATCHES OF DAC C AND DAC D
TO DAC LATCHES OF DAC C AND DAC B
TO ALL INPUT AND DAC LATCHES
A2
A1
A0
LDGH
LDEF
LDCD
LDAB
CLR
WR
CS
Figure 2. Input Control Logic
A0A2 FUNCTION
00 DAC A input latch
10 DAC D input latch
10 DAC B input latch
00 DAC C input latch
0
A1
0
1
0
1
DAC E input latch
11 DAC F input latch
1
0
001 DAC G input latch1 11 DAC H input latch1
_______________________________________________________________________________________ 9
__________Applications Information
Multiplying Operation
The MAX547 can be used for multiplying applications.
Its reference accepts both DC and AC signals. The volt-
age at each REF_ input sets the full-scale output voltage
for its respective DACs. Since the reference inputs
accept only positive voltages, multiplying operation is
limited to two quadrants. Do not bypass the reference
inputs when applying AC signals to them. Refer to the
graphs in the
Typical Operating Characteristics
for
dynamic performance of the DACs and output buffers.
Digital Code and Analog Output Voltage
The MAX547 uses offset binary coding. A 13-bit twos-
complement code can be converted to a 13-bit offset
binary code by adding 212 = 4096.
Bipolar Output Voltage Range (AGND_ = 0V)
For symmetrical bipolar operation, tie AGND_ to the
system ground. Table 3 shows the relationship between
digital code and output voltage. The following para-
graphs give a detailed explanation of this mode.
The DAC ladder output voltage (VDAC) is multiplied by
2 and level shifted by the reference voltage, which is
internally connected to the output amplifiers (Figure 1).
Since the feedback resistors are the same size, the
amplifier’s output voltage is 2 times the voltage at its
noninverting input, minus the reference voltage.
where VDAC is the voltage at the amplifier’s noninvert-
ing input (DAC ladder output voltage), and REF_ is the
voltage applied to the reference input of the DAC.
With AGND_ connected to the system ground, the DAC
ladder output voltage is:
where D is the numeric value of the DAC’s binary input
code and n is the DAC’s resolution (13 bits). Replace
VDAC in the equation and calculate the output voltage.
D ranges from 0 (20) to 8191 (213 - 1).
1LSB REF–1
4096
=
VOUT_ 2 D
2 REF– REF–
= REF– D
2–1 REF–D
4096 –1
13
12
=
()
−
=
VD
2
(REF–)D
2 (REF–)
DAC n13
==
VOUT 2(V ) REF–
DAC
=−
Table 2. Interface Truth Table
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
–
C
—
L
—
R
–FUNCTION
1 Both latches transparent
1 Both latches latched
1 Both latches latched
–
L
—
D
—
–
–
0
1
1
1 Input latch transparent
1 Input latch latched
1 Input latch latched
X
X
X
–
W
—
R
–
0
0
1
X
–
C
—
S
–
0
1
X
1
X
0
X
1
X0 All input and DAC latches at
1000hex, outputs at AGND–
XX
X1 DAC latch transparentX0
CS
WR
A0–A2
D0–D12
LD–
NOTES:
1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF
+5V. tr = tf = 5ns.
2. MEASUREMENT REFERENCE LEVEL IS
(VINH + VINL)/2.
3. IF LD– IS ACTIVATED WHILE WR IS LOW THEN LD– MUST STAY LOW
FOR t3 OR LONGER AFTER WR GOES HIGH.
t1
t2
t9t10
t7t8
t5t6
t3
t3
Figure 3. Write-Cycle Timing
10 ______________________________________________________________________________________
MAX547
Positive Unipolar Output Voltage Range
(AGND_ = REF_/2)
For positive unipolar output operation, set AGND_ to
(REF_/2). For example, if you use Figure 4’s circuit with,
a 4.096V reference and offset AGND_ by 2.048V with
matched resistors (R1 = R2) and an op amp, it results in
a 0V to 4.0955V (nominal) unipolar output voltage,
where 1LSB = 500µV. In general, the maximum current
flowing out of any AGND_ pin is given by:
Customizing the Output Voltage Range
The AGND_ inputs can be offset by any voltage within the
supply rails if the voltage at the referring REF_ input is
higher than the voltage at the AGND_ input. Select the
reference voltage and the voltage at AGND_ so the
resulting output voltages do not come within ±0.6V of the
supply rails. Figure 4’s circuit shows one way to add posi -
tive offset to AGND_; make sure that the op amp used
has sufficient current-sink capability to take up the
remaining AGND_ current:
Another way is to digitally offset AGND_ by connecting
the output of one DAC to one or more AGND_ inputs. Do
not connect a DAC output to its own AGND_ input.
Table 5 summarizes the relationship between the refer-
ence and AGND_ potentials and the output voltage in
the different modes of operation.
Power-Supply Sequencing
The sequence in which the supply voltages come up is
not critical. However, we recommend that on power-up,
VSS comes up first, VDD next, followed by the reference
voltages. If you use other sequences, limit the current
into any reference pin to 10mA. Also, make sure that
VSS is never more than 300mV above ground. If there is
a risk that this can occur at power-up, connect a
Schottky diode between VSS and GND, as shown in
Figure 5. We recommend that you not power up the
logic input pins before establishing the supply volt-
ages. If this is not possible and the digital lines can
drive more than 10mA, you should place current-limit-
ing resistors (e.g., 470Ω) in series with the logic pins.
Reference Selection
If you want a ±2.5V full-scale output voltage swing, you
can use the MAX873 reference. It operates from a sin-
gle 5V supply and is specified to drive up to 10mA.
Therefore, it can drive all four reference inputs simulta-
neously. Because the maximum load impedance can
vary from 1.25kΩto 12.5kΩ(four reference inputs in
parallel), the reference load current ranges from 2mA to
0.2mA (1.8mA maximum load step). The MAX873’s
IREF_ AGND_
5k
AGND_ =
−Ω
IREF_ AGND_
5k
AGND_ =
−Ω
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
OUTPUTINPUT
4095
+REF_
(
———
)
4096
1 1111 1111 1111
0V1 0000 0000 0000
1
+REF_
(
———
)
4096
1 0000 0000 0001
1
-REF_
(
———
)
4096
0 1111 1111 1111
4095
-REF_
(
———
)
4096
0 0000 0000 0001
-REF_0 0000 0000 0000
+5V
1µF
REFAB
AGNDAB
1µF
R1
REF
R2
VDD VDD
DIGITAL INPUTS NOT SHOWN.
NOT ALL DACS SHOWN.
1µF
VOUTA
VOUTB
DAC B
DAC A
MAX547
-5V
VSS VSS
1µF1µF
+REF–/21 0000 0000 0000
OUTPUT
0V0 0000 0000 0000
INPUT
8191
+REF_
(
———
)
8192
1 1111 1111 1111
Table 4. MAX547 Positive Unipolar Code Table
(AGND_ = REF
_)
2
Table 3. MAX547 Bipolar Code Table
(AGND_ = 0V)
Figure 4. Offsetting AGND–
load regulation is specified to 20ppm/mA max over
temperature, resulting in a maximum error of 36ppm
(90µV). This corresponds to a maximum error caused
by reference load regulation of only 0.147LSB
[0.147LSB = 90µV/(5V/8192)LSB] over temperature.
If you want a ±4.096V full-scale output swing (1LSB =
1mV), you can use the calibrated, low-drift, low-dropout
MAX676. Operating from a 5V supply, it is fully speci-
fied to drive two REF_ inputs with less than 60.4µV error
(0.0604LSB) over temperature, caused by the maxi-
mum load step.
Reference Buffering
Another way to obtain high accuracy is to buffer a refer-
ence with an op amp. When driving all reference inputs
simultaneously, keep the closed-loop output imped-
ance of the op amp below 0.03Ωto ensure an error of
less than 0.1LSB. The op amp must also drive the
capacitive load (typically 500pF to 1200pF).
Each reference input can also be buffered separately
by using the circuit in Figure 6. A reference load step
caused by a digital transition only affects the DAC pair
where the code transition occurs. It also allows the use
of references with little drive capability. Keep the
closed-loop output impedance of each op amp below
0.12Ω, to ensure an error of less than 0.1LSB. Figure 6
shows the op amp’s inverting input directly connected
to the MAX547’s reference terminal. This eliminates the
influence of board lead resistance by sensing the volt-
age with a low-current path sense line directly at the
reference input.
Adding feedback resistors to individual reference
buffer amplifiers enables different reference voltages to
be generated from a single reference.
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
______________________________________________________________________________________ 11
Figure 5. Optional Schottky Diode between VSS and GND
GND
VSS
SYSTEM GND
1N5817
MAX547
VSS
BIPOLAR OPERATION
(AGND_ = 0V) CUSTOM OPERATION
POSITIVE UNIPOLAR
OPERATION
(AGND_ = REF_/2)
PARAMETER
AGND_ (=0V) AGND–
Bipolar Zero Level, or
Unipolar Mid-scale,
(Code = 1000000000000)
REF–REF–- AGND–
REF–/2
Differential Reference Voltage
(VDR)
REF_
AGND–
(
= ———
)
2
-REF–AGND–- VDR
0V
Negative Full-scale Output
(Code = All 0s)
4095
(
———
)(
REF_
)
4096 4095
AGND _ +
(
———
)(
VDR
)
4096
8191
(
———
)(
REF_
)
8192
Positive Full-Scale Output
(Code = All 1s)
REF_
———
4096 VDR
———
4096
REF_
(
———
)
8192
LSB Weight
D
(
——— - 1
)(
REF_
)
4096 D
AGND _ +
(
—--—- - 1
)(
VDR
)
4096
D
(
———
)(
REF_
)
8192
VOUT–as a Function of
Digital Code (D, 0 to 8191)
Table 5. Reference, AGND– and Output Relationships
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
12 ______________________________________________________________________________________
Power-Supply Bypassing and
Ground Management
For optimum performance, use a multilayer PC board
with an unbroken analog ground. For normal opera-
tion, when all AGND_ pins are at the same potential,
connect the four AGND_ pins directly to the ground
plane or connect them together in a “star” configura-
tion. The center of this star point is a good location to
connect the digital system ground with the analog
ground.
If you are using a single common reference voltage,
you can connect the reference inputs together using a
“star” configuration. If you are using DC reference volt-
ages, bypass each reference input with a 0.1µF to 1µF
capacitor to AGND_.
MAX547
MAX494
+
-
REFAB
REFCD
REFEF
REFGH
Figure 6. Reference Buffering
MAX547AEQH -40°C to +85°C 44 PLCC
MAX547BEQH -40°C to +85°C 44 PLCC
MAX547AEMH -40°C to +85°C 44 Plastic FP
MAX547BEMH -40°C to +85°C 44 Plastic FP
±2
±4
±2
±4
PART TEMP. RANGE
PIN-PACKAGE INL
(LSBs)
_Ordering Information (continued)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
______________________________________________________________________________________ 13
VDD REFCDREFAB REFEF REFGH
9, 37 10 3 43 36
VSS GND
DAC
LATCH A
8
11
7
VOUTA
AGNDAB
VOUTB
DAC B
INPUT
LATCH A
DAC
LATCH B
DAC A
INPUT
LATCH B
DAC
LATCH C
6
2
5
VOUTC
AGNDCD
VOUTD
DAC D
D12–D0
INPUT
LATCH C
DAC
LATCH D
DAC C
INPUT
LATCH D
DAC
LATCH E
41
44
40
VOUTE
AGNDEF
VOUTF
DAC F
INPUT
LATCH E
DAC
LATCH F
DAC E
INPUT
LATCH F
DAC
LATCH G
39
35
38
VOUTG
AGNDGH
VOUTH
DAC H
Pin numbers shown for PLCC package.
4, 42 34
12, 1316, 18 32, 33 1
INPUT
LATCH G
DAC
LATCH H
DAC G
INPUT
LATCH H
A0–A2 CLRLDAB
LDCD
LDEF
LDGH
CS
WR
14
15
MAX547
CONTROL
LOGIC
DATA BUS
_________________________________________________________Functional Diagram
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
14 ______________________________________________________________________________________
VOUTA
VOUTC
0.242"
(6.147mm)
0.199"
(5.055mm)
A0
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
AGNDAB
LDAB
LDCD
CS
A1
A2
WR
VDD
REFAB
VOUTB
VOUTH
AGNDGH
GND
LDGH
LDEF
D2
D1
D0
VDD
VOUTG
REFGH
VOUTD
REFCD
AGNDCD
CLR
VOUTE
VOUTF
VSS
VSS
AGNDEF
REFEF
____________________________________________________________Chip Topography
TRANSISTOR COUNT: 8987
SUBSTRATE CONNECTED TO VDD
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
______________________________________________________________________________________ 15
________________________________________________________Package Information
DIM
A
A1
A2
A3
B
B1
C
D
D1
D2
D3
e
MIN
0.165
0.100
0.145
0.020
0.013
0.026
0.009
0.685
0.650
0.590
MAX
0.180
0.110
0.156
–
0.021
0.032
0.011
0.695
0.655
0.630
MIN
4.19
2.54
3.68
0.51
0.33
0.66
0.23
17.40
16.51
14.99
MAX
4.57
2.79
3.96
–
0.53
0.81
0.28
17.65
16.64
16.00
INCHES MILLIMETERS
44-PIN PLASTIC
LEADED CHIP
CARRIER
PACKAGE
21-350A
DD1
D
D1
D3
D2
e
B1 B
A3
A
A1
A2
12.70 REF0.500 REF 1.27 REF0.050 REF
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
