Revised July 2001 DM9602 Dual Retriggerable, Resettable One Shots General Description Features These dual resettable, retriggerable one shots have two inputs per function; one which is active HIGH, and one which is active LOW. This allows the designer to employ either leading-edge or trailing-edge triggering, which is independent of input transition times. When input conditions for triggering are met, a new cycle starts and the external capacitor is allowed to rapidly discharge and then charge again. The retriggerable feature permits output pulse widths to be extended. In fact a continuous true output can be maintained by having an input cycle time which is shorter than the output cycle time. The output pulse may then be terminated at any time by applying a LOW logic level to the RESET pin. Retriggering may be inhibited by either connecting the Q output to an active HIGH input, or the Q output to an active LOW input. 70 ns to output width range Resettable and retriggerable--0% to 100% duty cycle TTL input gating--leading or trailing edge triggering Complementary TTL outputs Optional retrigger lock-out capability Pulse width compensated for VCC and temperature variations Ordering Code: Order Number Package Number DM9602N N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Logic Diagrams Function Table Pin Numbers A Operation B CLR HL L H Trigger H LH H Trigger X X L Reset H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care (c) 2001 Fairchild Semiconductor Corporation DS006611 www.fairchildsemi.com DM9602 Dual Retriggerable, Resettable One Shots August 1986 DM9602 Operating Rules 1. An external resistor (RX) and external capacitor (CX) are required as shown in the Logic Diagram. This configuration is not recommended with retriggerable operation. 5. To obtain variable pulse width by remote trimming, the following circuit is recommended: 2. The value of CX may vary from 0 to any necessary value available. If, however, the capacitor has leakages approaching 3.0 A or if stray capacitance from either terminal to ground is more than 50 pF, the timing equations may not represent the pulse width obtained. 3. The output pulse with (t) is defined as follows: where: 6. Under any operating condition, CX and RX (min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup. RX is in k, CX is in pF 7. Input Trigger Pulse Rules (See Triggering Truth Table) t is in ns for CX < 10 pF, see Figure 1. 3 for K vs. CX see Figure 6. 4. If electrolytic type capacitors are to be used, the following three configurations are recommended: Input to Pin 5(11), 1. Use with low leakage capacitors: (Pin 3(13) = HIGH) Pin 4(12) = LOW t1, t3 = Min. Positive Input Pulse Width > 40 ns The normal RC configuration can be used predictably only if the forward capacitor leakage at 5.0V is less than 3 A, and the inverse capacitor leakage at 1.0V is less than 5 A over the operational temperature range. t2, t4 = Min. Negative Input Pulse Width > 40 ns Input to Pin 4(12) (Pin 3(13) = HIGH) Pin 5(11) = HIGH R < 0.6 RX (Max) 8. The retriggerable pulse width is calculated as shown below: 2. Use with high inverse leakage current electrolytic capacitors: The diode in this configuration prevents high inverse leakage currents through the capacitor by preventing an inverse voltage across the capacitor. The use of this configuration is not recommended with retriggerable operation. t 0.3 RCX The retrigger pulse width is equal to the pulse width (t) plus a delay time. For pulse widths greater than 500 ns, tW can be approximated as t. Retriggering will not occur if the retrigger pulse comes within 0.3 CX (ns) after the initial trigger pulse (i.e., during the discharge cycle). 9. Reset Operation--An overriding clear (active LOW level) is provided on each one shot. By applying a LOW to the reset, any timing cycle can be terminated or any new cycle inhibited until the LOW reset input is removed. Trigger inputs will not produce spikes in the output when the reset is held LOW. 3. Use to obtain extended pulse widths: This configuration can be used to obtain extended pulse widths, because of the larger timing resistor allowed by beta multiplication. Electrolytics with high inverse leakage currents can be used. R < RX (0.7) (hFE Q1) or < 2.5 M, whichever is the lesser RX (min) < RY < RX (max) (5 k RY 10 k is recommended) Q1: NPN silicon transistor with hFE requirements of above equations, such as 2N5961 or 2N5962. 10. VCC and Ground wiring should conform to good high frequency standards so that switching transients on VCC and Ground leads do not cause interaction between one shots. Use of a 0.01 to 0.1 F bypass capacitor between VCC and Ground located near the DM9602 is recommended. t 0.3 RCX Note 1: For further detailed device characteristics and output performance, please refer to the NSC one-shot application note, AN-366. www.fairchildsemi.com 2 DM9602 Typical Performance Characteristics FIGURE 4. Normalized Output Pulse Width vs. Supply Voltage FIGURE 1. Output Pulse Width vs. Timing Resistance and Capacitance for CX < 103 pF FIGURE 5. Minimum Output Pulse Width vs. Ambient Temperature FIGURE 2. Normalized Output Pulse Width vs. Ambient Temperature FIGURE 6. Typical "K" Coefficient Variation vs. Timing Capacitance FIGURE 3. Pulse Width vs. Timing Resistor 3 www.fairchildsemi.com DM9602 Absolute Maximum Ratings(Note 2) Supply Voltage Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0C to +70C Operating Free Air Temperature Range -65C to +150C Storage Temperature Range Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VIH HIGH Level Min Nom Max Units 4.75 5 5.25 V TA = -55C TA = 0C Input Voltage 1.9 TA = 25C 1.8 TA = 75C 1.65 V TA = 125C VIL TA = -55C LOW Level Input Voltage TA = 0C 0.85 TA = 25C 0.85 TA = 75C 0.85 V TA = 125C IOH HIGH Level Output Current -0.8 mA IOL LOW Level Output Current 16 mA TA Free Air Operating Temperature 75 C 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions (Note 3) VI Input Clamp Voltage VCC = Min, II = -12 mA VOH HIGH Level VCC = Min, IOH = Max VOL Output Voltage VIL = Max, VIH = Min (Note 5) LOW Level VCC = Min, IOL = Max Min Typ (Note 4) Max Units -1.5 V 2.4 V 0.45 V 60 A Output Voltage VIL = Max, VIH = Min (Note 5) IIH HIGH Level Input Current VCC = Max, VI = 4.5V IIL LOW Level VCC = Max VI = 0.45V -1.6 Input Current VCC = Min VI = 0.45V -1.41 IOS Short Circuit Output Current VCC = Max, VOUT = 1V (Note 5)(Note 6) ICC Supply Current VCC = Max 39 mA -35 mA 50 mA Note 3: Unless otherwise noted, RX = 10k for all tests. Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Ground PIN 1(15) for VOL on PIN 7(9) or VOH and IOS on PIN 6(10) and apply momentary ground to PIN 4(12). Open PIN 1(15) for VOL on PIN 6(10) or VOH and IOS on PIN 7(9). Note 6: Not more than one output should be shorted at a time. www.fairchildsemi.com 4 VCC = 5V, TA = 25C Symbol tPLH tPHL tPW(MIN) Parameter Conditions Propagation Delay Time, Negative Trigger Input CL = 15 pF LOW-to-HIGH Level Output to True Output CX = 0 Propagation Delay Time, Negative Trigger Input RX = 5 k HIGH-to-LOW Level Output To Complement Output Min Minimum True Output 48 ns 110 Pulse Width RX = 10 k Pulse Width CX = 1000 pF Maximum Allowable Wiring 3.08 Pins 2, 14 to GND Capacitance RX ns ns Minimum Complement CSTRAY Units 40 100 Pulse Width tPW Max External Timing Resistor 5 5 3.76 s 50 pF 50 k www.fairchildsemi.com DM9602 Switching Characteristics DM9602 Dual Retriggerable, Resettable One Shots Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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