MOTOROLA Order this document by MCM54260B/D SEMICONDUCTOR TECHNICAL DATA MCM54260B MCM5L4260B MCM5S4260B Advance Information 256K x 16 CMOS Dynamic RAM Fast Page Mode - 2 CAS, 1 Write Enable The MCM54260B is a 0.6 CMOS high-speed dynamic random access memory. It is organized as 262,144 sixteen-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost. The MCM54260B requires only 9 address lines; row and column address inputs are multiplexed. The device is packaged in a standard 400 mil SOJ plastic package and a 400 mil thin-small-outline package (TSOP). * * * * * * * * * * * Three-State Data Output Fast Page Mode TTL-Compatible Inputs and Outputs RAS-Only Refresh CAS Before RAS Refresh Hidden Refresh 512 Cycle Refresh: MCM54260B = 8 ms MCM5L4260B = 64 ms MCM5S4260B = 64 ms Fast Access Time (tRAC): MCM54260B-70, MCM5L4260B-70, and MCM5S4260B-70 = 70 ns (Max) MCM54260B-80, MCM5L4260B-80, and MCM5S4260B-80 = 80 ns (Max) MCM54260B-10, MCM5L4260B-10, and MCM5S4260B-10 = 100 ns (Max) Low Active Power Dissipation: MCM54260B-70, MCM5L4260B-70, and MCM5S4260B-70 = 550 mW (Max) MCM54260B-80, MCM5L4260B-80, and MCM5S4260B-80 = 468 mW (Max) MCM54260B-10, MCM5L4260B-10, and MCM5S4260B-10 = 413 mW (Max) Low Standby Power Dissipation: MCM54260B, MCM5L4260B, and MCM5S4260B= 5.5 mW (Max, TTL Levels) Battery Backup Power Dissipation: MCM5L4260B and MCM5S4260B = 1.7 mW (Max, Battery Backup Mode, tRC = 125 s) J PACKAGE 400 MIL SOJ CASE 923A-01 T PACKAGE 400 MIL TSOP CASE 924-01 PIN NAMES A0 - A8 . . . . . . . . . . . . . . Address Inputs DQ0 - DQ15 . . . . . . . Data Input/Output W . . . . . . . . . . . . . . . . Read/Write Enable RAS . . . . . . . . . . . . Row Address Strobe LCAS, UCAS . Column Address Strobe VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connect G . . . . . . . . . . . . . . . . . . . Output Enable This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 3 10/95 Motorola, Inc. 1995 MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 1 PIN ASSIGNMENTS 400 MIL SOJ 400 MIL TSOP VCC 1 40 VSS VCC 1 44 VSS DQ0 2 39 DQ15 DQ0 2 43 DQ15 DQ1 3 38 DQ14 DQ1 3 42 DQ14 DQ2 4 37 DQ13 DQ2 4 41 DQ13 DQ3 5 36 DQ12 DQ3 5 40 DQ12 VCC 6 35 VSS VCC 6 39 VSS DQ4 7 34 DQ11 DQ4 7 38 DQ11 DQ5 8 33 DQ10 DQ5 8 37 DQ10 DQ6 9 32 DQ9 DQ6 9 36 DQ9 DQ7 10 31 DQ8 DQ7 10 35 DQ8 NC 11 30 NC NC 12 29 LCAS W 13 28 UCAS NC 13 32 NC RAS 14 27 G NC 14 31 LCAS NC 15 26 A8 W 15 30 UCAS A0 16 25 A7 RAS 16 29 G A1 17 24 A6 NC 17 28 A8 A2 18 23 A5 A0 18 27 A7 A3 19 22 A4 A1 19 26 A6 VCC 20 21 VSS A2 20 25 A5 A3 21 24 A4 VCC 22 23 VSS MCM54260B*MCM5L4260B*MCM5S4260B 2 MOTOROLA DRAM BLOCK DIAGRAM DQ1 DQ3 DQ5 DQ0 VCC DQ7 DQ9 DQ11 DQ13 DQ15 DQ2 DQ4 DQ6 DQ8 DQ10 DQ12 DQ14 VSS G 8 VOLTAGE DOWN CONVERTER 8 DATA IN BUFFERS DATA OUT BUFFERS 8 WRITE UCAS 8 VCC 8 DATA OUT BUFFERS DATA IN BUFFERS 8 8 NO. 2 CLOCK GENERATOR LCAS 9 A0 8 COLUMN ADDRESS BUFFERS (9) 9 COLUMN DECODER SENSE AMP I/O GATE A1 16 REFRESH CONTROLLER A2 A3 512 x 16 A4 A6 9 9 A7 9 A8 ROW ADDRESS BUFFERS (9) ROW DECODER REFRESH COUNTER (9) A5 512 MEMORY ARRAY 512 x 512 x 16 SUBSTRATE BIAS GENERATOR RAS VSS VCC NO. 1 CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit VCC - 1 to + 7 V Vin, Vout - 1 to + 7 V Data Out Current Iout 50 mA Power Dissipation PD 700 mW Operating Temperature Range TA 0 to + 70 C Tstg - 55 to + 150 C Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Storage Temperature Range This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 3 DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS) Parameter Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 Logic High Voltage, All Inputs VIH 2.4 -- 6.0 V Logic Low Voltage, All Inputs Except DQ0 - DQ15 VIL - 0.5* -- 0.8 V Logic Low Voltage, DQ0 - DQ15 VIL - 0.5* -- 0.8 V Supply Voltage (Operating Voltage Range) *- 2.0 V at pulse width 20 ns DC CHARACTERISTICS Characteristic Symbol VCC Power Supply Current MCM54260B-70, MCM5L4260B-70, and MCM5S4260B-70, tRC = 130 ns MCM54260B-80, MCM5L4260B-80, and MCM5S4260B-80, tRC = 150 ns MCM54260B-10, MCM5L4260B-10, and MCM5S4260B-10, tRC = 180 ns ICC1 VCC Power Supply Current (Standby) (RAS = CAS = VIH) ICC2 VCC Power Supply Current During RAS Only Refresh Cycles (CAS = VIH) MCM54260B-70, MCM5L4260B-70, and MCM5S4260B-70, tRC = 130 ns MCM54260B-80, MCM5L4260B-80, and MCM5S4260B-80, tRC = 150 ns MCM54260B-10, MCM5L4260B-10, and MCM5S4260B-10, tRC = 180 ns ICC3 VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL) MCM54260B-70, MCM5L4260B-70, and MCM5S4260B-70, tPC = 45 ns MCM54260B-80, MCM5L4260B-80, and MCM5S4260B-80, tPC = 50 ns MCM54260B-10, MCM5L4260B-10, and MCM5S4260B-10, tPC = 60 ns ICC4 VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V) MCM54260B MCM5L4260B MCM5S4260B ICC5 VCC Power Supply Current During CAS Before RAS Refresh Cycle MCM54260B-70, MCM5L4260B-70, and MCM5S4260B-70, tRC = 130 ns MCM54260B-80, MCM5L4260B-80, and MCM5S4260B-80, tRC = 150 ns MCM54260B-10, MCM5L4260B-10, and MCM5S4260B-10, tRC = 180 ns ICC6 VCC Power Supply Current, Battery Backup Mode--MCM5L4260B and MCM5S4260B (tRC = 125 s; tRAS = 1 s; CAS = CAS Before RAS Cycle or 0.2 V; A0 - A8, W, D = VCC - 0.2 V or 0.2 V) Min Max -- -- -- 100 85 75 -- 2 -- -- -- 100 85 75 -- -- -- 70 60 55 -- -- -- 1.0 200 200 -- -- -- 100 85 75 ICC7 -- Input Leakage Current (0 V Vin 7.0 V) Ilkg(I) Output Leakage Current (0 V Vout 7.0 V, Output Disable) Unit Notes mA 1, 2 mA mA 1, 2 mA 1, 2 mA A A mA 1 300 A 1, 3 - 10 10 A Ilkg(O) - 10 10 A VOH 2.4 -- V Output High Voltage (IOH = - 5 mA) Output Low Voltage (IOL = 4.2 mA) VOL -- 0.4 V NOTES: 1. Current is a function of cycle rate and output loading. Maximum currents are at the specified cycle time (min) with the output open. 2. Column address can be changed once or less while RAS = VIL and CAS = VIH. 3. tRAS (max) = 1 s is only applied to refresh of battery back-up. tRAS (max) = 10 s is applied to functional operating. CAPACITANCE (f = 1.0 MHz, TA = 25C, VCC = 5 V, periodically sampled, not 100% tested) Parameter Input Capacitance A0 - A8 Symbol Max Unit Cin 5 pF RAS, CAS, W, G Input/Output Capacitance (CAS = VIH to Disable Output) DQ0 - DQ15 7 Cout 7 pF NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I t/V. MCM54260B*MCM5L4260B*MCM5S4260B 4 MOTOROLA DRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) READ, WRITE, AND READ-MODIFY-WRITE CYCLES (See Notes 1, 2, 3, 4, and 5) MCM54260B-70 MCM5L4260B-70 MCM5S4260B-70 Symbol Parameter Std MCM54260B-80 MCM5L4260B-80 MCM5S4260B-80 MCM54260B-10 MCM5L4260B-10 MCM5S4260B-10 Alt Min Max Min Max Min Max Unit Notes Random Read or Write Cycle Time tRELREL tRC 130 -- 150 -- 180 -- ns 5 Read-Modify-Write Cycle Time tRELREL tRWC 185 -- 205 -- 245 -- ns 5 Page Mode Cycle Time tCELCEL tPC 45 -- 50 -- 60 -- ns Page Mode Read-Modify-Write Cycle Time tCELCEL tPRWC 100 -- 105 -- 125 -- ns Access Time from RAS tRELQV tRAC -- 70 -- 80 -- 100 ns 6,7,8 Access Time from CAS tCELQV tCAC -- 20 -- 20 -- 25 ns 6, 7 Access Time from Column Address tAVQV tAA -- 35 -- 40 -- 50 ns 6, 8 Access Time from CAS Precharge tCEHQV tCPA -- 40 -- 45 -- 55 ns 6 CAS to Output in Low-Z tCELQX tCLZ 0 -- 0 -- 0 -- ns 6 Output Buffer Turn-Off Delay tCEHQZ tOFF 0 15 0 15 0 20 ns 9 Transition Time (Rise and Fall) tT tT 3 50 3 50 3 50 ns RAS Precharge Time tREHREL tRP 50 -- 60 -- 70 -- ns RAS Pulse Width tRELREH tRAS 70 10,000 80 10,000 100 10,000 ns RAS Pulse Width (Page Mode) tRELREH tRASP 70 100,000 80 100,000 100 100,000 ns RAS Hold Time tCELREH tRSH 20 -- 20 -- 25 -- ns CAS Hold Time tRELCEH tCSH 70 -- 80 -- 100 -- ns CAS Pulse Width tCELCEH tCAS 20 10,000 20 10,000 25 10,000 ns RAS to CAS Delay Time tRELCEL tRCD 20 50 20 60 25 75 ns 7 tRELAV tRAD 15 35 15 40 20 50 ns 8 CAS to RAS Precharge Time tCEHREL tCRP 5 -- 5 -- 10 -- ns CAS Precharge Time (Page Mode Only) tCEHCEL tCP 10 -- 10 -- 10 -- ns RAS Hold Time From CAS Precharge (Page Mode Only) tCEHREH tRHCP 40 -- 45 -- 55 -- ns RAS to Column Address Delay Time Row Address Setup Time tAVREL tASR 0 -- 0 -- 0 -- ns Row Address Hold Time tRELAX tRAH 10 -- 10 -- 15 -- ns Column Address Setup Time tAVCEL tASC 0 -- 0 -- 0 -- ns Column Address Hold Time tCELAX tCAH 15 -- 15 -- 20 -- ns Column Address to RAS Lead Time tAVREH tRAL 35 -- 40 -- 50 -- ns NOTES: (continued) 1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 2. An initial pause of 100 s is required after power-up followed by 8 RAS only refresh cycles or 8 CAS before RAS refresh cycles, before proper device operation is guaranteed. 3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. AC measurements tT = 5.0 ns. 5. The specifications for tRC (min) and tRMW (min) are used only to indicate cycle time at which proper operation over the full temperature range (0 TA 70C) is ensured. 6. Measured with a current load equivalent to 2 TTL (- 200 A, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V and VOL = 0.8 V. 7. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 8. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 9. tOFF (max) and tGZ (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 5 READ, WRITE, AND READ-MODIFY-WRITE CYCLES (Continued) MCM54260B-70 MCM5L4260B-70 MCM5S4260B-70 Symbol Parameter MCM54260B-80 MCM5L4260B-80 MCM5S4260B-80 MCM54260B-10 MCM5L4260B-10 MCM5S4260B-10 Std Alt Min Max Min Max Min Max Unit Read Command Setup Time tWHCEL tRCS 0 -- 0 -- 0 -- ns Read Command Hold Time tCEHWX tRCH 0 -- 0 -- 0 -- ns 10 Read Command Hold Time Referenced to RAS tREHWX tRRH 0 -- 0 -- 0 -- ns 10 Write Command Hold Time tCELWH tWCH 15 -- 15 -- 20 -- ns Write Command Pulse Width tWLWH tWP 15 -- 15 -- 20 -- ns Write Command to RAS Lead Time tWLREH tRWL 20 -- 20 -- 25 -- ns Write Command to CAS Lead Time tWLCEH tCWL 20 -- 20 -- 25 -- ns Data in Setup Time tDVCEL tDS 0 -- 0 -- 0 -- ns 11 Data in Hold Time tCELDX tDH 15 -- 15 -- 20 -- ns 11 tRVRV tRFSH -- -- -- 8 64 64 -- -- -- 8 64 64 -- -- -- 8 64 64 ms Write Command Setup Time tWLCEL tWCS 0 -- 0 -- 0 -- ns 12 CAS to Write Delay tCELWL tCWD 50 -- 50 -- 60 -- ns 12 RAS to Write Delay tRELWL tRWD 100 -- 110 -- 135 -- ns 12 Column Address to Write Delay tAVWL tAWD 65 -- 70 -- 85 -- ns 12 CAS Precharge to Write Delay tCEHWL tCPWD 70 -- 75 -- 90 -- ns 12 CAS Setup Time for CAS Before RAS Cycle tRELCEL tCSR 5 -- 5 -- 5 -- ns CAS Hold Time for CAS Before RAS Cycle tRELCEH tCHR 15 -- 15 -- 20 -- ns RAS Precharge to CAS Active Time tREHCEL tRPC 5 -- 5 -- 5 -- ns CAS Precharge Time (CAS Before RAS Counter Test) tCEHCEL tCPT 30 -- 30 -- 40 -- ns tGLREH tROH 10 -- 10 -- 20 -- ns G Access Time tGLQV tGA -- 20 -- 20 -- 25 ns G to Data Delay tGLHDX tGD 20 -- 20 -- 25 -- ns Output Buffer Turn-Off Delay Time from G tGHQZ tGZ 0 20 0 20 0 25 ns G Command Hold Time tWLGL tGH 20 -- 20 -- 25 -- ns Refresh Period MCM54260B MCM5L4260B MCM5S4260B RAS Hold Time Referenced to G Notes 6 9 Output Disable Setup Time tGLCEL tGDS 0 -- 0 -- 0 -- ns NOTES: 10. Either tRRH or tRCH must be satisfied for a read cycle. 11. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in late write or read-write cycles. 12. tWCS, tRWD, tCWD, tCPWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (min), tCPWD tCPWD (min), tRWD tRWD (min), and tAWD tAWD (min), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. MCM54260B*MCM5L4260B*MCM5S4260B 6 MOTOROLA DRAM READ CYCLE tRC tRP tRAS VIH RAS VIL tCSH tCRP UCAS, LCAS tRCD tCAS VIH VIL tRAD tASR VIH A0 - A8 VIL tCRP tRSH tRAL tRAH tASC ROW tCAH COLUMN tRCH tRRH tRCS VIH WRITE VIL tROH tAA tGA VIH G VIL tOFF tCAC tRAC DQ0 - DQ15 VOH VOL OPEN tGZ DATA OUT tCLZ MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 7 UPPER BYTE READ CYCLE tRC tRP tRAS VIH RAS VIL tCSH tCRP UCAS tRCD tRSH tCAS VIH tCRP VIL tCRP LCAS tRPC VIH VIL tRAD tRAH tRAL tASR VIH A0 - A8 VIL tASC ROW tCAH COLUMN tRCH tRRH tRCS VIH WRITE VIL tROH tAA tGA VIH G DQ0 - DQ7 VIL VOH OPEN VOL tOFF tCAC tRAC DQ8 - DQ15 VOH OPEN tGZ DATA OUT VOL tCLZ MCM54260B*MCM5L4260B*MCM5S4260B 8 MOTOROLA DRAM LOWER BYTE READ CYCLE tRC tRAS tRP VIH RAS VIL tRPC tCRP UCAS VIH VIL tCSH tCRP LCAS tRSH tCAS tRCD VIH tRAD VIL tRAH tRAL tASR VIH A0 - A8 tCRP tASC ROW tCAH COLUMN VIL tRCH tRRH tRCS VIH WRITE VIL tROH tAA tGA VIH G VIL tOFF tCAC tRAC DQ0 - DQ7 VOH tGZ OPEN DATA OUT VOL tCLZ DQ8 - DQ15 VOH OPEN VOL MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 9 WRITE CYCLE (EARLY WRITE) tRC tRAS tRP VIH RAS VIL tCSH tCRP UCAS, LCAS tRCD tRSH tCAS VIH VIL tASR tRAL tRAH tASC VIH A0 - A8 ROW tCRP tCAH COLUMN VIL tRAD tCWL tWCS tWCH tWP VIH WRITE VIL tRWL VIH G VIL tDS DQ0 - DQ15 VOH VOL MCM54260B*MCM5L4260B*MCM5S4260B 10 tDH DATA IN MOTOROLA DRAM UPPER BYTE WRITE CYCLE (EARLY WRITE) tRC tRAS tRP VIH RAS VIL tCSH tCRP LCAS tRCD tRSH tCAS VIH tCRP VIL tRPC tCRP UCAS VIH VIL tASC tASR VIH A0 - A8 tRAL tCAH tRAH ROW COLUMN VIL tRAD tCWL tWCS tWCH tWP VIH WRITE VIL tRWL VIH G VIL tDH tDS DQ8 - DQ15 VIH DATA IN VIL MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 11 LOWER BYTE WRITE CYCLE (EARLY WRITE) tRC tRAS tRP VIH RAS VIL tCRP UCAS tRPC VIH VIL tCSH tCRP LCAS tRCD tRSH tCAS VIH tCRP VIL tRAH tASR VIH A0 - A8 tRAL tCAH tASC ROW COLUMN VIL tRAD tCWL tWCS tWCH tWP VIH WRITE VIL tRWL VIH G VIL tDS DQ0 - DQ7 VIH tDH DATA IN VIL MCM54260B*MCM5L4260B*MCM5S4260B 12 MOTOROLA DRAM WRITE CYCLE (G CONTROLLED WRITE) tRC tRAS tRP VIH RAS VIL tCSH tCRP tRCD V UCAS, LCAS IH VIL tRAD tRAH tASR VIH A0 - A8 VIL tRSH tCAS tCRP tRAL tCAH tASC ROW COLUMN tCWL tRWL tWP VIH WRITE VIL tGDS tGH VIH G VIL tDS DQ0 - DQ15 VOH tDH DATA IN VOL MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 13 UPPER BYTE WRITE CYCLE (G CONTROLLED WRITE) tRC tRAS tRP VIH RAS VIL tCSH tRCD tCRP UCAS tRSH tCAS VIH VIL tCRP LCAS tRPC VIH VIL tRAD tRAH tASR VIH A0 - A8 tCRP VIL tRAL tCAH tASC ROW COLUMN tCWL tRWL tWP VIH WRITE VIL tGDS tGH VIH G VIL tDH tDS DQ8 - DQ15 VOH DATA IN VOL MCM54260B*MCM5L4260B*MCM5S4260B 14 MOTOROLA DRAM LOWER BYTE WRITE CYCLE (G CONTROLLED WRITE) tRC tRAS tRP VIH RAS VIL tCRP UCAS tRPC VIH VIL tCSH tRCD tCRP LCAS VIH VIL tRAD tRAH tASR VIH A0 - A8 tRSH tCRP tCAS tRAL tASC tCAH ROW COLUMN VIL tCWL tRWL tWP VIH WRITE VIL tGDS tGH VIH G VIL tDH tDS DQ0 - DQ7 VIH VIL MOTOROLA DRAM DATA IN MCM54260B*MCM5L4260B*MCM5S4260B 15 READ-MODIFY-WRITE CYCLE tRMW tRAS tRP VIH RAS VIL tCRP tCSH tRSH tCAS tRCD UCAS, LCAS VIH VIL tCRP tRAD tASC tASR tCAH tRAH VIH A0 - A8 VIL ROW COLUMN tAWD tCWD tCWL tRWL tWP tRCS VIH WRITE VIL tAA tRWD tGA VIH G VIL tGD tDH tRAC VIH tDS OPEN DATA IN VIL tCAC DQ0 - DQ15 tGZ tCLZ VOH OPEN VOL MCM54260B*MCM5L4260B*MCM5S4260B 16 DATA OUT MOTOROLA DRAM UPPER BYTE READ-MODIFY-WRITE CYCLE tRMW tRAS tRP VIH RAS VIL tCRP tCSH tRSH tCAS tRCD UCAS VIH tCRP VIL tCRP LCAS tRPC VIH VIL tRAD tASC tASR tCAH tRAH VIH A0 - A8 VIL ROW COLUMN tAWD tCWD tCWL tRWL tWP tRCS VIH WRITE VIL tAA tRWD tGA VIH G VIL tGD tDH tRAC VIH tDS OPEN DATA IN VIL tCAC DQ8 - DQ15 tGZ tCLZ VOH VOL MOTOROLA DRAM OPEN DATA OUT MCM54260B*MCM5L4260B*MCM5S4260B 17 LOWER BYTE READ-MODIFY-WRITE CYCLE tRMW tRAS tRP VIH RAS VIL tCRP LCAS tRCP VIH VIL tCRP tCSH tRSH tCAS tRCD UCAS VIH VIL tCRP tRAD tASC tASR tCAH tRAH VIH A0 - A8 VIL ROW COLUMN tAWD tCWD tCWL tRWL tWP tRCS VIH WRITE VIL tAA tRWD tGA VIH G VIL tGD tDH tRAC VIH tDS OPEN DATA IN VIL tCAC DQ0 - DQ7 tGZ tCLZ VOH OPEN VOL MCM54260B*MCM5L4260B*MCM5S4260B 18 DATA OUT MOTOROLA DRAM FAST PAGE MODE READ CYCLE tRP tRASP VIH RAS VIL tPC tPC tRSH tRHCP tCRP tCAS tRCD tCRP UCAS, LCAS VIH tCP tCAS tRAH VIL tCAS tRAD tCP tCSH tASR VIH A0 - A8 VIL tRAL tASC tASC tASC tCAH tCAH ROW COLUMN 1 COLUMN 2 tCAH COLUMN N tRCS tRCH tRCS tRCS tRCH tRCH VIH WRITE VIL tROH tAA tAA tAA tCPA tGA tRRH tCPA tGA tGA VIH G VIL tRAC tCAC tOFF tCAC tGZ tCLZ DQ0 - DQ15 tCAC tOFF tOFF tGZ tCLZ tCLZ tGZ VOH VOL MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 19 FAST PAGE MODE BYTE READ CYCLE tRP tRASP VIH RAS VIL tPC tRSH tRCD tRHCP tCRP UCAS tCAS VIH VIL tRAD tPC tASR LCAS VIH tCSH tCAH tASR A0 - A8 VIL tCP tCAS tRCP tRAH VIL VIH tCRP tCP tCAS tRAL tASC tCAH ROW tCAH tASC tASC COLUMN 1 COLUMN 2 COLUMN N tRCS tRCH tRCS tRCS tRCH tRCH VIH WRITE VIL tAA tAA tAA tCPA tGA tRRH tCPA tGA tGA VIH G VIL tOFF tCAC tCLZ V DQ0 - DQ7 OH VOL Dout 2 tRAC tCAC tOFF tCLZ DQ8 - DQ15 tGZ VOH VOL MCM54260B*MCM5L4260B*MCM5S4260B 20 tGZ Dout 1 tOFF tGZ tCAC tCLZ Dout N MOTOROLA DRAM FAST PAGE MODE WRITE CYCLE (EARLY WRITE) tRP tRASP VIH RAS VIL tPC tPC tRCD tCP tCAS tCRP V UCAS, LCAS IH VIL tRSH tCRP tCP tCAS tCAS tASC tRAL tASC tCAH tRAH tCSH tASC tASR VIH A0 - A8 VIL tCAH tCAH ROW COLUMN 1 COLUMN 2 tCWL tCWL tRAD tWCS tWCS WRITE tCWL tRWL tWCS tWCH tWCH tWP VIH COLUMN 3 tWCH tWP tWP VIL VIH G VIL tDH tDH tDS DQ0 - DQ15 VOH VOL MOTOROLA DRAM tDH tDS Din 1 tDS Din 2 Din N MCM54260B*MCM5L4260B*MCM5S4260B 21 FAST PAGE MODE BYTE WRITE CYCLE (EARLY WRITE) tRP tRASP VIH RAS VIL tPC tRCD tCRP UCAS tPC tCP tCP tRSH tCAS tCAS tCRP VIH VIL tCAS tCRP LCAS VIH tRPC tRAH tCSH VIL tASR VIH A0 - A8 tCAH tCAH ROW COLUMN 1 COLUMN 2 COLUMN 3 VIL tRAD tCWL tCWL tWCS tWCS tWP VIH tCWL tRWL tWCS tWCH tWCH WRITE tRAL tASC tCAH tASC tASC tWP tWCH tWP VIL VIH G VIL tDS DQ0 - DQ7 VIH Din 2 VIL tDS DQ8 - DQ15 VIH VIL tDH tDH Din 1 MCM54260B*MCM5L4260B*MCM5S4260B 22 tDS tDH Din N MOTOROLA DRAM FAST PAGE MODE READ-MODIFY-WRITE CYCLE tRP tRASP RAS tCSH VIH VIL tRCD tPRMW tCAS UCAS, VIH LCAS VIL tRAD tRAH tASR tPRMW tCAS tRSH tCAS tCAH tCP tCAH tCAH VIH tRAL tASC tASC tASC A0 - A8 tCRP tCP COL. 1 COL. 2 COL. N VIL tCWD tCPWD tRWD tCWD ROW tCPWD tCWD tRWL tCWL tRCS WRITE VIH VIL tAWD tAWD tAA tCWL tAA tGA tWP tAWD tCWL tGA tWP tAA tGA tWP VIH G VIL tGD VIH tCPA tRAC tCAC tDS tGD tCAC Din2 VIL tCLZ DQ0 - DQ15 tDS tCAC tDS tCPA tGD tGZ Din1 tDH tCLZ DinN tDH tDH tGZ tCLZ tGZ Din2 VOH VOL Dout1 MOTOROLA DRAM Dout2 DoutN MCM54260B*MCM5L4260B*MCM5S4260B 23 FAST PAGE MODE BYTE READ-MODIFY-WRITE CYCLE tRP tRASP RAS tCSH VIH VIL tCP tRCD UCAS tPRMW tCAS VIH tCRP tRSH tCAS tCAH tPRMW VIL tRAD LCAS VIL tRAH tASR tRAL tCAH tCAH tASC tASC A0 - A8 tCP tCAS VIH tASC VIH COL. 1 VIL COL. 2 tRWD ROW COL. N tCPWD tCWD tCWD tCPWD tCWD tRWL tRCS WRITE tCWL VIH VIL tAWD tAA tAWD tCWL tAA tGA tAWD tCWL tGA tWP tWP tAA tGA tWP VIH G VIL tRAC tGD tCPA tCAC tCAC tCPA tCAC tDS VIH Din2 VIL tCLZ DQ0 - DQ7 tDH tGZ VOH VOL Dout2 tGD tGD tDS tDS VIH DinN VIL DQ8 - DQ15 Din1 tDH tCLZ tDH tCLZ tGZ tGZ Dout1 DoutN VOH VOL MCM54260B*MCM5L4260B*MCM5S4260B 24 MOTOROLA DRAM RAS-ONLY REFRESH CYCLE tRC tRP RAS tRAS VIH VIL tRPC tCRP UCAS, LCAS VIH VIL tRAH tASR A0 - A8 VIH ROW VIL NOTE: WRITE, G = "H" or "L" CAS BEFORE RAS REFRESH CYCLE tRC tRP RAS tRP tRAS VIH VIL tCHR tRPC tCP UCAS, LCAS tCSR VIH VIL DQ0 - DQ15 VOH OPEN VOL NOTE: WRITE, G, A0 - A8= "H" or "L" CAS before RAS refresh is performed when either UCAS or LCAS meets this timing. MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 25 HIDDEN REFRESH CYCLE (READ) tRC tRC tRP tRAS RAS tRP tRAS VIH VIL tCRP UCAS, LCAS tRSH tRCD tCRP VIH tRAD VIL tCAH tASR A0 - A8 tCHR VIH tASC ROW VIL COLUMN tRAH tRCS WRITE tRRH VIH tAA VIL G tGA VIH VIL tOFF tCAC tCLZ DQ0 - DQ15 VOH VOL tGZ DATA - OUT tRAC MCM54260B*MCM5L4260B*MCM5S4260B 26 MOTOROLA DRAM HIDDEN REFRESH CYCLE (WRITE) tRC RAS tRC tRP tRAS tRP tRAS VIH VIL tCRP UCAS, LCAS tRSH tRCD tRAD tCAH tRAH tASR VIH VIL tASC ROW COLUMN tWCS WRITE tCRP VIH VIL A0 - A8 tCHR tWCH tWP VIH VIL G VIH VIL tDH tDS DQ0 - DQ15 VOH DATA - IN VOL MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 27 CAS BEFORE RAS REFRESH COUNTER TEST READ CYCLE tRP RAS tRAS VIH VIL tCHR UCAS, LCAS tRSH tCAS tCPT tCSR VIH tCRP VIL tRAL tASC A0 - A8 VIH tCAL COLUMN VIL tRRH tRCS WRITE tRCH VIH VIL G tROH tGA VIH VIL tOFF tCAC tAA VOH tGZ DATA - OUT DQ0 - DQ15 VOL tCLZ MCM54260B*MCM5L4260B*MCM5S4260B 28 MOTOROLA DRAM CAS BEFORE RAS REFRESH COUNTER TEST WRITE CYCLE tRP RAS tRAS VIH VIL tCHR UCAS, LCAS tRSH tCAS tCPT tCSR VIH tCRP VIL tRAL tCAL tASC A0 - A8 VIH COLUMN VIL tRWL tCWL tWCS WRITE tWCH VIH VIL G VIH VIL tDH tDS DQ0 - DQ15 VIH DATA - IN VIL MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 29 CAS BEFORE RAS REFRESH COUNTER TEST READ-MODIFY-WRITE CYCLE tRP RAS tRAS VIH VIL tCHR UCAS, LCAS tRSH tCAS tCPT tCSR VIH tCRP VIL tRAL tCAL tASC A0 - A8 VIH COLUMN VIL tCWL tAWD tCWD WRITE tRCS VIH VIL G tRWL tWP tGA tAA VIH VIL tDH tDS VIH Din VIL tGD tCAC DQ0 - DQ15 tGZ tCLZ VOH Dout VOL ORDERING INFORMATION (Order by Full Part Number) 54260B 5L4260B MCM 5S4260B X Motorola Memory Prefix XX XX Shipping Method (Blank = Rails or Tray, R = Tape and Reel) Part Number Speed (70 = 70 ns, 80 = 80 ns, 10 = 100 ns) Package (J = 400 mil SOJ, T = 400 mil TSOP) Full Part Numbers -- MCM54260BJ70 MCM54260BJ80 MCM54260BJ10 MCM5L4260BJ70 MCM5L4260BJ80 MCM5L4260BJ100 MCM5S4260BJ70 MCM5S4260BJ80 MCM5S4260BJ10 MCM54260BT70 MCM54260BT80 MCM54260BT10 MCM5L4260BT70 MCM5L4260BT80 MCM5L4260BT10 MCM5S4260BT70 MCM5S4260BT80 MCM5S4260BT10 MCM54260BJ70R MCM54260BJ80R MCM54260BJ10R MCM5L4260BJ70R MCM5L4260BJ80R MCM5L4260BJ10R MCM5S4260BJ70R MCM5S4260BJ80R MCM5S4260BJ10R MCM54260BT70R MCM54260BT80R MCM54260BT10R MCM5L4260BT70R MCM5L4260BT80R MCM5L4260BT10R MCM5S4260BT70R MCM5S4260BT80R MCM5S4260BT10R MCM54260B*MCM5L4260B*MCM5S4260B 30 MOTOROLA DRAM PACKAGE DIMENSIONS J PACKAGE 400 MIL SOJ CASE 923A-01 A -X40 21 B -Y- 1 20 0.007 (0.18) DETAIL H M T Y S X S C P K E 2X 38 X L 0.004 (0.10) G -T- T R SEATING PLANE 0.015 (0.38) T Y 40 X R 40 X F 0.007 (0.18) L T Y 40 X N 40 X D NOTE 3 0.007 (0.18) M T Y DETAIL H S X S S X S J 2 ZONES 20 X NOTE 3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006 (0.15) PER SIDE. 5. DIMENSIONS A AND B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE. DIM A B C D E F G J K L N P R INCHES MIN MAX 1.020 1.030 0.395 0.405 0.128 0.148 0.012 0.021 0.082 --- 0.024 0.032 0.050 BSC 0.030 0.040 0.031 --- 0.025 BSC 0.035 0.045 0.430 0.440 0.366 BSC MILLIMETERS MIN MAX 25.91 26.16 10.03 10.29 3.25 3.76 0.33 0.53 2.08 --- 0.61 0.81 1.27 BSC 0.77 1.01 0.80 --- 0.635 BSC 0.89 1.14 10.92 11.18 9.30 BSC Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA DRAM MCM54260B*MCM5L4260B*MCM5S4260B 31 T PACKAGE 400 MIL TSOP CASE 924-01 44 35 32 DETAIL A 23 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.006 (0.15) PER SIDE. 4. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS SHALL NOT ALLOW THE D DIMENSION TO EXCEED 0.023. B -YB B 1 10 13 22 E A -Z- DIM A B C D E F G J K L N R S T V W C 20 x S 0.008 (0.20) M T Y S 0.004 (0.10) 4xR -T36 x G RAD RAD T N L K W DETAIL A ROTATED 90 CLOCKWISE EEEEE CCC EEEEE CCC EEEEE CCC EEEEE CCC F BASE METAL V SEATING PLANE INCHES MILLIMETERS MIN MAX MIN MAX 0.721 0.729 18.313 18.517 0.396 0.404 10.058 10.262 --- 0.050 --- 1.270 0.012 0.018 0.305 0.457 0.038 0.042 0.965 1.067 0.012 0.016 0.305 0.406 0.315 BSC 0.800 BSC 0.005 0.008 0.127 0.203 0.016 0.023 0.406 0.584 0.002 0.006 0.051 0.152 0.004 0.006 0.101 0.152 0.0472 BSC 1.200 BSC 0.456 0.470 11.582 11.938 0.004 REF 0.100 REF 0.004 REF 0.100 REF 0_ 5_ 0_ 5_ J D 0.008 (0.20) M T Z S SECTION B-B How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MCM54260B*MCM5L4260B*MCM5S4260B 32 *MCM54260B/D* MCM54260B/D MOTOROLA DRAM