MCM54260B•MCM5L4260B•MCM5S4260B
1
MOTOROLA DRAM
Advance Information
256K x 16 CMOS Dynamic RAM
Fast Page Mode – 2 CAS, 1 Write Enable
The MCM54260B is a 0.6µ CMOS high–speed dynamic random access memory.
It is organized as 262,144 sixteen–bit words and fabricated with CMOS silicon–gate
process technology. Advanced circuit design and fine line processing provide high
performance, improved reliability, and low cost.
The MCM54260B requires only 9 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 400 mil SOJ plastic package
and a 400 mil thin–small–outline package (TSOP).
•Three–State Data Output
•Fast Page Mode
•TTL–Compatible Inputs and Outputs
•RAS–Only Refresh
•CAS Before RAS Refresh
•Hidden Refresh
•512 Cycle Refresh:
MCM54260B = 8 ms
MCM5L4260B = 64 ms
MCM5S4260B = 64 ms
•Fast Access Time (tRAC):
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70 = 70 ns (Max)
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80 = 80 ns (Max)
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10 = 100 ns (Max)
•Low Active Power Dissipation:
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70 = 550 mW (Max)
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80 = 468 mW (Max)
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10 = 413 mW (Max)
•Low Standby Power Dissipation:
MCM54260B, MCM5L4260B, and MCM5S4260B= 5.5 mW (Max, TTL Levels)
•Battery Backup Power Dissipation:
MCM5L4260B and MCM5S4260B = 1.7 mW (Max, Battery Backup Mode,
tRC = 125 µs)
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM54260B/D
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA MCM54260B
MCM5L4260B
MCM5S4260B
J PACKAGE
400 MIL SOJ
CASE 923A–01
T PACKAGE
400 MIL TSOP
CASE 924–01
PIN NAMES
A0 – A8 Address Inputs. . . . . . . . . . . . . .
DQ0 – DQ15 Data Input/Output. . . . . . .
W Read/Write Enable. . . . . . . . . . . . . . . .
RAS Row Address Strobe. . . . . . . . . . . .
LCAS, UCAS Column Address Strobe.
VCC Power Supply (+ 5 V). . . . . . . . . . .
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . .
NC No Connect. . . . . . . . . . . . . . . . . . . . .
GOutput Enable. . . . . . . . . . . . . . . . . . .
REV 3
10/95
Motorola, Inc. 1995
MCM54260B•MCM5L4260B•MCM5S4260B
2MOTOROLA DRAM
PIN ASSIGNMENTS
4
3
2
1
20
19
5
9
8
7
6
13
12
11
10
14
15
16
17
18 23
22
21
24
25
26
27
28
31
30
29
32
33
34
35
36
37
38
39
40VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ15
VSS
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
DQ7
DQ6
NC
NC
W
RAS
NC
A0
A1
A2
A3
VCC VSS
A4
A5
A6
A7
A8
G
UCAS
LCAS
4
3
2
1
22
21
5
9
8
7
6
15
14
13
10
16
17
18
19
20 25
24
23
26
27
28
29
30
35
32
31
36
37
38
39
40
41
42
43
44VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ15
VSS
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
DQ7
DQ6
NC
NC
W
RAS
NC
A0
A1
A2
A3
VCC VSS
A4
A5
A6
A7
A8
G
UCAS
LCAS
400 MIL SOJ 400 MIL TSOP
MCM54260B•MCM5L4260B•MCM5S4260B
3
MOTOROLA DRAM
BLOCK DIAGRAM
WRITE
UCAS
LCAS
RAS
A0
VOLTAGE DOWN
CONVERTER DATA IN
BUFFERS DATA OUT
BUFFERS
COLUMN
DECODER
SENSE AMP
I/O GATE
MEMORY
ARRAY
512 x 512 x 16
SUBSTRATE BIAS
GENERATOR
NO. 1 CLOCK
GENERATOR
ROW
ADDRESS
BUFFERS (9)
REFRESH
COUNTER (9)
REFRESH
CONTROLLER
COLUMN
ADDRESS
BUFFERS (9)
NO. 2 CLOCK
GENERATOR
VCC VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13 DQ15
DQ14
VCC
VCC
8888
8 8 8 8
16
99
9
9
9
A1
A2
A3
A4
A5
A6
A7
A8
DATA IN
BUFFERS
DATA OUT
BUFFERS
VSS
ROW
DECODER
512 x 16
512
G
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Power Supply Voltage VCC – 1 to + 7 V
Voltage Relative to VSS for Any Pin
Except VCC Vin, Vout – 1 to + 7 V
Data Out Current Iout 50 mA
Power Dissipation PD700 mW
Operating Temperature Range TA0 to + 70 °C
Storage Temperature Range Tstg – 55 to + 150 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however , it
is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to this
high–impedance circuit.
MCM54260B•MCM5L4260B•MCM5S4260B
4MOTOROLA DRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS)
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range)
VCC 4.5 5.0 5.5
V
VSS 0 0 0
Logic High Voltage, All Inputs VIH 2.4 — 6.0 V
Logic Low Voltage, All Inputs Except DQ0 – DQ15 VIL – 0.5* — 0.8 V
Logic Low Voltage, DQ0 – DQ15 VIL – 0.5* — 0.8 V
*– 2.0 V at pulse width ≤ 20 ns
DC CHARACTERISTICS
Characteristic Symbol Min Max Unit Notes
VCC Power Supply Current
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70, tRC = 130 ns
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80, tRC = 150 ns
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10, tRC = 180 ns
ICC1 —
—
—
100
85
75
mA 1, 2
VCC Power Supply Current (Standby) (RAS = CAS = VIH) ICC2 — 2 mA
VCC Power Supply Current During RAS Only Refresh Cycles (CAS = VIH)
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70, tRC = 130 ns
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80, tRC = 150 ns
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10, tRC = 180 ns
ICC3 —
—
—
100
85
75
mA 1, 2
VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL)
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70, tPC = 45 ns
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80, tPC = 50 ns
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10, tPC = 60 ns
ICC4 —
—
—
70
60
55
mA 1, 2
VCC Power Supply Current (Standby) (RAS = CAS = VCC – 0.2 V) MCM54260B
MCM5L4260B
MCM5S4260B
ICC5 —
—
—
1.0
200
200
mA
µA
µA
VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70, tRC = 130 ns
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80, tRC = 150 ns
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10, tRC = 180 ns
ICC6 —
—
—
100
85
75
mA 1
VCC Power Supply Current, Battery Backup Mode—MCM5L4260B and MCM5S4260B
(tRC = 125 µs; tRAS = 1 µs; CAS = CAS Before RAS Cycle or 0.2 V;
A0 – A8, W, D = VCC – 0.2 V or 0.2 V)
ICC7 — 300 µA 1, 3
Input Leakage Current (0 V ≤ Vin ≤ 7.0 V) Ilkg(I) – 10 10 µA
Output Leakage Current (0 V ≤ Vout ≤ 7.0 V, Output Disable) Ilkg(O) – 10 10 µA
Output High Voltage (IOH = – 5 mA) VOH 2.4 — V
Output Low Voltage (IOL = 4.2 mA) VOL — 0.4 V
NOTES:
1. Current is a function of cycle rate and output loading. Maximum currents are at the specified cycle time (min) with the output open.
2. Column address can be changed once or less while RAS = VIL and CAS = VIH.
3. tRAS (max) = 1 µs is only applied to refresh of battery back–up. tRAS (max) = 10 µs is applied to functional operating.
CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, periodically sampled, not 100% tested)
Parameter Symbol Max Unit
Input Capacitance A0 – A8 Cin 5 pF
RAS, CAS, W, G 7
Input/Output Capacitance (CAS = VIH to Disable Output) DQ0 – DQ15 Cout 7 pF
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
MCM54260B•MCM5L4260B•MCM5S4260B
5
MOTOROLA DRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ–MODIFY–WRITE CYCLES (See Notes 1, 2, 3, 4, and 5)
Symbol
MCM54260B–70
MCM5L4260B–70
MCM5S4260B–70
MCM54260B–80
MCM5L4260B–80
MCM5S4260B–80
MCM54260B–10
MCM5L4260B–10
MCM5S4260B–10
Parameter Std Alt Min Max Min Max Min Max Unit Notes
Random Read or Write Cycle Time tRELREL tRC 130 — 150 — 180 — ns 5
Read–Modify–Write Cycle Time tRELREL tRWC 185 — 205 — 245 — ns 5
Page Mode Cycle Time tCELCEL tPC 45 — 50 — 60 — ns
Page Mode Read–Modify–Write
Cycle Time tCELCEL tPRWC 100 — 105 — 125 — ns
Access Time from RAS tRELQV tRAC — 70 — 80 — 100 ns 6,7,8
Access Time from CAS tCELQV tCAC — 20 — 20 — 25 ns 6, 7
Access Time from Column Address tAVQV tAA — 35 — 40 — 50 ns 6, 8
Access Time from CAS Precharge tCEHQV tCPA — 40 — 45 — 55 ns 6
CAS to Output in Low–Z tCELQX tCLZ 0 — 0 — 0 — ns 6
Output Buffer Turn–Off Delay tCEHQZ tOFF 0 15 0 15 0 20 ns 9
Transition Time (Rise and Fall) tTtT3 50 3 50 3 50 ns
RAS Precharge Time tREHREL tRP 50 — 60 — 70 — ns
RAS Pulse Width tRELREH tRAS 70 10,000 80 10,000 100 10,000 ns
RAS Pulse Width (Page Mode) tRELREH tRASP 70 100,000 80 100,000 100 100,000 ns
RAS Hold Time tCELREH tRSH 20 — 20 — 25 — ns
CAS Hold Time tRELCEH tCSH 70 — 80 — 100 — ns
CAS Pulse Width tCELCEH tCAS 20 10,000 20 10,000 25 10,000 ns
RAS to CAS Delay Time tRELCEL tRCD 20 50 20 60 25 75 ns 7
RAS to Column Address Delay Time tRELAV tRAD 15 35 15 40 20 50 ns 8
CAS to RAS Precharge Time tCEHREL tCRP 5 — 5 — 10 — ns
CAS Precharge Time (Page Mode
Only) tCEHCEL tCP 10 — 10 — 10 — ns
RAS Hold Time From CAS
Precharge (Page Mode Only) tCEHREH tRHCP 40 — 45 — 55 — ns
Row Address Setup Time tAVREL tASR 0 — 0 — 0 — ns
Row Address Hold Time tRELAX tRAH 10 — 10 — 15 — ns
Column Address Setup Time tAVCEL tASC 0 — 0 — 0 — ns
Column Address Hold Time tCELAX tCAH 15 — 15 — 20 — ns
Column Address to RAS Lead Time tAVREH tRAL 35 — 40 — 50 — ns
NOTES: (continued)
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. T ransition times are measured between VIH and VIL.
2. An initial pause of 100 µs is required after power–up followed by 8 RAS only refresh cycles or 8 CAS before RAS refresh cycles, before
proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements tT = 5.0 ns.
5. The specifications for tRC (min) and tRMW (min) are used only to indicate cycle time at which proper operation over the full temperature
range (0 ≤ TA ≤ 70°C) is ensured.
6. Measured with a current load equivalent to 2 TTL (– 200 µA, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V and
VOL = 0.8 V.
7. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD
is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
8. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD
is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.
9. tOFF (max) and tGZ (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage
levels.
MCM54260B•MCM5L4260B•MCM5S4260B
6MOTOROLA DRAM
READ, WRITE, AND READ–MODIFY–WRITE CYCLES (Continued)
Symbol
MCM54260B–70
MCM5L4260B–70
MCM5S4260B–70
MCM54260B–80
MCM5L4260B–80
MCM5S4260B–80
MCM54260B–10
MCM5L4260B–10
MCM5S4260B–10
Parameter Std Alt Min Max Min Max Min Max Unit Notes
Read Command Setup Time tWHCEL tRCS 0 — 0 — 0 — ns
Read Command Hold Time tCEHWX tRCH 0 — 0 — 0 — ns 10
Read Command Hold Time
Referenced to RAS tREHWX tRRH 0 — 0 — 0 — ns 10
Write Command Hold Time tCELWH tWCH 15 — 15 — 20 — ns
Write Command Pulse Width tWLWH tWP 15 — 15 — 20 — ns
Write Command to RAS Lead Time tWLREH tRWL 20 — 20 — 25 — ns
Write Command to CAS Lead Time tWLCEH tCWL 20 — 20 — 25 — ns
Data in Setup Time tDVCEL tDS 0 — 0 — 0 — ns 11
Data in Hold Time tCELDX tDH 15 — 15 — 20 — ns 11
Refresh Period MCM54260B
MCM5L4260B
MCM5S4260B
tRVRV tRFSH —
—
—
8
64
64
—
—
—
8
64
64
—
—
—
8
64
64
ms
Write Command Setup Time tWLCEL tWCS 0 — 0 — 0 — ns 12
CAS to Write Delay tCELWL tCWD 50 — 50 — 60 — ns 12
RAS to Write Delay tRELWL tRWD 100 — 110 — 135 — ns 12
Column Address to Write Delay tAVWL tAWD 65 — 70 — 85 — ns 12
CAS Precharge to Write Delay tCEHWL tCPWD 70 — 75 — 90 — ns 12
CAS Setup Time for CAS Before
RAS Cycle tRELCEL tCSR 5 — 5 — 5 — ns
CAS Hold Time for CAS Before RAS
Cycle tRELCEH tCHR 15 — 15 — 20 — ns
RAS Precharge to CAS Active Time tREHCEL tRPC 5 — 5 — 5 — ns
CAS Precharge Time (CAS Before
RAS Counter Test) tCEHCEL tCPT 30 — 30 — 40 — ns
RAS Hold Time Referenced to G tGLREH tROH 10 — 10 — 20 — ns
G Access Time tGLQV tGA — 20 — 20 — 25 ns 6
G to Data Delay tGLHDX tGD 20 — 20 — 25 — ns
Output Buffer Turn–Off Delay Time
from G tGHQZ tGZ 0 20 0 20 0 25 ns 9
G Command Hold Time tWLGL tGH 20 — 20 — 25 — ns
Output Disable Setup Time tGLCEL tGDS 0 — 0 — 0 — ns
NOTES:
10. Either tRRH or tRCH must be satisfied for a read cycle.
11. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in late write or read–write cycles.
12. tWCS, tRWD, tCWD, tCPWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle. If tCWD ≥ tCWD (min), tCPWD ≥ tCPWD (min), tRWD ≥ tRWD (min), and tAWD ≥ tAWD (min), the cycle
is a read–modify–write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
MCM54260B•MCM5L4260B•MCM5S4260B
7
MOTOROLA DRAM
READ CYCLE
RAS VIL
VIH
UCAS, LCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ0 – DQ15
tRC
VOH
tRAS tRP
tCRP
tRSH
tCSH
tRCD
tRAD tRAL
tROH
tAA
tGZ
tRAC
tCRP
OPEN
tASR
tCLZ
tRCS
tRAH
tOFF
tGA
tRRH
tCAH
tASC
tRCH
DATA OUT
VOL
COLUMNROW
tCAS
tCAC
MCM54260B•MCM5L4260B•MCM5S4260B
8MOTOROLA DRAM
UPPER BYTE READ CYCLE
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ8 – DQ15
tRC
VOH
tCRP
tRPC
DATA OUT
VOL
tRAS tRP
tCRP
tCSH tRSH
tCAS
tRCD
tRAD tRAL
tROH
tAA
tCAC tGZ
tRAC
tCRP
tCAH
tRRH
tRCH
tGA
tOFF
tRAH
tASR
tRCS
tCLZ
tASC
OPEN
DQ0 – DQ7 VOH
VOL
LCAS VIL
VIH
COLUMNROW
OPEN
MCM54260B•MCM5L4260B•MCM5S4260B
9
MOTOROLA DRAM
LOWER BYTE READ CYCLE
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ8 – DQ15 VOH
VOL
DQ0 – DQ7 VOH
VOL
LCAS VIL
VIH
tRC
tRAS tRP
tRPC
tCRP
tCRP
tCSH
tRCD tRSH
tCAS tCRP
tRAD
tRAH
tASR tASC tCAH
tRCH
tRRH
tROH
tAA tGA
tCAC
tRAC tGZ
tOFF
tCLZ
DATA OUT
OPEN
COLUMNROW
tRAL
tRCS
OPEN
MCM54260B•MCM5L4260B•MCM5S4260B
10 MOTOROLA DRAM
WRITE CYCLE (EARLY WRITE)
RAS VIL
VIH
UCAS, LCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ0 – DQ15 VOH
VOL
tRC
tRAS tRP
tCRP
tCSH
tRCD tRSH
tCAS
tRAL tCAH
tRAH
tASR
tASC
tCWL
tWCS tWCH
tRWL
tDS tDH
COLUMNROW
DATA IN
tCRP
tWP
tRAD
MCM54260B•MCM5L4260B•MCM5S4260B
11
MOTOROLA DRAM
UPPER BYTE WRITE CYCLE (EARLY WRITE)
DATA IN
tRC
tRAS tRP
tRPC
tCRP
tCRP tCSH
tRCD tRSH
tCAS tCRP
tRALtCAH
tASC
tASR
tRAH
tRAD
tWCS tWCH
tRWL
tDS tDH
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ8 – DQ15 VIH
VIL
LCAS VIL
VIH
COLUMNROW
tCWL
tWP
MCM54260B•MCM5L4260B•MCM5S4260B
12 MOTOROLA DRAM
LOWER BYTE WRITE CYCLE (EARLY WRITE)
DATA IN
tRC
tRAS tRP
tRPC
tCRP
tCRP tCSH
tRCD tRSH
tCAS tCRP
tRALtCAH
tASC
tASR
tRAH
tRAD
tWCS tWCH
tRWL
tDS tDH
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ0 – DQ7 VIH
VIL
LCAS VIL
VIH
COLUMNROW
tCWL
tWP
MCM54260B•MCM5L4260B•MCM5S4260B
13
MOTOROLA DRAM
WRITE CYCLE (G CONTROLLED WRITE)
tRC
RAS VIL
VIH
UCAS, LCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ0 – DQ15 VOH
VOL
tRAS tRP
tCRP
tCRP tCSH
tRCD tRSH
tCAS
tRALtCAH
tASC
tASR
tCWL
tRWL
tWP
tGH
tGDS
tDS tDH
DATA IN
COLUMNROW
tRAD
tRAH
MCM54260B•MCM5L4260B•MCM5S4260B
14 MOTOROLA DRAM
UPPER BYTE WRITE CYCLE (G CONTROLLED WRITE)
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
LCAS VIL
VIH
tRC
tRAS tRP
tCRP
tCRP tCSH
tRCD tRSH
tCAS
tRPC
tCRP
tRAD tRAL
tRAH
tASR tASC tCAH
tCWL
tRWL
tWP
tGDS tGH
tDH
tDS
DATA IN
COLUMNROW
DQ8 – DQ15 VOH
VOL
MCM54260B•MCM5L4260B•MCM5S4260B
15
MOTOROLA DRAM
LOWER BYTE WRITE CYCLE (G CONTROLLED WRITE)
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ0 – DQ7 VIH
VIL
LCAS VIL
VIH
tRC
tRAS tRP
tRPC
tCRP
tCSH
tCRP tRCD tRSH tCRP
tCAS
tRAL
tCAH
tASC
tRAD
tRAH
tASR
tCWLtRWL
tWP
tGDS
tDS
tDH
DATA IN
COLUMNROW
tGH
MCM54260B•MCM5L4260B•MCM5S4260B
16 MOTOROLA DRAM
READ–MODIFY–WRITE CYCLE
tRAC
RAS VIL
VIH
UCAS, LCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
VIH
VIL
tRMW
tRAS tRP
tCRP
tCRP tCSH
tRCD tRSH
tCAS
tRAD
tASR tRAH
tASC tCAH
tAWDtCWD tCWL
tRWL
tWP
tAA
tRWD tGA
tGD tDH
tDS
tCAC
tCLZ
tGZ
DATA OUT
DATA IN
COLUMNROW
OPEN
OPEN
DQ0 – DQ15
VOH
VOL
tRCS
MCM54260B•MCM5L4260B•MCM5S4260B
17
MOTOROLA DRAM
UPPER BYTE READ–MODIFY–WRITE CYCLE
tRAC
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
VIH
VIL
tRMW
tRAS tRP
tCRP
tCRP tCSH
tRCD tRSH
tCAS
tRAD
tCRP
tRAH
tASC tCAH
tAWDtCWD tCWL
tRWL
tWP
tAA
tRWD tGA
tGD tDH
tDS
tCAC
tCLZ
tGZ
DATA OUT
DATA IN
COLUMNROW
OPEN
OPEN
DQ8 – DQ15
VOH
VOL
LCAS VIL
VIH
tASR
tRPC
tRCS
MCM54260B•MCM5L4260B•MCM5S4260B
18 MOTOROLA DRAM
LOWER BYTE READ–MODIFY–WRITE CYCLE
tRAC
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
VIH
VIL
tRMW
tRAS tRP
tCRP
tCRP tCSH
tRCD tRSH
tCAS
tRAD
tCRP
tRAH
tASC tCAH
tAWDtCWD tCWL
tRWL
tWP
tAA
tRWD tGA
tGD tDH
tDS
tCAC
tCLZ
tGZ
DATA OUT
DATA IN
COLUMNROW
OPEN
OPEN
DQ0 – DQ7
VOH
VOL
LCAS VIL
VIH
tASR
tRCP
tRCS
MCM54260B•MCM5L4260B•MCM5S4260B
19
MOTOROLA DRAM
FAST PAGE MODE READ CYCLE
RAS VIL
VIH
UCAS, LCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ0 – DQ15 VOH
VOL
tRASP tRP
tCRP
tRSH
tRHCP
tCAS
tPC
tPC
tCAS
tCAS tCP
tRCD
tCRP
tRAD
tRAH
tASR tASC tASC tASC
tCP tRAL
tCAH
tCAH
tCAH
ROW COLUMN 2COLUMN 1 COLUMN N
tRCS
tRCS tRCS
tRCH tRCH tRCH
tAA tAA tAA tROH tRRH
tCPA
tCPA tGA
tGA
tGA
tRAC tOFF tOFF tOFF
tGZ tGZ tGZ
tCLZ
tCLZ
tCLZ
tCSH
tCAC
tCAC
tCAC
MCM54260B•MCM5L4260B•MCM5S4260B
20 MOTOROLA DRAM
FAST PAGE MODE BYTE READ CYCLE
RAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
VOH
VOL
DQ0 – DQ7
VOH
VOL
UCAS VIL
VIH
DQ8 – DQ15
LCAS VIL
VIH
tRASP tRP
tRCS
tRCS tRCS
tRCH tRCH tRCH
tAA tAA tAA tRRH
tCPA
tCPA tGA
tGA
tGA
tPC
tPC
tCP
tCP
tCAS
tRCD
tCRP tCAS
tRHCP tCRP
tCAS
tRAD tASR tRCP
tRAL
tCAH
tASC
tCAH tASC
tCSH
tCAH tASC
tASR
tCAC
tCAC
tCAC tOFF
tGZ
tCLZ
tOFF
tOFF
tGZ
tGZ
tCLZ
tCLZ
tRAC
Dout 1 Dout N
Dout 2
ROW COLUMN 2COLUMN 1 COLUMN N
tRSH
tRAH
MCM54260B•MCM5L4260B•MCM5S4260B
21
MOTOROLA DRAM
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
RAS VIL
VIH
UCAS, LCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ0 – DQ15 VOH
VOL
tRASP tRP
tCRP
tRSH
tCAS
tPC
tPC
tCAS
tCAS
tCP
tRCD
tCRP
tRAH
tASR tASC tASC tASC
tCP
tRAL
tCAH
tCAH
tCAH
ROW COLUMN 2COLUMN 1 COLUMN 3
tCSH
Din 1 Din 2 Din N
tRAD
tWCS
tCWL tCWL tCWL
tWP tWP tWCH
tWCH
tWCH
tRWL
tWCS
tWCS
tDS
tDH tDS tDS
tDH tDH
tWP
MCM54260B•MCM5L4260B•MCM5S4260B
22 MOTOROLA DRAM
FAST PAGE MODE BYTE WRITE CYCLE (EARLY WRITE)
tRAH
tASR tASC tASC tASC
tCAH
tCAH
tCAH
ROW COLUMN 2COLUMN 1 COLUMN 3
tCSH
tRAD
tWCS
tCWL tCWL tCWL
tWP tWP tWCH
tWCH
tWCH
tRWL
tWCS
tWCS
Din 1
Din 2
Din N
tRASP tRP
tCRP
tRSH
tCAS
tCAS
tCP
tCP
tRCD
tCRP
tCRP tCAS tRPC
tRAL
tDS
tDS tDS tDH
tDH
tDH
RAS VIL
VIH
UCAS VIL
VIH
A0 – A8 VIL
VIH
WRITE VIL
VIH
GVIL
VIH
DQ8 – DQ15 VIH
VIL
LCAS VIL
VIH
DQ0 – DQ7 VIH
VIL
tPC
tPC
tWP
MCM54260B•MCM5L4260B•MCM5S4260B
23
MOTOROLA DRAM
FAST PAGE MODE READ–MODIFY–WRITE CYCLE
tCRP
RAS VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
UCAS,
LCAS
A0 – A8
WRITE
G
DQ0 –
DQ15
tPRMW
tRASP
tCSH
tPRMW
tCAS tCAS tRSH
tCAS
tRAL
tRWD
tCWD
tCWD
tCPWD tCWD
tAWD
tAWD
tAWD
tCPA tCPA
tAA tAA
tAA
tRAC
tRCD tCP
tCAH
tASC
tCAH tASC
tRWL
tWP
tDS
tDH
tGZ
tDH
tGZ
ROW
COL. 1 COL. 2 COL. N
tGD tDS
tGA
tGZ
tCLZ tDH
tCLZ tCLZ
tDS tGD
tCAC
tWP
tWP
tCWL
tCWL tGA tGA
tCAH
tCP
tRAH
tASR tASC
tRCS
tRP
tCWL
tRAD
tCAC
tCAC
tCPWD
Din2
Dout2
Din1
Dout1DoutN
DinN
Din2
tGD
MCM54260B•MCM5L4260B•MCM5S4260B
24 MOTOROLA DRAM
FAST PAGE MODE BYTE READ–MODIFY–WRITE CYCLE
Din2
tRAC
tRASP
tCSH
tCAS
tRCD
tCAH
tRP
tCRP
tPRMW
tPRMW
tCAS
tCAS
tRAL
tRWD tCWD tCWD
tCPWD tCWD
tAWD
tAWD
tAWD
tAA tAA
tAA
tCP
tCAH
tASC
tCAH tASC
tRWL
tWP
tGA tWP
tCWL
tCWL
tGA tGA
tCP
tRAD
tASR tASC
tRCS
tCWL
tCPWD
tWP
tRAH
tCPA tCPA
tDH
tGZ
tCLZ
tDS
tCAC tCAC
tCAC
tGD tDS
tDH tCLZ tDH
tGZ
tGD tDS
tGZ
tCLZ
COL. 1 COL. 2 COL. N
Dout2
Din1
Dout1DoutN
DinN
RAS VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
UCAS
A0 – A8
WRITE
G
DQ0 –
DQ7
VIH
VIL
VOH
VOL
DQ8 –
DQ15
VIH
VIL
LCAS
ROW
tRSH
tGD
MCM54260B•MCM5L4260B•MCM5S4260B
25
MOTOROLA DRAM
RAS–ONLY REFRESH CYCLE
RAS VIH
VIL
VIH
VIL
VIH
VIL
UCAS, LCAS
A0 – A8
tRPC
ROW
tRC tRP
tRAS
tRAH
tCRP
tASR
NOTE: WRITE, G = “H” or “L”
CAS BEFORE RAS REFRESH CYCLE
RAS VIH
VIL
VIH
VIL
VOH
VOL
UCAS, LCAS
NOTE: WRITE, G, A0 – A8= “H” or “L”
CAS before RAS refresh is performed when either UCAS or LCAS meets this timing.
tRPC
tRC tRP
tCP tCSR
tRAS
OPEN
tRP
tCHR
DQ0 – DQ15
MCM54260B•MCM5L4260B•MCM5S4260B
26 MOTOROLA DRAM
HIDDEN REFRESH CYCLE (READ)
RAS VIH
VIL
VIH
VIL
VIH
VIL
UCAS, LCAS
A0 – A8
tCAH
VIH
VIL
WRITE
VIH
VIL
G
VOH
VOL
DQ0 – DQ15
tRAS tRC tRP tRAS
tCHR tCRP
tRSH
tRCD
tCAC
tRAC
tGZ
tRC
tASC
tRRH
tGA
tOFF
tRP
tASR
tCRP
tRAH tRCS
tCLZ
tRAD
COLUMN
ROW
DATA – OUT
tAA
MCM54260B•MCM5L4260B•MCM5S4260B
27
MOTOROLA DRAM
HIDDEN REFRESH CYCLE (WRITE)
RAS VIH
VIL
VIH
VIL
VIH
VIL
UCAS, LCAS
A0 – A8
VIH
VIL
WRITE
VIH
VIL
G
VOH
VOL
DQ0 – DQ15
tCAH
tRAS tRC tRP tRAS
tCHR tCRP
tRSH
tRCD
tRC
tASC
tRP
tASR
tCRP
tRAD
COLUMN
ROW
tRAH
tWCS
tDS
tWCH
tWP
tDH
DATA – IN
MCM54260B•MCM5L4260B•MCM5S4260B
28 MOTOROLA DRAM
CAS BEFORE RAS REFRESH COUNTER TEST READ CYCLE
RAS VIH
VIL
VIH
VIL
VIH
VIL
UCAS, LCAS
A0 – A8
VIH
VIL
WRITE
VIH
VIL
G
VOH
VOL
DQ0 – DQ15
tRAS
tASC
tRP
tRSH
tRAL
tCAL
tCHR
tROH
tAA tGZ
tCPT tCAS
tCAC
tCLZ
tCSR
tRCS
tGA
tRRH
tRCH
tCRP
tOFF
COLUMN
DATA – OUT
MCM54260B•MCM5L4260B•MCM5S4260B
29
MOTOROLA DRAM
CAS BEFORE RAS REFRESH COUNTER TEST WRITE CYCLE
RAS VIH
VIL
VIH
VIL
VIH
VIL
UCAS, LCAS
A0 – A8
VIH
VIL
WRITE
VIH
VIL
G
VIH
VIL
DQ0 – DQ15
tRAS
tASC
tRSH
tRAL
tCAL
tCHR tCPT tCAS
tCSR tCRP
COLUMN
tRWL
tCWL
tWCH
tDH
tWCS
tDS
DATA – IN
tRP
MCM54260B•MCM5L4260B•MCM5S4260B
30 MOTOROLA DRAM
CAS BEFORE RAS REFRESH COUNTER TEST READ–MODIFY–WRITE CYCLE
RAS VIH
VIL
VIH
VIL
VIH
VIL
UCAS, LCAS
A0 – A8
VIH
VIL
WRITE
VIH
VIL
G
VIH
VIL
DQ0 – DQ15
tRAS
tASC
tRSH
tRAL
tCAL
tCHR tCPT tCAS
tCSR tCRP
COLUMN
tAWD
tCWD tRWL
tAA
tRCS
tCAC
tCLZ
tDS
tWP
tGA
tDH
tGD
tGZ
tCWL
VOH
VOL Dout
Din
tRP
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
Package (J = 400 mil SOJ, T = 400 mil TSOP)
Shipping Method (Blank = Rails or
Tray, R = Tape and Reel)
Speed (70 = 70 ns, 80 = 80 ns, 10 = 100 ns)
MCM
54260B
5L4260B
5S4260B X XX XX
Full Part Numbers — MCM54260BJ70 MCM5L4260BJ70 MCM5S4260BJ70
MCM54260BJ80 MCM5L4260BJ80 MCM5S4260BJ80
MCM54260BJ10 MCM5L4260BJ100 MCM5S4260BJ10
MCM54260BT70 MCM5L4260BT70 MCM5S4260BT70
MCM54260BT80 MCM5L4260BT80 MCM5S4260BT80
MCM54260BT10 MCM5L4260BT10 MCM5S4260BT10
MCM54260BJ70R MCM5L4260BJ70R MCM5S4260BJ70R
MCM54260BJ80R MCM5L4260BJ80R MCM5S4260BJ80R
MCM54260BJ10R MCM5L4260BJ10R MCM5S4260BJ10R
MCM54260BT70R MCM5L4260BT70R MCM5S4260BT70R
MCM54260BT80R MCM5L4260BT80R MCM5S4260BT80R
MCM54260BT10R MCM5L4260BT10R MCM5S4260BT10R
MCM54260B•MCM5L4260B•MCM5S4260B
31
MOTOROLA DRAM
PACKAGE DIMENSIONS
J PACKAGE
400 MIL SOJ
CASE 923A–01
40 X R
40 X F
40 X N
-T-
0.004 (0.10) T
SEATING
PLANE
DETAIL H
2 X L38 X G
K
A
-X-
B
-Y-
40 21
1 20
R
PC
E
0.007 (0.18) MT Y X
S S
0.015 (0.38) T Y
0.007 (0.18) LT Y X
S S
40 X D
0.007 (0.18) MT Y X
S S
NOTE 3
2 ZONES 20 X
NOTE 3
DETAIL H
DIM
AMIN MAX MIN MAX
MILLIMETERS
1.020 1.030 25.91 26.16
INCHES
B0.395 0.405 10.03 10.29
C0.128 0.148 3.25 3.76
D0.012 0.021 0.33 0.53
E0.082 ––– 2.08 –––
F0.024 0.032 0.61 0.81
G0.050 BSC 1.27 BSC
J0.030 0.040 0.77 1.01
K0.031 ––– 0.80 –––
L0.025 BSC 0.635 BSC
N0.035 0.045 0.89 1.14
P0.430 0.440 10.92 11.18
R0.366 BSC 9.30 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE -T-.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.006 (0.15) PER SIDE.
5. DIMENSIONS A AND B INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT THE
PARTING LINE.
J
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer .
MCM54260B•MCM5L4260B•MCM5S4260B
32 MOTOROLA DRAM
T PACKAGE
400 MIL TSOP
CASE 924–01
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.004 (0.10)
SEATING
PLANE
0.008 (0.20) T Y
A
B
B
E
C
4 x R
36 x G
20 x S
LKW
BASE METAL
RAD
VRAD T
F
JN
D
0.008 (0.20) T Z
DETAIL A
ROTATED 90° CLOCK-
WISE SECTION
B-B
DETAIL
A
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE MOLD
PROTRUSION IS 0.006 (0.15) PER SIDE.
4. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSIONS
SHALL NOT ALLOW THE D DIMENSION TO
EXCEED 0.023.
44 35 32 23
1 10 13 22
-Z-
-Y-
B
M S
-T-
M S
DIM
AMIN MAX MIN MAX
MILLIMETERS
0.721 0.729 18.313 18.517
INCHES
B0.396 0.404 10.058 10.262
C––– 0.050 ––– 1.270
D0.012 0.018 0.305 0.457
E0.038 0.042 0.965 1.067
F0.012 0.016 0.305 0.406
G0.315 BSC 0.800 BSC
J0.005 0.008 0.127 0.203
K0.016 0.023 0.406 0.584
L0.002 0.006 0.051 0.152
N0.004 0.006 0.101 0.152
R0.0472 BSC 1.200 BSC
S0.456 0.470 11.582 11.938
T0.004 REF 0.100 REF
V0.004 REF 0.100 REF
W0 5 0 5
_ _ _ _
How to reach us:
USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MCM54260B/D
*MCM54260B/D*
◊
