TLE42794
Low Dropout Fixed Voltage Regulator
Data Sheet, Rev. 1.1, October 2008
Automotive Power
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PG-DSO-8
PG-DSO-14
PG-SSOP-14 exposed pad
Type Package Marking
TLE42794G PG-DSO-8 42794G
TLE42794GM PG-DSO-14 42794GM
TLE42794E PG-SSOP-14 exposed pad 42794E
Data Sheet 2 Rev. 1.1, 2008-10-09
TLE42794Low Dropout Fixed Voltage Regulator
1Overview
Features
• Output Voltage 5 V ± 2%
• Ouput Current up to 150 mA
• Very low Current Consumption
• Early Warning
• Power-on and Undervoltage Reset with Programmable Delay Time
• Reset Low Down to VQ = 1 V
• Adjustable Reset Threshold
• Very Low Dropout Voltage
• Output Current Limitation
• Reverse Polarity Protection
• Overtemperature Protection
• Suitable for Use in Automotive Electronics
• Wide Temperature Range from -40 °C up to 150 °C
• Input Voltage Range from -42 V to 45 V
• Green Product (RoHS compliant)
• AEC Qualified
Description
The TLE42794G is a monolithic integrated low dropout voltage
regulator, especially designed for automotive applications. An input
voltage up to 45 V is regulated to an output voltage of 5.0 V. The
component is able to drive loads up to 150 mA. It is short-circuit
protected by the implemented current limitation and has an integrated
overtemperature shutdown. A reset signal is generated for an output
voltage VQ,rt of typically 4.65 V. This threshold can be decreased by
an external resistor divider. The power-on reset delay time can be
programmed by the external delay capacitor. The additional sense
comparator provides an early warning function: Any voltage (e.g. the
input voltage) can be monitored, an under-voltage condition is indicated
by setting the comparator’s output to low. If pull-up resistors are desired
at the outputs of the reset and the sense comparator, the TLE42694 with
integrated pull-up reistors can be used instead of the TLE42794.
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Data Sheet 3 Rev. 1.1, 2008-10-09
TLE42794
Overview
Dimensioning Information on External Components
The input capacitor CI is recommended for compensation of line influences. The output capacitor CQ is necessary
for the stability of the control loop.
Circuit Description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any
oversaturation of the power element. The component also has a number of internal circuits for protection against:
• Overload
• Overtemperature
• Reverse polarity
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TLE42794
Block Diagram
Data Sheet 4 Rev. 1.1, 2008-10-09
2 Block Diagram
Figure 1 Block Diagram
AEB01955
Control
Saturation
Current and
Reference
Trimming
Amplifier
Error
Reference
Ι
D
RADJ
SI
Q
RO
SO
&
GND
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Data Sheet 5 Rev. 1.1, 2008-10-09
TLE42794
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment TLE42794G (PG-DSO-8)
Figure 2 Pin Configuration (top view)
3.2 Pin Definitions and Functions TLE42794G (PG-DSO-8)
Pin Symbol Function
1I Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
2SI Sense Input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
3RADJ Reset Threshold Adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
4D Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
5GND Ground
6RO Reset Output
open collector output; external pull-up resistor required, respecting values given in
Item 5.6.5;
leave open if the reset function is not needed
7SO Sense Output
open collector output; external pull-up resistor required, respecting values given in
Item 5.8.6;
leave open if the sense comparator is not needed
8Q Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in “Functional Range” on Page 9
GND
RO
SO
D5
6
7
RADJ
8
4
3
2
1
AEP01668
Q
ΙS
Ι
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TLE42794
Pin Configuration
Data Sheet 6 Rev. 1.1, 2008-10-09
3.3 Pin Assignment TLE42794GM (PG-DSO-14)
Figure 3 Pin Configuration (top view)
3.4 Pin Definitions and Functions TLE42794GM (PG-DSO-14)
Table 1
Pin Symbol Function
1RADJ Reset Threshold Adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2D Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
3, 4, 5, 6 GND Ground
connect all pins to PCB and heatsink area
7RO Reset Output
open collector output; external pull-up resistor required, respecting values given in
Item 5.6.5;
leave open if the reset function is not needed
8SO Sense Output
open collector output; external pull-up resistor required, respecting values given in
Item 5.8.6;
leave open if the sense comparator is not needed
9Q Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 9
10, 11, 12 GND Ground
connect all pins to PCB and heatsink area
13 I Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
14 SI Sense Input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
AEP02248
Q
GND
SI
GND
RO
GND
Ι
10
9
GND GND
1
2
3
4
5
GND
6
7SO
14
13
12
11
D
GND
8
RADJ
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Data Sheet 7 Rev. 1.1, 2008-10-09
TLE42794
Pin Configuration
3.5 Pin Assignment TLE42794E (PG-SSOP-14 exposed pad)
Figure 4 Pin Configuration (top view)
3.6 Pin Definitions and Functions TLE42794E (PG-SSOP-14 exposed pad)
Table 2
Pin Symbol Function
1RADJ Reset Threshold Adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2, 5, 6 n.c. not connected
3D Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
4GND Ground
connect all pins to PCB and heatsink area
7RO Reset Output
open collector output; external pull-up resistor required, respecting values given in
Item 5.6.4;
leave open if the reset function is not needed
8SO Sense Output
open collector output; external pull-up resistor required, respecting values given in
Item 5.8.6;
leave open if the sense comparator is not needed
9, 10, 12 n.c. not connected
11 Q Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 9
13 I Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
14 SI Sense Input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
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TLE42794
General Product Characteristics
Data Sheet 8 Rev. 1.1, 2008-10-09
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Absolute Maximum Ratings 1)
-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
1) not subject to production test, specified by design
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Input, Sense Input
4.1.1 Voltage VI-40 45 V –
Output, Reset Output, Sense Output
4.1.2 Voltage VQ-0.3 7 V –
Reset Delay, Reset Threshold
4.1.3 Voltage VD-0.3 7 V –
Temperature
4.1.4 Junction Temperature Tj-40 150 °C–
4.1.5 Storage Temperature Tstg -50 150 °C–
ESD Absorption
4.1.6 ESD Absorption VESD,HBM -2 2 kV Human Body
Model (HBM)2)
2) ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114
4.1.7 VESD,CDM -500 500 V Charge Device
Model (CDM)3)
3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1
4.1.8 -750 750 V Charge Device
Model (CDM)3) at
corner pins
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Data Sheet 9 Rev. 1.1, 2008-10-09
TLE42794
General Product Characteristics
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Input Voltage VI5.5 45 V –
4.2.2 Output Capacitor’s Requirements
for Stability
CQ10 – µF –1)
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
ESR(CQ)–3Ω–2)
2) relevant ESR value at f=10kHz
4.2.3 Junction Temperature Tj-40 150 °C–
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TLE42794
General Product Characteristics
Data Sheet 10 Rev. 1.1, 2008-10-09
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Value Unit Conditions
Min. Typ. Max.
TLE42794G (PG-DSO-8)
4.3.4 Junction to Soldering Point1)
1) not subject to production test, specified by design
RthJSP – 80 – K/W measured to pin 5
4.3.5 Junction to Ambient1) RthJA –113–K/W
2)
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.6 – 172 – K/W Footprint only3)
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
4.3.7 – 142 – K/W 300mm2 heatsink area on
PCB3)
4.3.8 – 136 – K/W 600mm2 heatsink area on
PCB3)
TLE42794GM (PG-DSO-14)
4.3.9 Junction to Soldering Point1) RthJSP – 27 – K/W measured to group of pins
3, 4, 5, 10, 11, 12
4.3.10 Junction to Ambient1) RthJA –63–K/W
2)
4.3.11 – 104 – K/W Footprint only3)
4.3.12 – 73 – K/W 300mm2 heatsink area on
PCB3)
4.3.13 – 65 – K/W 600mm2 heatsink area on
PCB3)
TLE42794E (PG-SSOP-14 exposed pad)
4.3.14 Junction to Case1) RthJC – 10 – K/W measured to Exposed
Pad
4.3.15 Junction to Ambient1) RthJA –47–K/W
2)
4.3.16 – 145 – K/W Footprint only3)
4.3.17 – 63 – K/W 300mm2 heatsink area on
PCB3)
4.3.18 – 53 – K/W 600mm2 heatsink area on
PCB3)
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Data Sheet 11 Rev. 1.1, 2008-10-09
TLE42794
Block Description and Electrical Characteristics
5 Block Description and Electrical Characteristics
5.1 Voltage Regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output
capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional
Range” on Page 9 have to be maintained. For details see also the typical performance graph “Output Capacitor
Series Resistor ESR(CQ) versus Output Current IQ” on Page 14. As the output capacitor also has to buffer
load steps it should be sized according to the application’s needs.
An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the
component’s terminals.
A protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown
in case of overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the package,
the maximum output current is decreased at input voltages above VI=22V.
The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output
continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction
temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.
The TLE42794 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC,
increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal
protection circuit is not operating during reverse polarity conditions.
Figure 5 Voltage Regulator
Bandgap
Reference
GND
QI
BlockDiagram_VoltageR egul ator.vsd
Saturation Control
Current Limitation
Temperature
Shutdown
C
Q
ESR
C
}
LOAD
Supply
C
I
Regulated
Output Voltage
I
Q
I
I
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TLE42794
Block Description and Electrical Characteristics
Data Sheet 12 Rev. 1.1, 2008-10-09
5.2 Electrical Characteristics Voltage Regulator
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.2.1 Output Voltage VQ4.9 5.0 5.1 V 100 µA < IQ < 100 mA
6V
< VI < 18 V
5.2.2 Output Current Limitation IQ,max 150 200 500 mA VQ = 4.8V
5.2.3 Load Regulation
steady-state
∆VQ,load -30 -15 – mV IQ = 5mA to 100mA
VI = 6 V
5.2.4 Line Regulation
steady-state
∆VQ,line –1040mVVI = 6 V to 32 V
IQ = 5 mA
5.2.5 Dropout Voltage1)
Vdr = VI - VQ
1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V
Vdr – 250 500 mV IQ = 100 mA
5.2.6 Overtemperature Shutdown
Threshold
Tj,sd 151 – 200 °C Tj increasing2)
2) not subject to production test, specified by design
5.2.7 Overtemperature Shutdown
Threshold Hysteresis
Tj,sdh –15–°CTj decreasing2)
5.2.8 Power Supply Ripple
Rejection2)
PSRR –70–dB
fripple = 100 Hz
Vripple = 0.5 Vpp
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Data Sheet 13 Rev. 1.1, 2008-10-09
TLE42794
Block Description and Electrical Characteristics
5.3 Typical Performance Characteristics Voltage Regulator
Output Voltage VQ versus
Junction Temperature TJ
Output Current IQ versus
Input Voltage VI
Power Supply Ripple Rejection PSRR versus
ripple frequency fr
Line Regulation ∆VQ,line versus
Input Voltage VI
01_VQ_TJ.VSD
4,6
4,7
4,8
4,9
5
5,1
5,2
-40 0 40 80 120 160
Tj [°C]
V
Q
[V]
I
Q
= 5 mA
V
I
= 13.5 V
02_IQ_VI.VSD
0
50
100
150
200
250
300
0 10203040
V
I
[V]
I
Q,max
[mA]
V
Q
= 4.8 V
T
j
= -40 °C
T
j
= 25 °C
T
j
= 150 °C
03_PSRR_FR.VSD
0
10
20
30
40
50
60
70
80
90
0,01 0,1 1 10 100 1000
f
[kHz]
PSRR
[dB ]
Tj
=25°C
IQ
= 10 mA
CQ
=10µF ceramic
04_DVQ_DVI.VSD
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
0 10203040
VI
[V]
∆
V
Q
[mV]
I
Q = 5 mA
T
j = -40 °C
T
j = 25 °C
T
j = 150 °C
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TLE42794
Block Description and Electrical Characteristics
Data Sheet 14 Rev. 1.1, 2008-10-09
Load Regulation ∆VQ,load versus
Output Current IQ
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
Dropout Voltage Vdr versus
Output Current IQ
Dropout Voltage Vdr versus
Junction Temperature Ti
05_DVQ_DIQ.VSD
-14
-12
-10
-8
-6
-4
-2
0
0 20 40 60 80 100
I
Q [mA]
∆
V
Q [mV]
V
I
= 13.5 V
T
j
= -40
T
j
= 25 °C
T
j
= 150
06_ESR_IQ.VSD
0,01
0,1
1
10
100
0 50 100 150
I
Q [mA]
ESR(C
Q
)
[Ω]
CQ = 10 µF
VI = 13.5 V
Stable
Region
Unstable
Region
07_VDR_IQ.VSD
0
50
100
150
200
250
300
0 20406080100
IQ [mA]
VDR [mV]
Tj = 150 °C
Tj = 25 °C
Tj = -40 °C
08_VDR_TJ.VSD
0
50
100
150
200
250
300
-40 0 40 80 120 160
T
j
[°C]
V
DR
[mV]
IQ
= 100 mA
IQ
= 25 mA
IQ
= 5 mA
IQ
= 100 µA
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Data Sheet 15 Rev. 1.1, 2008-10-09
TLE42794
Block Description and Electrical Characteristics
5.4 Current Consumption
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.4.1 Current Consumption
Iq = IQ - II
Iq–210280µAIQ = 100 µA
Tj = 25 °C
5.4.2 – 240 300 µA IQ = 100 µA
Tj ≤ 85 °C
5.4.3 – 0.7 1 mA IQ = 10 mA
5.4.4 – 3.5 8 mA IQ = 50 mA
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TLE42794
Block Description and Electrical Characteristics
Data Sheet 16 Rev. 1.1, 2008-10-09
5.5 Typical Performance Characteristics Current Consumption
Current Consumption Iq versus
Output Current IQ (IQ low)
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Input Voltage VI
09_IQ_IQ_IQLOW.VSD
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
0 5 10 15 20 25
I
Q
[mA]
I
q
[mA]
VI
= 13.5 V
Tj
=25°C
10_IQ_IQ.VSD
0
2
4
6
8
10
12
020406080100120
I
Q
[mA]
I
q
[mA]
VI
= 13.5 V
Tj
= 25 °C
11_IQ_VI.VSD
0
1
2
3
4
5
6
0 10203040
V
I
[V]
I
q
[mA]
R
LOAD
= 100 Ω
R
LOAD
= 50 k Ω
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Data Sheet 17 Rev. 1.1, 2008-10-09
TLE42794
Block Description and Electrical Characteristics
5.6 Reset Function
The reset function provides several features:
Output Undervoltage Reset:
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used
to reset a microcontroller during low supply voltage.
Power-On Reset Delay Time:
The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame
from exceeding the reset switching threshold VRT until the reset is released by switching the reset output “RO” from
“low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D
charged by the delay capacitor charge current ID,ch starting from VD=0V.
If the application needs a power-on reset delay time trd different from the value given in Item 5.6.7, the delay
capacitor’s value can be derived from the specified values in Item 5.6.7 and the desired power-on delay time:
with
•CD: capacitance of the delay capacitor to be chosen
•trd,new: desired power-on reset delay time
•trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Reset Reaction Time:
The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset
reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay
capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes:
with
•trr: reset reaction time
•trr,int: internal reset reaction time
•trr,d: reset discharge
CD
trd new,
trd
---------------- 47nF×=
trr trd int,trr d,
+=
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TLE42794
Block Description and Electrical Characteristics
Data Sheet 18 Rev. 1.1, 2008-10-09
Reset Output Pull-Up Resistor RRO:
The Reset Output RO is an open collector output requiring an external pull-up resistor. In Table “Electrical
Characteristics Reset Function” on Page 20 a minimum value for the external resistor RRO is given. Keep in
mind to stay within the values specified for the Reset Output RO in Table 4.1 “Absolute Maximum Ratings” on
Page 8
Reset Adjust Function
The undervoltage reset switching threshold can be adjusted according to the application’s needs by connecting
an external voltage divider (RADJ1,RADJ2) at pin RADJ. For selecting the default threshold connect pin RADJ to
GND.
When dimensioning the voltage divider, take into consideration that there will be an additional current constantly
flowing through the resistors.
With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows:
with
•VRT,new: the desired new reset switching threshold
•RADJ1, RADJ2: resistors of the external voltage divider
•VRADJ,th: reset adjust switching threshold given in Table “Electrical Characteristics Reset Function” on
Page 20
Figure 6 Block Diagram Reset Function
VRT new,
RADJ 1,R+ADJ 2,
RADJ 2,
------------------------------------------ VRADJ th,
×=
GND
QI
BlockDiagram_ResetAdjust.vsd
OR
Supply
RO
V
DST
Int.
Supply
I
D,ch
I
D,dch
V
RADJ,t h
RADJ
Control
D
C
D
Reset
optional
C
Q
VDD
Micro-
Controller
GND
R
ADJ,1
R
ADJ,2
I
RO
I
RADJ
R
RO
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Data Sheet 19 Rev. 1.1, 2008-10-09
TLE42794
Block Description and Electrical Characteristics
Figure 7 Timing Diagram Reset
VI
t
VQ
t
VRT
VRO
TimingDiagram_Reset.v
s
t
VRO,low
1 V
1V
trr,total
trd
Thermal
Shutdown
Input
Voltage Dip
tr r ,to ta l
trd trd
t < tr r ,to ta l
trd
Under-
voltage
Spike at
output
Over-
load
trr,total
VDRL
VDU
t
VD
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TLE42794
Block Description and Electrical Characteristics
Data Sheet 20 Rev. 1.1, 2008-10-09
Electrical Characteristics Reset Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Output Undervoltage Reset
5.6.1 Default Output Undervoltage Reset
Switching Thresholds
VRT 4.5 4.65 4.8 V VQ decreasing
Output Undervoltage Reset Threshold Adjustment
5.6.2 Reset Adjust
Switching Threshold
VRADJ,th 1.26 1.35 1.44 V 3.5 V ≤ VQ < 5 V
5.6.3 Reset Adjustment Range1)
1) VRT is scaled linearly, in case the Reset Switching Threshold is modified
VRT,range 3.50 – 4.65 V –
Reset Output RO
5.6.4 Reset Output Low Voltage VRO,low –0.10.4V1V ≤ VQ ≤ VRT
external
RRO,ext =10kΩ
5.6.5 Reset Output External
Pull-up Resistor to VQ
RRO,ext 10 – – kΩ1V ≤ VQ ≤ VRT ;
VRO ≤ 0.4 V
Reset Delay Timing
5.6.6 Delay Pin Output Voltage VD––5V–
5.6.7 Power On Reset Delay Time trd 17 28 39 ms CD = 100 nF
5.6.8 Upper Delay
Switching Threshold
VDU – 1.8 – V –
5.6.9 Lower Delay
Switching Threshold
VDL –0.45–V–
5.6.10 Delay Capacitor
Charge Current
ID,ch –6.5–µAVD = 1 V
5.6.11 Delay Capacitor
Reset Discharge Current
ID,dch – 70 – mA VD = 1 V
5.6.12 Delay Capacitor
Discharge Time
trr,d – 1.9 3 µs Calculated Value:
trr,d = CD*(VDU -
VDL)/ ID,dch
CD = 100 nF
5.6.13 Internal Reset Reaction Time trr,int –37µsCD = 0 nF 2)
2) parameter not subject to production test; specified by design
5.6.14 Reset Reaction Time trr,total – 4.9 10 µs Calculated Value:
trr,total = trr,int + trr,d
CD = 100 nF
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Data Sheet 21 Rev. 1.1, 2008-10-09
TLE42794
Block Description and Electrical Characteristics
5.7 Typical Performance Characteristics Reset
Power On Reset Delay Time trd versus
Junction Temperature Tj
12_TRD_TJ.VSD
0
5
10
15
20
25
30
35
-40 0 40 80 120 160
T
j
[°C]
t
rd
[ms]
C
D
= 100 nF
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TLE42794
Block Description and Electrical Characteristics
Data Sheet 22 Rev. 1.1, 2008-10-09
5.8 Early Warning Function
The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can be
monitored, an undervoltage condition is indicated by setting the comparator’s output to low.
Figure 8 Sense Timing Diagram
Electrical Characteristics Early Warning Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Sense Comparator Input
5.8.1 Sense Threshold High VSI,high 1.24 1.31 1.38 V –
5.8.2 Sense Threshold Low VSI,low 1.16 1.22 1.28 V –
5.8.3 Sense Switching Hysteresis VSI,hy 20 90 160 mV –
5.8.4 Sense Input Current ISI -1 -0.1 1 µA –
AED03049
t
Sense
t
SI, High
V
SI, Low
V
Input
Voltage
High
Low
Output
Sense
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Data Sheet 23 Rev. 1.1, 2008-10-09
TLE42794
Block Description and Electrical Characteristics
Sense Comparator Output
5.8.5 Sense Output Low Voltage VSO,low –0.10.4VVSI < VSI,low
VI > 5.5 V
RSO,ext =10kΩ
5.8.6 Sense Output External
Pull-up Resistor to VQ
RSO,ext 10 – – kΩVI > 5.5 V
VSO ≤ 0.4 V
Electrical Characteristics Early Warning Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
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TLE42794
Package Outlines
Data Sheet 24 Rev. 1.1, 2008-10-09
6 Package Outlines
Figure 9 PG-DSO-8
+0.06
0.19
0.35 x 45˚
1)
-0.2
4
C
8 MAX.
0.64
±0.2
6
±0.25
0.2 8x
M
C
1.27
+0.1
0.41 0.2
M
A
-0.06
1.75 MAX.
(1.45)
±0.07
0.175
B
8x
B
2)
Index Marking
5
-0.21)
41
85
A
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
GPS01181
0.1
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Data Sheet 25 Rev. 1.1, 2008-10-09
TLE42794
Package Outlines
Figure 10 PG-DSO-14
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
-0.2
8.75 1)
0.64
0.19
+0.06
Index Marking
1.27
+0.10
0.41
0.1
1
14
2)
7
14x
8
0.175
(1.47)
±
0.07
±0.2
6
0.35 x 45˚
-0.2
1.75 MAX.
41)
±0.25
8˚MAX.
-0.06
0.2 MAB
M
0.2 C
C
B
A
GPS01230
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TLE42794
Package Outlines
Data Sheet 26 Rev. 1.1, 2008-10-09
Figure 11 PG-SSOP-14 exposed pad
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
PG-SSOP-14-1,-2,-3-PO V02
17
14 8
14
17
8
14x
0.25
±0.05 2)
M
0.15 DC A-B
0.65 C
Stand Off
0 ... 0.1
(1.45)
1.7 MAX.
0.08 C
A
B
4.9
±0.11)
A-BC0.1 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
Bottom View
±0.2
3
±0.2
2.65
0.2
±0.2
D6
M
D 8x
0.64
±0.25
3.9
±0.11)
0.35 x 45˚
0.1 CD
+0.06
0.19
8
˚
MAX.
Index Marking
Exposed
Diepad
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
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Data Sheet 27 Rev. 1.1, 2008-10-09
TLE42794
Revision History
7 Revision History
Revision Date Changes
1.1 2008-10-09 package version TLE42794E in PG-SSOP-14 exposed pad and all related
information added
In “Overview” on Page 2 package graphic for PG-SSOP-14 exposed pad and
product name “TLE42794E” added
In Chapter 3 “Pin Assignment TLE42794E (PG-SSOP-14 exposed pad)” on
Page 7 and “Pin Definitions and Functions TLE42794E (PG-SSOP-14
exposed pad)” on Page 7 added
In “Thermal Resistance” on Page 10 values for TLE42794E added
In “Package Outlines” on Page 24 outlines for TLE4279E added
1.0 2008-09-19 initial version data sheet
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Edition 2008-10-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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