0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz ADRF5720 Data Sheet FUNCTIONAL BLOCK DIAGRAM D5/CLK D4/SERIN D3/SEROUT D2 D1 D0 ADRF5720 24 23 22 21 20 19 LE 1 18 VDD PS 2 17 VSS GND 3 16 GND GND 4 15 GND ATTIN 5 14 ATTOUT GND 6 13 GND SERIAL/ PARALLEL INTERFACE 6-BIT DIGITAL ATTENUATOR 12 PACKAGE BASE GND 15959-001 11 GND 10 GND 9 GND 8 GND 7 GND Ultrawideband frequency range: 9 kHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.0 dB up to 18 GHz 2.8 dB up to 26 GHz 4.5 dB up to 40 GHz Attenuation accuracy with impedance match (0.20 + 1.0% of attenuation state) up to 18 GHz (0.20 + 1.5% of attenuation state) up to 26 GHz (0.40+ 3.0% of attenuation state) up to 40 GHz Typical step error with impedance match 0.25 dB up to 26 GHz 0.65 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 8 s 24-terminal, 4 mm x 4 mm LGA package Pin-compatible with ADRF5730, fast switching version GND FEATURES Figure 1. APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5720 is a silicon, 6-bit digital attenuator with 31.5 dB attenuation control range in 0.5 dB steps. The ADRF5720 is pin-compatible with the ADRF5730, the fast switching version, which operates from 100 MHz to 40 GHz. This device operates from 9 kHz to 40 GHz with better than 4.5 dB of insertion loss and excellent attenuation accuracy. The ATTIN port of the ADRF5720 has a radio frequency (RF) input power handling capability of 27 dBm average and 30 dBm peak for all states. The ADRF5720 RF ports are designed to match a characteristic impedance of 50 . For wideband applications, impedance matching on the RF transmission lines can further optimize high frequency insertion loss, return loss, and attenuation accuracy characteristics. Refer to the Electrical Specifications section, the Typical Performance Characteristics section, and the Applications Information section for more details. The ADRF5720 requires a dual supply voltage of +3.3 V and -3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls. Rev. B The ADRF5720 comes in a 24-terminal, 4 mm x 4 mm, RoHS compliant, land grid array (LGA) package and operates from -40C to +105C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5720 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................8 Functional Block Diagram .............................................................. 1 Input Power Compression and Third-Order Intercept ......... 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Revision History ............................................................................... 2 Power Sequence .......................................................................... 13 Specifications..................................................................................... 3 RF Input and Output ................................................................. 13 Electrical Specifications ............................................................... 3 Serial or Parallel Mode Selection ............................................. 14 Timing Specifications .................................................................. 5 Serial Mode Interface ................................................................. 14 Absolute Maximum Ratings............................................................ 6 Parallel Mode Interface.............................................................. 15 Power Derating Curves ................................................................ 6 Applications Information .............................................................. 16 ESD Caution .................................................................................. 6 Evaluation Board ........................................................................ 16 Pin Configuration and Function Descriptions ............................. 7 Probe Matrix Board ................................................................... 18 Interface Schematics..................................................................... 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 19 REVISION HISTORY 11/2020--Rev. A to Rev. B Changes to tCH Parameter and tCO Parameter, Table 2 ................. 5 Changes to Figure 26 and Figure 27............................................. 11 Changes to Serial Mode Interface Section, Using SEROUT Section, and Figure 34 ................................................................................... 14 Deleted Figure 33; Renumbered Sequentially ............................ 14 3/2020--Rev. 0 to Rev. A Changes to RF Power Parameter, Table 1 .......................................5 Changes to Table 3.............................................................................6 Changes to Power Supply Section ................................................ 13 Added Power-Up State Section..................................................... 13 Moved Serial or Parallel Mode Selection Section and Table 7; Renumbered Sequentially ......................................................................14 7/2018--Revision 0: Initial Version Rev. B | Page 2 of 19 Data Sheet ADRF5720 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = -3.3 V, digital voltages = 0 V or VDD, case temperature (TCASE) = 25C, and 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS (IL) With Impedance Match Without Impedance Match RETURN LOSS With Impedance Match Without Impedance Match ATTENUATION Range Step Size Accuracy With Impedance Match Without Impedance Match Test Conditions/Comments See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz ATTIN and ATTOUT, all attenuation states See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Between minimum and maximum attenuation states Between any successive attenuation states Referenced to insertion loss See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Rev. B | Page 3 of 19 Min 0.009 Typ Max 40,000 Unit MHz 1.5 2.0 2.8 3.7 4.5 dB dB dB dB dB 1.6 2.1 2.7 3.6 4.6 dB dB dB dB dB 18 17 17 15 15 dB dB dB dB dB 18 15 15 14 11 dB dB dB dB dB 31.5 dB 0.5 dB (0.15 + 1.0% of state) (0.20 + 1.0% of state) (0.20 + 1.5% of state) (0.25 + 2.5% of state) (0.40 + 3.0% of state) dB dB dB dB dB (0.15 + 1.0% of state) (0.25 + 1.0% of state) (0.20 + 1.5% of state) (0.25 + 2.0% of state) (0.40 + 5.0% of state) dB dB dB dB dB ADRF5720 Parameter Step Error With Impedance Match Without Impedance Match RELATIVE PHASE With Impedance Match Without Impedance Match SWITCHING CHARACTERISTICS Rise and Fall Time (tRISE and tFALL) On and Off Time (tON and tOFF) RF Amplitude Settling Time 0.1 dB 0.05 dB Overshoot Undershoot RF Phase Settling Time 5 1 INPUT LINEARITY 1 Data Sheet Test Conditions/Comments Between any successive state See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Referenced to insertion loss See Figure 43 10 GHz 18 GHz 26 GHz 35 GHz 40 GHz See Figure 42 10 GHz 18 GHz 26 GHz 35 GHz 40 GHz All attenuation states at input power = 10 dBm 10% to 90% of RF output 50% triggered control (CTL) to 90% of RF output Min 50% triggered CTL to 0.1 dB of final RF output 50% triggered CTL to 0.05 dB of final RF output f = 5 GHz 50% triggered CTL to 5 of final RF output 50% triggered CTL to 1 of final RF output 1 MHz to 30 GHz Typ Max Unit 0.15 0.23 0.25 0.50 0.65 dB dB dB dB dB 0.15 0.23 0.25 0.40 0.70 dB dB dB dB dB 15 30 50 75 100 Degrees Degrees Degrees Degrees Degrees 15 30 50 80 105 Degrees Degrees Degrees Degrees Degrees 1.3 3.9 s s 8 10 2 -1.5 s s dB dB 3 4 s s 30 27 50 dBm dBm dBm 0.1 dB Power Compression (P0.1dB) Insertion Loss State Other Attenuation States Third-Order Intercept (IP3) DIGITAL CONTROL INPUTS Voltage Low (VINL) High (VINH) Current Low (IINL) High (IINH) Two-tone input power = 14 dBm per tone, f = 1 MHz, all attenuation states LE, PS, D0, D1, D2, D3/SEROUT 2, D4/SERIN, D5/CLK pins 0 1.2 D0, D1, D2 LE, PS, D3/SEROUT2, D4/SERIN, D5/CLK pins Rev. B | Page 4 of 19 0.8 3.3 <1 33 <1 V V A A A Data Sheet ADRF5720 Parameter DIGITAL CONTROL OUTPUT Voltage Low (VOUTL) High (VOUTH) Current (IOUTL, IOUTH) SUPPLY CURRENT Positive Supply Current Negative Supply Current RECOMMENDED OPERATING CONDITIONS Supply Voltage Positive (VDD) Negative (VSS) Digital Control Voltage RF Power 3 Input at ATTIN Input at ATTOUT Test Conditions/Comments D3/SEROUT pin2 Min Typ Max Unit 0.5 V V mA 0 0.3 VDD 0.3 VDD and VSS pins 117 -117 A A 3.15 -3.45 0 3.45 -3.15 VDD V V V -40 27 30 24 27 18 21 15 18 +105 dBm dBm dBm dBm dBm dBm dBm dBm C f = 1 MHz to 30 GHz, TCASE = 85C 4, all attenuation states Steady state average Steady state peak Hot switching average Hot switching peak Steady state average Steady state peak Hot switching average Hot switching peak Case Temperature (TCASE) Input linearity performance degrades over frequency, see Figure 30 and Figure 31. The D3/SEROUT pin is an input in parallel control mode and an output in serial control mode. See Table 5 for the pin function descriptions. For power derating over frequency, see Figure 2 to Figure 3. Applicable for all ATTIN and ATTOUT power specifications. 4 For 105C operation, the power handling degrades from the TCASE = 85C specifications by 3 dB. 1 2 3 TIMING SPECIFICATIONS See Figure 33, Figure 34, and Figure 35 for the timing diagrams. Table 2. Parameter tSCK tCS tCH tLN tLEW tLES tCKN tPH tPS tCO Description Minimum serial period, see Figure 33 Control setup time, see Figure 33 Control hold time, see Figure 33 LE setup time, see Figure 33 Minimum LE pulse width, see Figure 33 and Figure 35 Minimum LE pulse spacing, see Figure 33 Serial clock hold time from LE, see Figure 33 Hold time, see Figure 35 Setup time, see Figure 35 Clock to output (SEROUT) time, see Figure 34 Rev. B | Page 5 of 19 Min 70 15 Typ Max 3 5 10 630 0 10 2 20 25 15 15 Unit ns ns ns ns ns ns ns ns ns ns ADRF5720 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating -0.3 V to +3.6 V -3.6 V to +0.3 V -0.3 V to VDD + 0.3 V 3 mA JC is the junction to case bottom (channel to package bottom) thermal resistance. Table 4. Thermal Resistance Package Type CC-24-5 28 dBm 31 dBm 25 dBm 28 dBm JC 100 Unit C/W POWER DERATING CURVES 2 0 POWER DERATING (dB) -2 19 dBm 22 dBm 16 dBm 19 dBm -4 -6 -8 -10 -12 21 dBm 15 dBm -16 1k 135C -65C to +150C 260C 0.5 W 10k 100k 1M 10M 100M 1G 10G 100G FREQUENCY (GHz) 15959-002 -14 Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85C 2 0 -2 For power derating over frequency, see Figure 2 and Figure 3. Applicable for all ATTIN and ATTOUT power specifications. 2 For 105C operation, the power handling degrades from the TCASE = 85C specifications by 3 dB. 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. -4 -6 -8 -10 -12 -14 -16 26 28 30 32 34 36 38 40 42 FREQUENCY (GHz) 44 46 48 50 15959-003 1500 V 2000 V 1250 V POWER DERATING (dB) Parameter Positive Supply Voltage Negative Supply Voltage Digital Control Inputs Voltage Current RF Power1 (f = 1 MHz to 30 GHz, TCASE = 85C2) Input at ATTIN Steady State Average Steady State Peak Hot Switching Average Hot Switching Peak Input at ATTOUT Steady State Average Steady State Peak Hot Switching Average Hot Switching Peak RF Power Under Unbiased Condition (VDD, VSS = 0 V) Input at ATTIN Input at ATTOUT Temperature Junction (TJ) Storage Reflow Continuous Power Dissipation (PDISS) Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) ATTIN and ATTOUT Pins Digital Pins Charged Device Model (CDM) Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85C ESD CAUTION Rev. B | Page 6 of 19 Data Sheet ADRF5720 D2 D1 D0 23 22 21 20 19 LE 1 18 VDD PS 2 17 VSS GND 3 ADRF5720 16 GND TOP VIEW (Not to Scale) 13 GND 7 8 9 10 11 12 GND 6 GND ATTOUT GND GND GND 14 GND 15 GND 4 5 GND GND ATTIN NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO THE RF AND DC GROUND OF THE PCB. 15959-004 D4/SERIN 24 D3/SEROUT D5/CLK PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic LE PS 3, 4, 6 to 13, 15, 16 5 GND ATTIN 14 ATTOUT 17 18 19 20 21 22 VSS VDD D0 D1 D2 D3/SEROUT 23 D4/SERIN 24 D5/CLK EPAD Description Latch Enable Input. See the Theory of Operation section for more information. Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more information. Ground. These pins must be connected to the RF and dc ground of the PCB. Attenuator Input. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. Attenuator Output. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. Negative Supply Input. Positive Supply Input. Parallel Control Input for 0.5 dB Attenuator Bit. See the Theory of Operation section for more information. Parallel Control Input for 1 dB Attenuator Bit. See the Theory of Operation section for more information. Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information. Parallel Control Input for 4 dB Attenuator Bit (D3). Serial Data Output (SEROUT). See the Theory of Operation section for more information. Parallel Control Input for 8 dB Attenuator Bit (D4). Serial Data Input (SERIN). See the Theory of Operation section for more information. Parallel Control Input for 16 dB Attenuator Bit (D5). Serial Clock Input (CLK). See the Theory of Operation section for more information. Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB. INTERFACE SCHEMATICS VDD VDD VDD VDD LE, PS, D3/SEROUT, D4/SERIN, D5/CLK 15959-005 100k ATTIN, ATTOUT 15959-006 Figure 5. Digital Input Interface (LE, PS, D3/SEROUT, D4/SERIN, D5/CLK) Figure 6. ATTIN and ATTOUT Interface Rev. B | Page 7 of 19 15959-007 D0, D1, D2 Figure 7. Digital Input Interface (D0, D1, D2) ADRF5720 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE 0 0 -1 -1 -2 -2 -4 -5 -6 -7 +105C +85C +25C -40C -5 -6 -7 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) -10 Figure 8. Insertion Loss vs. Frequency over Temperature with Impedance Match 0 -5 NORMALIZED ATTENUATION (dB) -5 -20 -25 -35 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) INPUT RETURN LOSS (dB) -10 -20 -25 -30 -35 25 30 FREQUENCY (GHz) 35 40 45 20 25 30 35 40 45 -15 -20 -25 -30 -35 -45 Figure 10. Input Return Loss vs. Frequency (Major States Only) with Impedance Match STATE 0dB STATE 1.0dB STATE 4.0dB STATE 16.0dB STATE 0.5dB STATE 2.0dB STATE 8.0dB STATE 31.5dB 20 35 -50 15959-010 20 15 -40 STATE 0.5dB STATE 2.0dB STATE 8.0dB STATE 31.5dB 15 10 Figure 12. Normalized Attenuation vs. Frequency for All States at Room Temperature Without Impedance Match -15 10 5 FREQUENCY (GHz) -10 5 45 -30 0 0 40 -25 -5 -50 35 -20 0 -45 30 -15 -5 STATE 0dB STATE 1.0dB STATE 4.0dB STATE 16.0dB 25 -10 0 Figure 9. Normalized Attenuation vs. Frequency for All States at Room Temperature with Impedance Match -40 20 -35 15959-009 -30 15 Figure 11. Insertion Loss vs. Frequency over Temperature Without Impedance Match 0 -15 10 FREQUENCY (GHz) 0 -10 5 0 5 10 15 25 30 FREQUENCY (GHz) 40 45 15959-013 -10 +105C +85C +25C -40C -9 15959-008 -9 NORMALIZED ATTENUATION (dB) -4 -8 -8 INPUT RETURN LOSS (dB) -3 15959-012 -3 15959-011 INSERTION LOSS (dB) INSERTION LOSS (dB) VDD = 3.3 V, VSS = -3.3 V, digital voltages = 0 V or VDD, TCASE = 25C, and a 50 system, unless otherwise noted. Measured on probe matrix board using ground signal ground (GSG) probes close to the RF pins (ATTIN and ATTOUT). See the Applications Information section for details on evaluation and probe matrix boards. Figure 13. Input Return Loss vs. Frequency (Major States Only) Without Impedance Match Rev. B | Page 8 of 19 ADRF5720 0 -5 -5 -10 -10 OUTPUT RETURN LOSS (dB) 0 -15 -20 -25 -30 -35 -40 STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB -50 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) -20 -25 -30 -35 -40 -50 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) 0.5 0.5 0.3 0.3 0.1 0.1 -0.1 -0.1 STEP ERROR (dB) -0.3 -0.5 -0.7 -0.3 -0.5 -0.7 -0.9 0.5 30 35 40 45 -0.5 -1.0 Figure 16. Step Error vs. Attenuation State over Frequency with Impedance Match Rev. B | Page 9 of 19 ATTENUATION STATE (dB) Figure 19. Step Error vs. Attenuation State over Frequency Without Impedance Match 15959-019 30.0 31.5 30GHz 35GHz 40GHz 45GHz 5GHz 10GHz 15GHz 20GHz 25GHz 28.0 -2.0 15959-016 30.0 31.5 28.0 26.0 24.0 22.0 20.0 18.0 16.0 ATTENUATION STATE (dB) 25 0 -1.5 14.0 12.0 8.0 30GHz 35GHz 40GHz 45GHz 10.0 6.0 0 2.0 4.0 5GHz 10GHz 15GHz 20GHz 25GHz -1.5 20 26.0 STEP ERROR (dB) 0.5 -1.0 15 Figure 18. Step Error vs. Frequency (Major States Only) Without Impedance Match 1.0 -0.5 10 FREQUENCY (GHz) 1.0 0 5 24.0 Figure 15. Step Error vs. Frequency (Major States Only) with Impedance Match 0 22.0 FREQUENCY (GHz) -1.5 20.0 45 18.0 40 16.0 35 14.0 30 12.0 25 8.0 20 STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 10.0 15 6.0 10 0 5 4.0 -1.5 0 STATE 0dB STATE 1dB STATE 4dB STATE 16dB -1.3 15959-018 -1.1 STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB STATE 0dB STATE 1dB STATE 4dB STATE 16dB -1.3 15959-015 -1.1 2.0 STEP ERROR (dB) -15 Figure 17. Output Return Loss vs. Frequency (Major States Only) Without Impedance Match -0.9 STEP ERROR (dB) STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB -45 Figure 14. Output Return Loss vs. Frequency (Major States Only) with Impedance Match -2.0 STATE 0dB STATE 1dB STATE 4dB STATE 16dB 15959-017 STATE 0dB STATE 1dB STATE 4dB STATE 16dB -45 15959-014 OUTPUT RETURN LOSS (dB) Data Sheet ADRF5720 3.0 Data Sheet STATE 0dB STATE 1dB STATE 4dB STATE 16dB 2.5 3.0 STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 2.5 1.0 0.5 1.5 1.0 0.5 0 0 -0.5 -0.5 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) Figure 20. State Error vs. Frequency (Major States Only) with Impedance Match 3.0 5GHz 10GHz 15GHz 20GHz 25GHz 2.5 -1.0 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) 15959-023 STATE ERROR (dB) 1.5 -1.0 Figure 23. State Error vs. Frequency (Major States Only) Without Impedance Match 3.0 30GHz 35GHz 40GHz 45GHz 30GHz 35GHz 40GHz 45GHz 5GHz 10GHz 15GHz 20GHz 25GHz 2.5 2.0 110 STATE 0dB STATE 1dB STATE 4dB STATE 16dB 100 90 RELATIVE PHASE (Degrees) 90 80 70 60 50 40 30 20 31.5 15959-024 30.0 28.0 26.0 24.0 22.0 20.0 18.0 16.0 14.0 Figure 24. State Error vs. Attenuation State over Frequency Without Impedance Match STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB STATE 0dB STATE 1dB STATE 4dB STATE 16dB 100 12.0 ATTENUATION STATE (dB) Figure 21. State Error vs. Attenuation State over Frequency with Impedance Match 110 10.0 31.5 ATTENUATION STATE (dB) 15959-021 30.0 28.0 26.0 24.0 22.0 20.0 18.0 16.0 14.0 10.0 12.0 -1.0 8.0 -0.5 -1.0 6.0 -0.5 4.0 0 0 0 8.0 0.5 6.0 0.5 1.0 4.0 1.0 1.5 0 1.5 2.0 STATE ERROR (dB) 2.0 2.0 10 STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 80 70 60 50 40 30 20 10 0 -10 -10 0 5 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 15959-022 0 Figure 22. Relative Phase vs. Frequency (Major States Only) with Impedance Match Rev. B | Page 10 of 19 0 5 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 15959-025 STATE ERROR (dB) STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 2.0 15959-020 STATE ERROR (dB) 2.0 RELATIVE PHASE (Degrees) STATE 0dB STATE 1dB STATE 4dB STATE 16dB Figure 25. Relative Phase vs. Frequency (Major States Only) Without Impedance Match Data Sheet 120 ADRF5720 5GHz 20GHz 35GHz 10GHz 25GHz 40GHz 120 15GHz 30GHz 45GHz 10GHz 25GHz 40GHz 15GHz 30GHz 45GHz 100 30.0 31.5 28.0 26.0 24.0 22.0 20.0 18.0 16.0 14.0 12.0 8.0 ATTENUATION STATE (dB) Figure 27. Relative Phase vs. Attenuation State over Frequency Without Impedance Match Figure 26. Relative Phase vs. Attenuation State over Frequency with Impedance Match Rev. B | Page 11 of 19 15959-027 ATTENUATION STATE (dB) 15959-026 30.0 31.5 28.0 26.0 24.0 22.0 20.0 18.0 16.0 14.0 12.0 8.0 10.0 6.0 0 4.0 0 0 20 2.0 20 10.0 40 6.0 40 60 4.0 60 80 0 80 2.0 RELATIVE PHASE (Degrees) 100 RELATIVE PHASE (Degrees) 5GHz 20GHz 35GHz ADRF5720 Data Sheet 35 30 30 25 25 20 15 10 STATE 0dB STATE 1dB STATE 4dB STATE 16dB 5 0 0 5 10 15 20 25 STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 30 35 40 FREQUENCY (GHz) 15 10 STATE 0dB STATE 1dB STATE 4dB STATE 16dB 5 Figure 28. Input P0.1dB vs. Frequency (Major States Only) 0 10k 100k 1M 10M STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 100M 1G FREQUENCY (Hz) Figure 30. Input P0.1dB vs. Frequency (Major States Only), Low Frequency Detail 80 70 70 60 60 INPUT IP3 (dBm) 80 50 40 30 20 50 40 30 20 10 0 0 5 10 15 20 25 STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 30 35 FREQUENCY (GHz) Figure 29. Input IP3 vs. Frequency (Major States Only) 40 STATE 0dB STATE 1dB STATE 4dB STATE 16dB 10 0 10k 100k 1M 10M FREQUENCY (Hz) STATE 0.5dB STATE 2dB STATE 8dB STATE 31.5dB 100M 1G 15959-031 STATE 0dB STATE 1dB STATE 4dB STATE 16dB 15959-029 INPUT IP3 (dBm) 20 15959-030 INPUT P0.1dB (dBm) 35 15959-028 INPUT P0.1dB (dBm) INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT Figure 31. Input IP3 vs. Frequency (Major States Only), Low Frequency Detail Rev. B | Page 12 of 19 Data Sheet ADRF5720 THEORY OF OPERATION 4. The ADRF5720 incorporates a 6-bit fixed attenuator array that offers an attenuation range of 31.5 dB in 0.5 dB steps. An integrated driver provides both serial and parallel mode control of the attenuator array (see Figure 32). The power-down sequence is the reverse order of the power-up sequence. Power-Up State Note that when referring to a single function of a multifunction pin in this section, only the portion of the pin name that is relevant is mentioned. For full pin names of the multifunction pins, refer to the Pin Configuration and Function Descriptions section. The ADRF5720 has internal power-on reset circuity. This circuity sets the attenuator to the maximum attenuation state (31.5 dB) when the VDD and VSS voltages are applied and LE is set to low. RF INPUT AND OUTPUT POWER SEQUENCE Both RF ports (ATTIN and ATTOUT) are dc-coupled to 0 V. No dc blocking is required at the RF ports when the RF line potential is equal to 0 V. Bypassing capacitors are recommended on the positive supply voltage line (VDD) and negative supply line (VSS) to filter high frequency noise. The RF ports are internally matched to 50 . Therefore, external matching components are not required. For wideband applications, use impedance matching to improve insertion loss, return loss, and attenuation accuracy performance at high frequencies. See the Impedance Matching section. The power-up sequence is as follows: 1. 2. 3. Apply an RF input signal to ATTIN or ATTOUT. Connect GND. Power up the VDD and VSS voltages. Power up VSS after VDD to avoid current transients on VDD during ramp-up. Power up the digital control inputs. The order of the digital control inputs is not important. However, powering the digital control inputs before the VDD voltage supply may inadvertently forward bias and damage the internal ESD structures. To avoid this damage, use a series 1 k resistor to limit the current flowing in to the control pin. Use pullup or pull-down resistors if the controller output is in a high impedance state after the VDD voltage is powered up and the control pins are not driven to a valid logic state. The ADRF5720 supports bidirectional operation at a lower power level. The power handling of the ATTIN and ATTOUT ports are different. Therefore, the bidirectional power handling is defined by the ATTOUT port. Refer to the RF input power specifications in Table 1. Table 6. Truth Table D5 Low Low Low Low Low Low High High D1 Low Low High Low Low Low Low High D0 Low High Low Low Low Low Low High Attenuation State (dB) 0 (reference) 0.5 1.0 2.0 4.0 8.0 16.0 31.5 Any combination of the control voltage input states shown in Table 6 provides an attenuation equal to the sum of the bits selected. D0 SERIN D1 D3 D4 D Q D Q D Q D Q D Q D2 D5 D Q D Q D Q SEROUT CLK PS PARALLEL OR SERIAL SELECT LE 6-BIT OR 8-BIT LATCH RF INPUT 0.5dB 1dB 2dB 4dB 8dB Figure 32. Simplified Circuit Diagram Rev. B | Page 13 of 19 16dB RF OUTPUT 15959-032 1 D4 Low Low Low Low Low High Low High Digital Control Input1 D3 D2 Low Low Low Low Low Low Low High High Low Low Low Low Low High High ADRF5720 Data Sheet In serial mode, the SERIN data is clocked most significant bit (MSB) first on the rising CLK edges into the shift register. Then, LE must be toggled high to latch the new attenuation state into the device. LE must be set to low to clock new SERIN data into the shift register as CLK is masked to prevent the attenuator value from changing if LE is kept high. See Figure 33 in conjunction with Table 2 and Table 6. SERIAL OR PARALLEL MODE SELECTION The ADRF5720 can be controlled in either serial or parallel mode by setting the PS pin to high or low, respectively (see Table 7). Table 7. Mode Selection PS Low High Control Mode Parallel Serial Using SEROUT The ADRF5720 also features a serial data output, SEROUT. SEROUT outputs the serial input data at the 8th clock cycle, and can control a cascaded attenuator using a single SPI bus. Figure 34 shows the serial out timing diagram. SERIAL MODE INTERFACE The ADRF5720 supports a 4-wire SPI: serial data input (SERIN), clock (CLK), serial data output (SEROUT), and latch enable (LE). The serial control interface is activated when PS is set to high. When using the attenuator in a daisy-chain operation, 8-bit SERIN data must be used due to the 8 clock cycle delay between SERIN and SEROUT. The SEROUT pin does not support high impedance mode. A tristate buffer can be used to interface a shared bus. The ADRF5720 attenuation states can be controlled using 6-bit or 8-bit SERIN data. If an 8-bit word is used to control the state of the attenuator, the first two bits, D7 and D6, are don't care bits. It does not matter if these two bits are held low or high, or if they are omitted altogether. Only Bits[D0:D5] set the state of the attenuator. PS SERIN [FIRST IN] OPTIONAL OPTIONAL X X D7 MSB D6 tCS D5 [LAST IN] LSB tCH D4 D3 D2 D1 D0 D[7:0] NEXT WORD X tLN X tCKN tLEW tSCK 15959-033 CLK tLES LE Figure 33. Serial Control Timing Diagram PS SERIN X X D5 1 D4 2 D3 D2 D1 D0 3 4 5 6 X 7 8 9 10 11 12 13 14 CLK D5 SEROUT tCO Figure 34. Serial Output Timing Diagram Rev. B | Page 14 of 19 D4 D3 D2 D1 D0 X 15959-035 LE Data Sheet ADRF5720 PARALLEL MODE INTERFACE Latched Parallel Mode The ADRF5720 has six digital control inputs, D0 (LSB) to D5 (MSB), to select the desired attenuation state in parallel mode, as shown in Table 6. The parallel control interface is activated when PS is set to low. To enable latched parallel mode, the LE pin must be kept low when changing the control voltage inputs (D0 to D5) to set the attenuation state. When the desired state is set, LE must be toggled high to transfer the 6-bit data to the bypass switches of the attenuator array, and then toggled low to latch the change into the device until the next desired attenuation change (see Figure 35 in conjunction with Table 2). Direct Parallel Mode To enable direct parallel mode, the LE pin must be kept high. The attenuation state is changed by the control voltage inputs (D0 to D5) directly. This mode is ideal for manual control of the attenuator. PS X tPS D5 TO D0 tPH X X tLEW LE 15959-036 There are two modes of parallel operation: direct parallel and latched parallel. Figure 35. Latched Parallel Mode Timing Diagram Rev. B | Page 15 of 19 ADRF5720 Data Sheet APPLICATIONS INFORMATION EVALUATION BOARD 0 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) T = 2.2mil H = 12mil -3 -4 -5 -6 -7 -8 0.5oz Cu (0.7mil) THRU LOSS EMBEDDED INSERTION LOSS DE-EMBEDDED INSERTION LOSS -9 -10 0 5 10 15 20 25 30 35 FREQUENCY (GHz) 1.5oz Cu (2.2mil) 40 45 Figure 37. Insertion Loss vs. Frequency 0.5oz Cu (0.7mil) 15959-037 TOTAL THICKNESS -62mil RO4003 -2 15959-039 W = 16mil G = 6mil -1 INSERTION LOSS (dB) The ADRF5720-EVALZ is a 4-layer evaluation board. The top and bottom copper layer are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil) and are separated by dielectric materials. The stackup for this evaluation board is shown in Figure 36. Figure 38 shows the actual ADRF5720 evaluation board with component placement. All RF and dc traces are routed on the top copper layer, whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. The top dielectric material is 12 mil Rogers RO4003, offering optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges. The RF transmission lines are designed using a coplanar waveguide (CPWG) model, with a trace width of 16 mil and ground clearance of 6 mil to have a characteristic impedance of 50 . For optimal RF and thermal grounding, as many through vias as possible are arranged around transmission lines and under the exposed pad of the package. The ADRF5720-EVALZ does not have high frequency impedance matching implemented on the RF transmission lines. For more details on the impedance matched circuit, refer to the Impedance Matching portion of the Probe Matrix Board section. Thru calibration can be used to calibrate out the board loss effects from the ADRF5720-EVALZ evaluation board measurements to determine the device performance at the pins of the IC. Figure 37 shows the typical board loss for the ADRF5720-EVALZ evaluation board at room temperature, the embedded insertion loss, and the de-embedded insertion loss for the ADRF5720. 15959-038 Figure 36. Evaluation Board Stackup Figure 38. Evaluation Board, Top View Two power supply ports are connected to the VDD and VSS test points, TP1 and TP2, and the ground reference is connected to the GND test point, TP4. On the supply traces, VDD and VSS, a 100 pF bypass capacitor is used to filter high frequency noise. Additionally, unpopulated components positions are available for applying extra bypass capacitors. All the digital control pins are connected through digital signal traces to the 2 x 9-pin header, P1. There are provisions for a resistor capacitor (RC) filter that helps eliminate dc-coupled noise. The ADRF5720 was evaluated without an external RC filter, the series resistors are 0 , and the shunt capacitors are unpopulated on the evaluation board. The RF input and output ports (ATTIN and ATTOUT) are connected through 50 transmission lines to the 2.4 mm RF launchers, J1 and J2, respectively. These high frequency RF launchers are connected by contact and are not soldered onto the board. A thru calibration line connects the unpopulated J3 and J4 launchers. This transmission line is used to estimate the loss of the PCB over the environmental conditions being evaluated. The schematic of the ADRF5720-EVALZ evaluation board is shown in Figure 39. Rev. B | Page 16 of 19 Data Sheet ADRF5720 D3_SEROUT R5 R6 D2 D4_SERIN 0 R4 0 R7 D1 0 0 R8 D0 D5_CLK R3 P1 1 PS 3 LE D5_CLK 5 D4_SERIN 7 D3_SEROUT 9 D2 11 13 D1 15 D0 17 0 VDD TP1 R2 LE 0 R1 PS 1 2 3 4 5 6 EPAD LE PS GND GND ATTIN GND C1 100pF VDD VSS GND ADRF5720 GND ATTOUT GND 18 17 16 15 14 13 VSS TP2 87759-1850 AGND TP4 C2 100pF GND GND GND GND GND GND 0 25 D5/CLK D4/SERIN D3/SEROUT D2 D1 D0 24 23 22 21 20 19 0 7 8 9 10 11 12 J1 J2 ATTOUT J3 DNI THRU CAL J4 DNI 15959-040 ATTIN 2 6 4 8 10 12 14 16 18 Figure 39. Evaluation Board Schematic Table 8. Evaluation Board Components Component C1, C2 J1 to J4 P1 R1 to R8 TP1, TP2, TP4 U1 Default Value 100 pF Not applicable Not applicable 0 Not applicable ADRF5720 Description Capacitors, C0402 package 2.4 mm end launch connectors (Southwest Microwave: 1492-04A-5) 2 x 9-pin header Resistors, 0402 package Through hole mount test points ADRF5720 digital attenuator, Analog Devices, Inc. Rev. B | Page 17 of 19 ADRF5720 Data Sheet PROBE MATRIX BOARD The probe matrix board is a 4-layer board. Similar to the evaluation board, the probe matrix board also uses a 12 mil Rogers RO4003 dielectric. The top and bottom copper layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil). The RF transmission lines are designed using a CPWG model with a width of 16 mil and ground spacing of 6 mil to have a characteristic impedance of 50 . Figure 40 and Figure 41 show the cross sectional view and the top view of the board, respectively. Measurements are made using GSG probes at close proximity to the RF pins (ATTIN and ATTOUT). Unlike the evaluation board, probing reduces reflections caused by mismatch arising from connectors, cables, and board layout, resulting in a more accurate measurement of the device performance. W = 16mil 1.5oz Cu (2.2mil) G = 6mil 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) Impedance Matching Impedance matching at the RF pins (ATTIN and ATTOUT) can improve insertion loss, return loss, and attenuation accuracy at high frequencies. Figure 42 and Figure 43 show the difference in the transmission lines at the ATTIN and ATTOUT pins. The dimensions of the 50 lines are 16 mil trace width and 6 mil gap. To implement this impedance matched circuit, the pad length is extended by 5 mil (from 17 mil to 22 mil). The calibration reference kit does not include the 5 mil matching line and, therefore, the measured insertion loss includes the losses of the matching circuit. H = 12mil 0.5oz Cu (0.7mil) 6mil 17mil 1.5oz Cu (2.2mil) 10mil 6mil Figure 40. Probe Matrix Board Stackup, Cross Sectional View 15959-043 15959-041 16mil 0.5oz Cu (0.7mil) Figure 42. Without Impedance Match 10mil 15959-044 16mil 22mil Figure 43. With Impedance Match 15959-042 TOTAL THICKNESS -62mil RO4003 T = 2.2mil The probe matrix board includes a thru reflect line (TRL) calibration kit, allowing board loss de-embedding. The actual board duplicates the same layout in matrix form to assemble multiple devices at one time. All S-parameters were measured on this board. Figure 41. Probe Matrix Board Top View Rev. B | Page 18 of 19 Data Sheet ADRF5720 OUTLINE DIMENSIONS 0.30 0.25 0.20 0.35 0.30 0.25 CHAMFERED PIN 1 (0.2 x 45) 24 19 18 1 2.50 REF SQ 2.50 2.40 SQ 2.30 EXPOSED PAD 13 0.50 BSC TOP VIEW 6 12 7 BOTTOM VIEW 0.375 BSC 0.85 0.75 0.65 SIDE VIEW 0.530 REF PKG-005303 0.240 0.220 0.200 0.125 BSC FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 09-29-2016-B PIN 1 CORNER AREA 4.10 4.00 3.90 Figure 44. 24-Terminal Land Grid Array [LGA] 4 mm x 4 mm Body and 0.75 mm Package Height (CC-24-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF5720BCCZN ADRF5720BCCZN-R7 ADRF5720-EVALZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 24-Terminal Land Grid Array [LGA] 24-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. (c)2018-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15959-11/20(B) Rev. B | Page 19 of 19 Package Option CC-24-5 CC-24-5