PIC16C5X EPROM/ROM-Based 8-Bit CMOS Microcontroller Series Devices Included in this Data Sheet: Peripheral Features: * * * * * * * * * * 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler * Power-on Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable Code Protection * Power saving SLEEP mode * Selectable oscillator options: - RC: Low-cost RC oscillator - XT: Standard crystal/resonator - HS: High-speed crystal/resonator - LP: Power saving, low-frequency crystal PIC16C54 PIC16CR54 PIC16C55 PIC16C56 PIC16CR56 PIC16C57 PIC16CR57 PIC16C58 PIC16CR58 Note: 16C5X refers to all revisions of the part (i.e., 16C54 refers to 16C54, 16C54A, and 16C54C), unless specifically called out otherwise. High-Performance RISC CPU: CMOS Technology: * Only 33 single word instructions to learn * All instructions are single cycle (200 ns) except for program branches which are two-cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * Low-power, high-speed CMOS EPROM/ROM technology * Fully static design * Wide-operating voltage and temperature range: - EPROM Commercial/Industrial 2.0V to 6.25V - ROM Commercial/Industrial 2.0V to 6.25V - EPROM Extended 2.5V to 6.0V - ROM Extended 2.5V to 6.0V * Low-power consumption - < 2 mA typical @ 5V, 4 MHz - 15 A typical @ 3V, 32 kHz - < 0.6 A typical standby current (with WDT disabled) @ 3V, 0C to 70C Device Pins I/O EPROM/ RAM ROM PIC16C54 18 12 512 25 PIC16C54A 18 12 512 25 PIC16C54C 18 12 512 25 PIC16CR54A 18 12 512 25 PIC16CR54C 18 12 512 25 PIC16C55 28 20 512 24 PIC16C55A 28 20 512 24 PIC16C56 18 12 1K 25 PIC16C56A 18 12 1K 25 PIC16CR56A 18 12 1K 25 PIC16C57 28 20 2K 72 PIC16C57C 28 20 2K 72 PIC16CR57C 28 20 2K 72 PIC16C58B 18 12 2K 73 PIC16CR58B 18 12 2K 73 * 12-bit wide instructions * 8-bit wide data path * Seven or eight special function hardware registers * Two-level deep hardware stack * Direct, indirect and relative addressing modes for data and instructions 2000 Microchip Technology Inc. Note: Preliminary In this document, figure and table titles refer to all varieties of the part number indicated, (i.e., The title "Figure 14-1: Load Conditions - PIC16C54A", also refers to PIC16LC54A and PIC16LV54A parts) unless specifically called out otherwise. DS30453C-page 1 PIC16C5X Pin Diagrams PDIP, SOIC, Windowed CERDIP 18 17 16 15 14 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD 13 12 RB7 RB6 RB5 RB4 11 10 *1 28 MCLR/VPP VDD 2 27 OSC1/CLKIN N/C 3 26 VSS 4 25 OSC2/CLKOUT RC7 24 RC6 23 21 RC5 RC4 RC3 N/C 5 RA0 6 RA1 7 RA2 8 RA3 9 20 RC2 RB0 10 19 RB1 11 18 RC1 RC0 RB2 12 17 RB7 RB3 13 16 RB6 RB4 14 15 RB5 22 SSOP SSOP DS30453C-page 2 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4 Preliminary VSS T0CKI VDD VDD RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 VSS *1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16C55 PIC16C57 PIC16CR57 *1 2 3 4 5 6 7 8 9 10 PIC16C54 PIC16CR54 PIC16C56 PIC16CR56 PIC16C58 PIC16CR58 RA2 RA3 T0CKI MCLR/VPP VSS VSS RB0 RB1 RB2 RB3 T0CKI PIC16C55 PIC16C57 PIC16CR57 PIC16C54 PIC16CR54 PIC16C56 PIC16CR56 PIC16C58 PIC16CR58 *1 2 3 4 5 6 7 8 9 RA2 RA3 T0CKI MCLR/VPP VSS RB0 RB1 RB2 RB3 PDIP, SOIC, Windowed CERDIP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5 2000 Microchip Technology Inc. PIC16C5X Device Differences Device Voltage Range Oscillator Selection (Program) Oscillator Process Technology (Microns) ROM Equivalent MCLR Filter PIC16C54 2.5-6.25 Factory See Note 1 1.2 PIC16CR54A No PIC16C54A 2.0-6.25 User See Note 1 0.9 -- No PIC16C54C 2.5-5.5 User See Note 1 0.7 PIC16CR54C Yes PIC16C55 2.5-6.25 Factory See Note 1 1.7 -- No PIC16C55A 2.5-5.5 User See Note 1 0.7 -- Yes PIC16C56 2.5-6.25 Factory See Note 1 1.7 -- No PIC16C56A 2.5-5.5 User See Note 1 0.7 PIC16CR56A Yes PIC16C57 2.5-6.25 Factory See Note 1 1.2 -- No PIC16C57C 2.5-5.5 User See Note 1 0.7 PIC16CR57C Yes PIC16C58B 2.5-5.5 User See Note 1 0.7 PIC16CR58B Yes PIC16CR54A 2.5-6.25 Factory See Note 1 1.2 N/A Yes PIC16CR54C 2.5-5.5 Factory See Note 1 0.7 N/A Yes PIC16CR56A 2.5-5.5 Factory See Note 1 0.7 N/A Yes PIC16CR57C 2.5-5.5 Factory See Note 1 0.7 N/A Yes PIC16CR58B 2.5-5.5 Factory See Note 1 0.7 N/A Yes Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties, please refer to Section 2.0. 2000 Microchip Technology Inc. Preliminary DS30453C-page 3 PIC16C5X Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC16C5X Device Varieties ......................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................. 9 4.0 Memory Organization ................................................................................................................................................................. 15 5.0 I/O Ports ..................................................................................................................................................................................... 25 6.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 27 7.0 Special Features of the CPU ...................................................................................................................................................... 31 8.0 Instruction Set Summary ............................................................................................................................................................ 43 9.0 Development Support................................................................................................................................................................. 55 10.0 Electrical Characteristics - PIC16C54/55/56/57 ......................................................................................................................... 61 11.0 DC and AC Characteristics - PIC16C54/55/56/57...................................................................................................................... 73 12.0 Electrical Characteristics - PIC16CR54A ................................................................................................................................... 81 13.0 Electrical Characteristics - PIC16C54A ...................................................................................................................................... 93 14.0 DC and AC Characteristics - PIC16C54A ................................................................................................................................ 105 15.0 Electrical Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B......................................... 115 16.0 DC and AC Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ..................................... 127 17.0 Packaging Information.............................................................................................................................................................. 137 Appendix A: Compatibility .................................................................................................................................................................. 149 Index .................................................................................................................................................................................................. 151 On-Line Support................................................................................................................................................................................. 153 Reader Response .............................................................................................................................................................................. 154 PIC16C5X Product Identification System .......................................................................................................................................... 155 PIC16C54/55/56/57 Product Identification System ........................................................................................................................... 156 To Our Valued Customers Most Current Data Sheet To automatically obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet. * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. DS30453C-page 4 Preliminary 2000 Microchip Technology Inc. PIC16C5X 1.0 GENERAL DESCRIPTION 1.1 The PIC16C5X from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (200 ns) except for program branches which take two cycles. The PIC16C5X delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C5X products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. Power saving SLEEP mode, Watchdog Timer and Code Protection features improve system cost, power and reliability. Applications The PIC16C5X series fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. The EPROM technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC16C5X series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of "glue" logic in larger systems, co-processor applications). The UV erasable CERDIP packaged versions are ideal for code development, while the cost-effective One Time Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP microcontrollers, while benefiting from the OTP's flexibility. The PIC16C5X products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM PC and compatible machines. 2000 Microchip Technology Inc. Preliminary DS30453C-page 5 PIC16C5X TABLE 1-1: PIC16C5X FAMILY OF DEVICES PIC16C54 Clock Memory Peripherals Features PIC16CR54 PIC16C55 PIC16C56 PIC16CR56 Maximum Frequency of Operation (MHz) 20 20 20 20 20 EPROM Program Memory (x12 words) 512 -- 512 1K -- ROM Program Memory (x12 words) -- 512 -- -- 1K RAM Data Memory (bytes) 25 25 24 25 25 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 20 12 12 Number of Instructions 33 33 33 33 33 Packages 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC; 28-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP All PICmicro(R) Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability. PIC16C57 PIC16CR57 PIC16C58 PIC16CR58 Maximum Frequency of Operation (MHz) 20 20 20 20 EPROM Program Memory (x12 words) 2K -- 2K -- Memory ROM Program Memory (x12 words) -- 2K -- 2K RAM Data Memory (bytes) 72 72 73 73 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 I/O Pins 20 20 12 12 Clock Features Number of Instructions 33 33 33 33 Packages 28-pin DIP, SOIC; 28-pin SSOP 28-pin DIP, SOIC; 28-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP All PICmicro(R) Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability. DS30453C-page 6 Preliminary 2000 Microchip Technology Inc. PIC16C5X 2.0 PIC16C5X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16C5X Product Identification System at the back of this data sheet to specify the correct part number. For the PIC16C5X family of devices, there are four device types, as indicated in the device number: 1. 2. 3. 4. 2.1 C, as in PIC16C54C. These devices have EPROM program memory and operate over the standard voltage range. LC, as in PIC16LC54A. These devices have EPROM program memory and operate over an extended voltage range. CR, as in PIC16CR54A. These devices have ROM program memory and operate over the standard voltage range. LCR, as in PIC16LCR54A. These devices have ROM program memory and operate over an extended voltage range. UV Erasable Devices (EPROM) The UV erasable versions, offered in CERDIP packages, are optimal for prototype development and pilot programs. UV erasable devices can be programmed for any of the four oscillator configurations. Microchip's PICSTART and PRO MATE programmers both support programming of the PIC16C5X. Third party programmers also are available. Refer to the Third Party Guide for a list of sources. 2.2 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround-Production (SQTPSM ) Devices Microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number. 2.5 Read Only Memory (ROM) Devices Microchip offers masked ROM versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products. One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers expecting frequent code changes and updates. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must be programmed. 2000 Microchip Technology Inc. Preliminary DS30453C-page 7 PIC16C5X NOTES: DS30453C-page 8 Preliminary 2000 Microchip Technology Inc. PIC16C5X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C5X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C5X uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200ns @ 20MHz) except for program branches. The PIC16C54/CR54 and PIC16C55 address 512 x 12 of program memory, the PIC16C56/CR56 address 1K x 12 of program memory, and the PIC16C57/CR57 and PIC16C58/CR58 address 2K x 12 of program memory. All program memory is internal. The PIC16C5X device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1. The PIC16C5X can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC16C5X has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C5X simple yet efficient. In addition, the learning curve is reduced significantly. 2000 Microchip Technology Inc. Preliminary DS30453C-page 9 PIC16C5X FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM 9-11 9-11 EPROM/ROM 512 X 12 TO 2048 X 12 T0CKI PIN STACK 1 STACK 2 CONFIGURATION WORD "DISABLE" "OSC SELECT" PC WATCHDOG TIMER 12 "CODE PROTECT" 2 OSCILLATOR/ TIMING & CONTROL INSTRUCTION REGISTER WDT TIME OUT 9 12 OSC1 OSC2 MCLR CLKOUT WDT/TMR0 PRESCALER 8 "SLEEP" INSTRUCTION DECODER 6 "OPTION" OPTION REG. DIRECT ADDRESS DIRECT RAM ADDRESS FROM W 5 5-7 LITERALS 8 STATUS TMR0 GENERAL PURPOSE REGISTER FILE (SRAM) 24, 25, 72 or 73 Bytes FSR 8 W DATA BUS ALU 8 FROM W 4 4 "TRIS 5" 8 "TRIS 6" TRISA PORTA 4 RA<3:0> DS30453C-page 10 FROM W Preliminary TRISB FROM W 8 PORTB 8 RB<7:0> 8 "TRIS 7" TRISC 8 PORTC 8 RC<7:0> (28-Pin Devices Only) 2000 Microchip Technology Inc. PIC16C5X TABLE 3-1: Name RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 T0CKI PINOUT DESCRIPTION - PIC16C54s, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, PIC16CR58 DIP, SOIC SSOP I/O/P Input No. No. Type Levels 17 18 1 2 6 7 8 9 10 11 12 13 3 19 20 1 2 7 8 9 10 11 12 13 14 3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL ST Description Bi-directional I/O port Bi-directional I/O port Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. 4 4 I ST Master clear (RESET) input/programming voltage input. This MCLR/VPP pin is an active low RESET to the device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of programming mode. OSC1/CLKIN 16 18 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 17 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. VDD 14 15,16 P -- Positive supply for logic and I/O pins. VSS 5 5,6 P -- Ground reference for logic and I/O pins. Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input 2000 Microchip Technology Inc. Preliminary DS30453C-page 11 PIC16C5X TABLE 3-2: Name RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 T0CKI PINOUT DESCRIPTION - PIC16C55, PIC16C57, PIC16CR57 DIP, SOIC SSOP I/O/P Input No. No. Type Levels 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL ST Description Bi-directional I/O port Bi-directional I/O port Bi-directional I/O port Clock input to Timer0. Must be tied to VSS or VDD if not in use to reduce current consumption. 28 28 I ST Master clear (RESET) input. This pin is an active low RESET MCLR to the device. OSC1/CLKIN 27 27 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 26 26 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. 2 3,4 P -- Positive supply for logic and I/O pins. VDD VSS 4 1,14 P -- Ground reference for logic and I/O pins. N/C 3,5 -- -- -- Unused, do not connect. Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input DS30453C-page 12 Preliminary 2000 Microchip Technology Inc. PIC16C5X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 3-2 and Example 3-1. Instruction Flow/Pipelining An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase clock Q3 Q4 PC PC OSC2/CLKOUT (RC mode) EXAMPLE 3-1: PC+1 Fetch INST (PC) Execute INST (PC-1) PC+2 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW 1. MOVLW 55H 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed. 2000 Microchip Technology Inc. Preliminary DS30453C-page 13 PIC16C5X NOTES: DS30453C-page 14 Preliminary 2000 Microchip Technology Inc. PIC16C5X 4.0 MEMORY ORGANIZATION FIGURE 4-2: PIC16C5X memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS Register bits. For devices with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR). PC<9:0> Stack Level 1 Stack Level 2 000h Program Memory Organization The PIC16C54, PIC16CR54 and PIC16C55 have a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 4-1). The PIC16C56 and PIC16CR56 have a 10-bit Program Counter (PC) capable of addressing a 1K x 12 program memory space (Figure 4-2). The PIC16CR57, PIC16C58 and PIC16CR58 have an 11-bit Program Counter capable of addressing a 2K x 12 program memory space (Figure 4-3). Accessing a location above the physically implemented address will cause a wraparound. FIGURE 4-3: A NOP at the RESET vector location will cause a restart at location 000h. The RESET vector for the PIC16C54, PIC16CR54 and PIC16C55 is at 1FFh. The RESET vector for the PIC16C56 and PIC16CR56 is at 3FFh. The RESET vector for the PIC16C57, PIC16CR57, PIC16C58, and PIC16CR58 is at 7FFh. FIGURE 4-1: User Memory Space 2000 Microchip Technology Inc. RESET Vector 3FFh PIC16C57/CR57/C58/ CR58 PROGRAM MEMORY MAP AND STACK 11 Stack Level 1 Stack Level 2 000h User Memory Space 000h 1FFh 2FFh 300h 0FFh 100h 1FFh 200h Stack Level 1 Stack Level 2 RESET Vector On-chip Program Memory (Page 1) On-chip Program Memory (Page 0) 9 0FFh 100h 0FFh 100h 1FFh 200h CALL, RETLW PC<8:0> On-chip Program Memory On-chip Program Memory (Page 0) PC<10:0> PIC16C54/CR54/C55 PROGRAM MEMORY MAP AND STACK CALL, RETLW 10 CALL, RETLW User Memory Space 4.1 PIC16C56/CR56 PROGRAM MEMORY MAP AND STACK On-chip Program Memory (Page 1) 2FFh 300h 3FFh 400h On-chip Program Memory (Page 2) 4FFh 500h 5FFh 600h Preliminary On-chip Program Memory (Page 3) 6FFh 700h RESET Vector 7FFh DS30453C-page 15 PIC16C5X 4.2 Data Memory Organization FIGURE 4-4: Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers and General Purpose Registers. PIC16C54, PIC16CR54, PIC16C55, PIC16C56, PIC16CR56 REGISTER FILE MAP File Address The Special Function Registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports) and the File Select Register (FSR). In addition, Special Purpose Registers are used to control the I/O port configuration and prescaler options. 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR The General Purpose Registers are used for data and control information under command of the instructions. 05h PORTA 06h PORTB For the PIC16C54, PIC16CR54, PIC16C56 and PIC16CR56, the register file is composed of 7 Special Function Registers and 25 General Purpose Registers (Figure 4-4). 07h PORTC(2) 08h 0Fh 10h For the PIC16C55, the register file is composed of 8 Special Function Registers and 24 General Purpose Registers. For the PIC16C57 and PIC16CR57, the register file is composed of 8 Special Function Registers, 24 General Purpose Registers and up to 48 additional General Purpose Registers that may be addressed using a banking scheme (Figure 4-5). For the PIC16C58 and PIC16CR58, the register file is composed of 7 Special Function Registers, 25 General Purpose Registers and up to 48 additional General Purpose Registers that may be addressed using a banking scheme (Figure 4-6). 4.2.1 General Purpose Registers 1Fh Note 1: Not a physical register. See Section 4.7. 2: PIC16C55 only, in all other devices this is implemented as a a general purpose register. GENERAL PURPOSE REGISTER FILE The register file is accessed either directly or indirectly through the File Select Register (FSR). The FSR Register is described in Section 4.7. DS30453C-page 16 Preliminary 2000 Microchip Technology Inc. PIC16C5X FIGURE 4-5: PIC16C57/CR57 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 20h 60h Addresses map back to addresses in Bank 0. 07h PORTC 08h General Purpose Registers 0Fh 40h 10h 2Fh 4Fh 6Fh 30h 50h 70h General Purpose Registers 1Fh General Purpose Registers 3Fh Bank 0 General Purpose Registers 5Fh Bank 1 General Purpose Registers 7Fh Bank 2 Bank 3 Note 1: Not a physical register. See Section 4.7. FIGURE 4-6: PIC16C58/CR58 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 01h TMR0 20h 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 40h 60h Addresses map back to addresses in Bank 0. 07h General Purpose Registers 2Fh 0Fh 10h 4Fh 30h General Purpose Registers 1Fh General Purpose Registers 3Fh Bank 0 6Fh 50h 70h General Purpose Registers 5Fh Bank 1 General Purpose Registers 7Fh Bank 2 Bank 3 Note 1: Not a physical register. See Section 4.7. DS30453C-page 17 Preliminary 2000 Microchip Technology Inc. PIC16C5X 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Registers can be classified into two sets. The Special Function Registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on MCLR and WDT Reset Value on Power-on Reset N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 --11 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 03h STATUS 0001 1xxx 000q quuu PA2 PA1 PA0 TO PD Z DC C 1uuu uuuu(3) 04h FSR 05h PORTA -- -- -- -- RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 06h 07h (2) Indirect data memory address pointer (3) 1xxx xxxx Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5 for an explanation of how to access these bits. 2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and PIC16CR58. 3: For the PIC16C54 and PIC16C55, the value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu. DS30453C-page 18 Preliminary 2000 Microchip Technology Inc. PIC16C5X 4.3 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS Register as 000u u1uu (where u = unchanged). This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bits for program memories larger than 512 words. It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS Register because these instructions do not affect the Z, DC or C bits from the STATUS Register. For other instructions which do affect STATUS Bits, see Section 8.0, Instruction Set Summary. The STATUS Register can be the destination for any instruction, as with any other register. If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different than intended. REGISTER 4-1: R/W-0 PA2 bit7 STATUS REGISTER (ADDRESS:03h) R/W-0 PA1 R/W-0 PA0 R-1 TO R-1 PD R/W-x Z R/W-x DC 6 5 4 3 2 1 R/W-x C bit0 R = Readable bit W = Writable bit - n = Value at POR reset bit 7: PA2: This bit unused at this time. Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5: PA<1:0>: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(PIC16C58/CR58) 00 = Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58 01 = Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58 10 = Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58 11 = Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58 Each page is 512 words. Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF 1 = A carry occurred 1 = A borrow did not occur 0 = A carry did not occur 0 = A borrow occurred DS30453C-page 19 Preliminary RRF or RLF Loaded with LSb or MSb, respectively 2000 Microchip Technology Inc. PIC16C5X 4.4 OPTION Register The OPTION Register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W Register will be transferred to the OPTION Register. A RESET sets the OPTION<5:0> bits. REGISTER 4-2: OPTION REGISTER U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1 -- -- T0CS T0SE PSA PS2 PS1 PS0 6 5 4 3 2 1 bit7 bit 7-6: Unimplemented. bit 5: T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: Timer0 source edge select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3: PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS<2:0>: Prescaler rate select bits Bit Value Timer0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 DS30453C-page 20 Preliminary bit0 W = Writable bit U = Unimplemented bit - n = Value at POR reset 2000 Microchip Technology Inc. PIC16C5X 4.5 Program Counter FIGURE 4-7: As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC. GOTO Instruction 8 For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure 4-7 and Figure 4-8). For the PIC16C56, PIC16CR56, PIC16C57, PIC16CR57, PIC16C58 and PIC16CR58, a page number must be supplied as well. Bit5 and bit6 of the STATUS Register provide page information to bit9 and bit10 of the PC (Figure 4-8 and Figure 4-9). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-7 and Figure 4-8). LOADING OF PC BRANCH INSTRUCTIONS PIC16C54, PIC16CR54, PIC16C55 Note: 0 PCL Instruction Word CALL or Modify PCL Instruction 8 7 0 PCL PC Instruction Word Reset to '0' FIGURE 4-8: Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5. For the PIC16C56, PIC16CR56, PIC16C57, PIC16CR57, PIC16C58 and PIC16CR58, a page number again must be supplied. Bit5 and bit6 of the STATUS Register provide page information to bit9 and bit10 of the PC (Figure 4-8 and Figure 4-9). 7 PC LOADING OF PC BRANCH INSTRUCTIONS PIC16C56/PIC16CR56 GOTO Instruction 10 9 8 7 0 PC PCL Instruction Word Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). 2 PA<1:0> 7 0 STATUS CALL or Modify PCL Instruction 10 9 8 7 0 PC PCL Instruction Word 2 Reset to `0' PA<1:0> 7 0 STATUS 2000 Microchip Technology Inc. Preliminary DS30453C-page 21 PIC16C5X FIGURE 4-9: LOADING OF PC BRANCH INSTRUCTIONS PIC16C57/PIC16CR57, AND PIC16C58/PIC16CR58 4.6 PIC16C5X devices have a 10-bit or 11-bit wide, two-level hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL's are executed, only the most recent two return addresses are stored. GOTO Instruction 10 9 8 7 0 PC PCL A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW's are executed, the stack will be filled with the address previously stored in level 2. Note that the W Register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Instruction Word 2 PA<1:0> 7 0 STATUS CALL or Modify PCL Instruction 10 9 8 7 0 PC For the RETLW instruction, the PC is loaded with the Top of Stack (TOS) contents. All of the devices covered in this data sheet have a two-level stack. The stack has the same bit width as the device PC. PCL Instruction Word 2 4.7 Reset to `0' PA<1:0> 7 0 Indirect Data Addressing; INDF and FSR Registers The INDF Register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR Register (FSR is a pointer). This is indirect addressing. STATUS 4.5.1 Stack PAGING CONSIDERATIONS - PIC16C56/CR56, PIC16C57/CR57 AND PIC16C58/CR58 EXAMPLE 4-1: If the Program Counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. However, the page preselect bits in the STATUS Register will not be updated. Therefore, the next GOTO, CALL or modify PCL instruction will send the program to the page specified by the page preselect bits (PA0 or PA<1:0>). For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address 0xxh on page 0 (assuming that PA<1:0> are clear). INDIRECT ADDRESSING * * * * Register file 08 contains the value 10h Register file 09 contains the value 0Ah Load the value 08 into the FSR Register A read of the INDF Register will return the value of 10h * Increment the value of the FSR Register by one (FSR = 09h) * A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF Register indirectly results in a no-operation (although STATUS bits may be affected). To prevent this, the page preselect bits must be updated under program control. A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2. 4.5.2 EXAMPLE 4-2: EFFECTS OF RESET The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page (e.g., the RESET vector). The STATUS Register page preselect bits are cleared upon a RESET, which means that page 0 is pre-selected. NEXT Therefore, upon a RESET, a GOTO instruction at the RESET vector location will automatically cause the program to jump to page 0. CONTINUE DS30453C-page 22 Preliminary movlw movwf clrf incf btfsc goto : HOW TO CLEAR RAM USING INDIRECT ADDRESSING 0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF Register ;inc pointer ;all done? ;NO, clear next ;YES, continue 2000 Microchip Technology Inc. PIC16C5X The FSR is either a 5-bit (PIC16C54, PIC16CR54, PIC16C55), 6-bit (PIC16C56, PIC16CR56), or 7-bit (PIC16C57s, PIC16CR57, PIC16C58, PIC16CR58) wide register. It is used in conjunction with the INDF Register to indirectly address the data memory area. PIC16C54, PIC16CR54, PIC16C55: These do not use banking. FSR<6:5> bits are unimplemented and read as '1's. PIC16C57, PIC16CR57, PIC16C58, PIC16CR58: FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = bank 0, 01 = bank 1, 10 = bank 2, 11 = bank 3). The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. FIGURE 4-10: DIRECT/INDIRECT ADDRESSING Direct Addressing (FSR) 6 5 4 bank select location select Indirect Addressing (opcode) 0 6 5 4 bank 00 01 10 (FSR) 0 location select 11 00h Addresses map back to addresses in Bank 0. Data Memory(1) 0Fh 10h 1Fh Bank 0 Note 1: 3Fh 5Fh Bank 1 7Fh Bank 2 Bank 3 For register map detail see Section 4.2. 2000 Microchip Technology Inc. Preliminary DS30453C-page 23 PIC16C5X NOTES: DS30453C-page 24 Preliminary 2000 Microchip Technology Inc. PIC16C5X 5.0 I/O PORTS 5.5 As with any other register, the I/O Registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin's input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers (TRISA, TRISB, TRISC) are all set. 5.1 PORTA PORTA is a 4-bit I/O Register. Only the low order 4 bits are used (RA<3:0>). Bits 7-4 are unimplemented and read as '0's. 5.2 The equivalent circuit for an I/O port pin is shown in Figure 5-1. All ports may be used for both input and output operation. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output. FIGURE 5-1: Data Bus D PORTC WR Port PORTC is an 8-bit I/O Register for PIC16C55, PIC16C57 and PIC16CR57. PORTC is a General Purpose Register for PIC16C54, PIC16CR54, PIC16C56, PIC16C58 and PIC16CR58. 5.4 EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN PORTB PORTB is an 8-bit I/O Register (PORTB<7:0>). 5.3 I/O Interfacing W Reg TRIS Registers CK VDD Q P N D TRIS `f' I/O pin(1) Q TRIS Latch The Output Driver Control Registers are loaded with the contents of the W Register by executing the TRIS f instruction. A '1' from a TRIS Register bit puts the corresponding output driver in a hi-impedance (input) mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. Note: Q Data Latch CK VSS Q RESET A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. RD Port Note 1: I/O pins have protection diodes to VDD and VSS. The TRIS Registers are "write-only" and are set (output drivers disabled) upon RESET. TABLE 5-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I/O Control Registers (TRISA, TRISB, TRISC) Value on Power-On Reset Value on MCLR and WDT Reset 1111 1111 1111 1111 N/A TRIS 05h PORTA -- -- -- -- RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu Legend: Shaded boxes = unimplemented, read as `0', -- = unimplemented, read as '0', x = unknown, u = unchanged 2000 Microchip Technology Inc. Preliminary DS30453C-page 25 PIC16C5X 5.6 I/O Programming Considerations 5.6.1 BI-DIRECTIONAL I/O PORTS EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. ;Initial PORT Settings ; PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- ---------BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp MOVLW 03Fh ; TRIS PORTB ;10pp pppp 10pp pppp ; ;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High). Example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. 5.6.2 A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. FIGURE 5-2: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched SUCCESSIVE OPERATIONS ON I/O PORTS MOVWF PORTB PC + 1 MOVF PORTB,W Q1 Q2 Q3 Q4 PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. RB<7:0> Port pin written here Instruction executed DS30453C-page 26 MOVWF PORTB (Write to PORTB) Port pin sampled here MOVF PORTB,W (Read PORTB) Preliminary NOP 2000 Microchip Technology Inc. PIC16C5X 6.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1. The Timer0 module has the following features: * 8-bit timer/counter register, TMR0 - Readable and writable * 8-bit software programmable prescaler * Internal or external clock select - Edge select for external clock Note: Figure 6-1 is a simplified block diagram of the Timer0 module, while Figure 6-2 shows the electrical structure of the Timer0 input. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-3 and Figure 6-4). The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 6-1: The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. A summary of registers associated with the Timer0 module is found in Table 6-1. TIMER0 BLOCK DIAGRAM Data Bus FOSC/4 0 PSout 1 1 T0CKI pin Programmable Prescaler(2) T0SE(1) 0 8 Sync with Internal Clocks TMR0 reg PSout (2 cycle delay) Sync 3 T0CS(1) PSA(1) PS2, PS1, PS0(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6). FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN RIN T0CKI pin (1) VSS N (1) Schmitt Trigger Input Buffer VSS Note 1: ESD protection circuits. 2000 Microchip Technology Inc. Preliminary DS30453C-page 27 PIC16C5X FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 T0 Timer0 T0+1 Instruction Executed FIGURE 6-4: PC+3 T0+2 NT0 NT0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 PC+4 PC+5 MOVF TMR0,W NT0 NT0+1 Read TMR0 reads NT0 + 1 Read TMR0 reads NT0 PC+6 MOVF TMR0,W NT0+2 Read TMR0 reads NT0 + 2 TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 PC PC+1 MOVWF TMR0 Instruction Fetch T0 Timer0 PC+3 PC+4 PC+5 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 PC+6 MOVF TMR0,W NT0+1 NT0 Write TMR0 executed TABLE 6-1: PC+2 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W T0+1 Instruction Execute Address PC+2 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 T0 Read TMR0 reads NT0 + 1 REGISTERS ASSOCIATED WITH TIMER0 Name 01h TMR0 N/A OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 - 8-bit real-time clock/counter -- -- T0CS T0SE PSA Value on Power-on Reset Value on MCLR and WDT Reset xxxx xxxx uuuu uuuu PS2 PS1 PS0 --11 1111 --11 1111 Legend: Shaded cells: Unimplemented bits, - = unimplemented, x = unknown, u = unchanged. DS30453C-page 28 Preliminary 2000 Microchip Technology Inc. PIC16C5X 6.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. FIGURE 6-5: 6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing. TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Prescaler Output (2) Q1 Q2 Q3 Q4 Small pulse misses sampling (1) External Clock/Prescaler Output After Sampling (3) Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 2000 Microchip Technology Inc. Preliminary DS30453C-page 29 PIC16C5X 6.2 Prescaler EXAMPLE 6-1: An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 6.1.2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. 1.CLRWDT 2.CLRF TMR0 3.MOVLW '00xx1111'b 4.OPTION 5.CLRWDT 6.MOVLW '00xx1xxx'b 7.OPTION The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. EXAMPLE 6-2: CHANGING PRESCALER (WDTTIMER0) CLRWDT SWITCHING PRESCALER ASSIGNMENT MOVLW The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. FIGURE 6-6: ;Clear WDT ;Clear TMR0 & Prescaler ;These 3 lines (5, 6, 7) ; are required only if ; desired ;PS<2:0> are 000 or ;001 ;Set Postscaler to ; desired WDT rate To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's. 6.2.1 CHANGING PRESCALER (TIMER0WDT) 'xxxx0xxx' ;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source OPTION BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = FOSC/4) Data Bus 0 T0CKI pin 1 8 M U X 1 M U X 0 Sync 2 Cycles TMR0 reg T0SE T0CS 0 Watchdog Timer 1 M U X PSA 8-bit Prescaler 8 8 - to - 1MUX PS<2:0> PSA WDT Enable bit 1 0 MUX PSA WDT Time-Out Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. DS30453C-page 30 Preliminary 2000 Microchip Technology Inc. PIC16C5X 7.0 SPECIAL FEATURES OF THE CPU The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external RESET or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC16C5X family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: * * * * * * * * 7.1 Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type and one bit is the Watchdog Timer enable bit. Nine bits are code protection bits (Figure 7-1 and Figure 7-2) for the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, and PIC16CR58 devices. Oscillator selection RESET Power-on Reset (POR) Device Reset Timer (DRT) Watchdog Timer (WDT) SLEEP Code Protection ID locations QTP or ROM devices have the oscillator configuration programmed at the factory and these parts are tested accordingly (see "Product Identification System" diagrams in the back of this data sheet). The PIC16C5X Family has a Watchdog Timer, which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in RESET until the crystal oscillator is stable. With this timer on-chip, most applications need no external RESET circuitry. FIGURE 7-1: Configuration Bits CONFIGURATION WORD FOR PIC16CR54A/C54C/CR54C/C55A/C56A/CR56A/C57C/ CR57C/C58B/CR58B CP CP CP CP CP CP CP CP CP bit11 10 9 8 7 6 5 4 3 WDTE FOSC1 FOSC0 2 1 bit0 Register: Address(1): CONFIG FFFh bit 11-3: CP: Code protection bits 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to access the configuration word. 2000 Microchip Technology Inc. Preliminary DS30453C-page 31 PIC16C5X FIGURE 7-2: CONFIGURATION WORD FOR PIC16C54/C54A/C55/C56/C57 -- -- -- -- -- -- -- -- CP bit11 10 9 8 7 6 5 4 3 WDTE FOSC1 FOSC0 2 1 bit0 Register: Address(1): CONFIG FFFh bit 11-4: Unimplemented: Read as '0' bit 3: CP: Code protection bit. 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator selection bits(2) 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the configuration word. 2: PIC16LV54A supports XT, RC and LP oscillator only. PIC16LV58A supports XT, RC and LP oscillator only. DS30453C-page 32 Preliminary 2000 Microchip Technology Inc. PIC16C5X 7.2 Oscillator Configurations 7.2.1 OSCILLATOR TYPES FIGURE 7-4: PIC16C5Xs can be operated in four different oscillator modes. The user can program two configuration bits (FOSC<1:0>) to select one of these four modes: * * * * LP: XT: HS: RC: Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor Note: Not all oscillator selections available for all parts. See Section 7.1. 7.2.2 TABLE 7-1: Osc Type XT In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 7-3). The PIC16C5X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 7-4). CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION) C1(1) OSC1 PIC16C5X SLEEP XTAL RS(2) RF(3) OSC2 HS Note: CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16C5X, PIC16CR5X Resonator Freq Cap. Range C1 Cap. Range C2 455 kHz 22-100 pF 22-100 pF 2.0 MHz 15-68 pF 15-68 pF 4.0 MHz 15-68 pF 15-68 pF 4.0 MHz 15-68 pF 15-68 pF 8.0 MHz 10-68 pF 10-68 pF 16.0 MHz 10-22 pF 10-22 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. TABLE 7-2: Osc Type OSC2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC16C5X, PIC16CR5X Resonator Freq Cap.Range C1 Cap. Range C2 15 pF 15 pF 32 kHz(1) 100 kHz 15-30 pF 30-47 pF 200 kHz 15-30 pF 15-82 pF XT 100 kHz 15-30 pF 200-300 pF 15-30 pF 100-200 pF 200 kHz 15-30 pF 15-100 pF 455 kHz 1 MHz 15-30 pF 15-30 pF 2 MHz 15-30 pF 15-30 pF 4 MHz 15-47 pF 15-47 pF HS 4 MHz 15-30 pF 15-30 pF 8 MHz 15-30 pF 15-30 pF 20 MHz 15-30 pF 15-30 pF Note 1: For VDD > 4.5V, C1 = C2 30 pF is recommended. 2: These values are for design guidance only. Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. LP To internal logic C2(1) Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen (approx. value = 10 M). Note: 2000 Microchip Technology Inc. OSC1 PIC16C5X Clock from ext. system Open CRYSTAL OSCILLATOR / CERAMIC RESONATORS FIGURE 7-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Preliminary If you change from one device to another device, please verify oscillator characteristics in your application. DS30453C-page 33 PIC16C5X 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT FIGURE 7-6: Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance or one with series resonance. Figure 7-5 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. FIGURE 7-5: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE) To Other Devices 10k 74AS04 4.7k 74AS04 PIC16C5X OSC1 OSC2 10k 100k XTAL Note: 20 pF If you change from one device to another device, please verify oscillator characteristics in your application. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region. DS30453C-page 34 To Other Devices 330 74AS04 74AS04 74AS04 PIC16C5X OSC1 0.1 F OSC2 XTAL 100k Note: If you change from one device to another device, please verify oscillator characteristics in your application. RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-7 shows how the R/C combination is connected to the PIC16C5X. For REXT values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 3 k and 100 k. 10k 20 pF 330 7.2.4 +5V EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE) Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Preliminary 2000 Microchip Technology Inc. PIC16C5X The Electrical Specification sections show RC frequency variation from part to part due to normal process variation. Also, see the Electrical Specification sections for variation of oscillator frequency due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for given R, C and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic. FIGURE 7-7: RC OSCILLATOR MODE VDD REXT OSC1 N CEXT Internal clock PIC16C5X VSS FOSC/4 OSC2/CLKOUT Note: If you change from one device to another device, please verify oscillator characteristics in your application. 2000 Microchip Technology Inc. 7.3 RESET PIC16C5X devices may be RESET in one of the following ways: * * * * * Power-on Reset (POR) MCLR Reset (normal operation) MCLR Wake-up Reset (from SLEEP) WDT Reset (normal operation) WDT Wake-up Reset (from SLEEP) Table 7-3 shows these RESET conditions for the PCL and STATUS registers. Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on Power-on Reset (POR), MCLR or WDT Reset. A MCLR or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before SLEEP. The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different RESET conditions (Section 7.7). These bits may be used to determine the nature of the RESET. Table 7-4 lists a full description of RESET states of all registers. Figure 7-8 shows a simplified block diagram of the on-chip RESET circuit. Preliminary DS30453C-page 35 PIC16C5X TABLE 7-3: RESET CONDITIONS FOR SPECIAL REGISTERS PCL Addr: 02h STATUS Addr: 03h Power-on Reset 1111 1111 0001 1xxx MCLR Reset (normal operation) 1111 1111 000u uuuu(1) MCLR Wake-up (from SLEEP) 1111 1111 0001 0uuu WDT Reset (normal operation) 1111 1111 0000 uuuu(2) Condition WDT Wake-up (from SLEEP) 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented read as '0'. Note 1: TO and PD bits retain their last value until one of the other RESET conditions occur. 2: The CLRWDT instruction will set the TO and PD bits. TABLE 7-4: 0000 0uuu RESET CONDITIONS FOR ALL REGISTERS Register Address Power-on Reset MCLR or WDT Reset W N/A xxxx xxxx uuuu uuuu TRIS N/A 1111 1111 1111 1111 OPTION N/A --11 1111 --11 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu (1) 02h 1111 1111 1111 1111 STATUS(1) 03h 0001 1xxx 000q quuu FSR 04h 1xxx xxxx 1uuu uuuu PORTA 05h ---- xxxx ---- uuuu 06h xxxx xxxx uuuu uuuu 07h xxxx xxxx uuuu uuuu PCL PORTB (2) PORTC General Purpose Register Files 07-7Fh xxxx xxxx Legend: u = unchanged, x = unknown, - = unimplemented, read as '0', q = see tables in Section 7.7 for possible values. Note 1: See Table 7-3 for RESET value for specific conditions. 2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58. FIGURE 7-8: uuuu uuuu SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-up Detect POR (Power-on Reset) VDD MCLR/VPP pin WDT Time-out RESET WDT On-Chip RC OSC 8-bit Asynch Ripple Counter (Start-Up Timer) S Q R Q CHIP RESET DS30453C-page 36 Preliminary 2000 Microchip Technology Inc. PIC16C5X 7.4 Power-on Reset (POR) FIGURE 7-9: The PIC16C5X family incorporates on-chip Power-on Reset (POR) circuitry which provides an internal chip RESET for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 7-8. The Power-on Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the Reset Latch is set and the DRT is RESET. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the Reset Latch and thus end the on-chip RESET signal. A power-up example where MCLR is not tied to VDD is shown in Figure 7-10. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of RESET TDRT msec after MCLR goes high. In Figure 7-11, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together). The VDD is stable before the start-up timer times out and there is no problem in getting a proper RESET. However, Figure 7-12 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses a high on the MCLR/VPP pin, and when the MCLR/VPP pin (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external (RESET) BOR circuits or external RC circuits be used to achieve longer POR delay times (Figure 7-9). Note: VDD EXAMPLE OF EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD D R R1 MCLR C PIC16C5X * External Power-on Reset circuit is required only if VDD power-up is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. * R < 40 k is recommended to make sure that voltage drop across R does not violate the device electrical specification. * R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For more information on PIC16C5X POR, see Power-Up Considerations - AN522 in the Embedded Control Handbook. The POR circuit does not produce an internal RESET when VDD declines. 2000 Microchip Technology Inc. Preliminary DS30453C-page 37 PIC16C5X FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will RESET properly if, and only if, V1 VDD min. DS30453C-page 38 Preliminary 2000 Microchip Technology Inc. PIC16C5X 7.5 Device Reset Timer (DRT) 7.6 The Device Reset Timer (DRT) provides a fixed 18 ms nominal time-out on RESET. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after the voltage on the MCLR/VPP pin has reached a logic high (VIH) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications. The Device Reset time delay will vary from device to device due to VDD, temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the PIC16C5X from SLEEP mode automatically. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT Reset or Wake-up Reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a '0' (Section 7.1). Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the configuration word. 7.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. 7.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT Wake-up Reset. 2000 Microchip Technology Inc. Preliminary DS30453C-page 39 PIC16C5X FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source 0 M 1 Watchdog Postscaler Postscaler U Timer X 8 - to - 1 MUX PS<2:0> PSA WDT Enable EPROM Bit To TMR0 1 0 MUX PSA Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. WDT Time-out TABLE 7-5: Address N/A SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Name OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset -- -- T0CS T0SE PSA PS2 PS1 PS0 --11 1111 Value on MCLR and WDT Reset --11 1111 Legend: Shaded boxes = Not used by Watchdog Timer, - = unimplemented, read as '0', u = unchanged DS30453C-page 40 Preliminary 2000 Microchip Technology Inc. PIC16C5X 7.7 Time-Out Sequence and Power-down Status Bits (TO/PD) The TO and PD bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset, or a MCLR or WDT Wake-up Reset. TABLE 7-6: TO PD 1 1 u u 1 0 TO/PD STATUS AFTER RESET RESET on Brown-Out A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC16C5X devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-14 and Figure 7-15. FIGURE 7-14: BROWN-OUT PROTECTION CIRCUIT 1 RESET was caused by VDD Power-up (POR) (1) MCLR Reset (normal operation) MCLR Wake-up Reset (from SLEEP) 0 1 WDT Reset (normal operation) 0 0 WDT Wake-up Reset (from SLEEP) Legend: u = unchanged Note 1: The TO and PD bits maintain their status (u) until a RESET occurs. A low-pulse on the MCLR input does not change the TO and PD status bits. These STATUS bits are only affected by events listed in Table 7-7. TABLE 7-7: Event EVENTS AFFECTING TO/PD STATUS BITS TO Power-up WDT Time-out SLEEP instruction CLRWDT instruction Legend: u = unchanged Note: 7.8 PD 1 1 0 u 1 0 1 1 10k Q1 MCLR 40k PIC16C5X This circuit will activate RESET when VDD goes below Vz + 0.7V (where Vz = Zener voltage). FIGURE 7-15: BROWN-OUT PROTECTION CIRCUIT 2 VDD Remarks VDD R1 No effect on PD Q1 MCLR R2 A WDT time-out will occur regardless of the status of the TO bit. A SLEEP instruction will be executed, regardless of the status of the PD bit. Table 7-3 lists the RESET conditions for the Special Function Registers, while Table 7-4 lists the RESET conditions for all the registers. 2000 Microchip Technology Inc. VDD 33k 40k PIC16C5X This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 = 0.7V VDD * R1 + R2 Preliminary DS30453C-page 41 PIC16C5X FIGURE 7-16: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 7.10 If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. VDD MCP809 bypass capacitor Vss Program Verification/Code Protection VDD Note: VDD Microchip does not recommend code protecting windowed devices. RST MCLR 7.11 PIC16C62X This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both "active high and active low" RESET pins. There are 7 different trip point selections to accommodate 5V and 3V systems. 7.9 ID Locations Four memory locations are designated as ID locations, where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as '1's. Note: Power-down Mode (SLEEP) Microchip will assign a unique pattern number for QTP and SQTP requests and for ROM devices. This pattern number will be unique and traceable to the submitted code. A device may be powered down (SLEEP) and later powered up (wake-up from SLEEP). 7.9.1 SLEEP The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR/VPP pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the MCLR/VPP pin must be at a logic high level. 7.9.2 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. 2. An external RESET input on MCLR/VPP pin. A Watchdog Timer time-out RESET (if WDT was enabled). Both of these events cause a device RESET. The TO and PD bits can be used to determine the cause of device RESET. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The WDT is cleared when the device wakes from SLEEP, regardless of the wake-up source. DS30453C-page 42 Preliminary 2000 Microchip Technology Inc. PIC16C5X 8.0 INSTRUCTION SET SUMMARY Each PIC16C5X instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16C5X instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator is used to specify which one of the 32 file registers in that bank is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time would be 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time would be 2 s. Figure 8-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where 'h' signifies a hexadecimal digit. FIGURE 8-1: Byte-oriented file register operations 11 For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. TABLE 8-1: GENERAL FORMAT FOR INSTRUCTIONS 6 OPCODE 5 d 4 0 f (FILE #) d = 0 for destination W d = 1 for destination f f = 5-bit file register address OPCODE FIELD DESCRIPTIONS Bit-oriented file register operations Field Description 11 f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d label TOS PC WDT 8 7 OPCODE 0 k (literal) k = 8-bit immediate value Literal and control operations - GOTO instruction 11 9 8 OPCODE Program Counter 0 k (literal) k = 9-bit immediate value Watchdog Timer Counter Power-down bit 11 Top of Stack Time-out bit italics 0 f (FILE #) Literal and control operations (except GOTO) Label name PD [ ] ( ) <> 8 7 5 4 b (BIT #) b = 3-bit bit address f = 5-bit file register address Destination select; d = 0 (store result in W) d = 1 (store result in file register 'f') Default is d = 1 TO dest OPCODE Destination, either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier) 2000 Microchip Technology Inc. Preliminary DS30453C-page 43 PIC16C5X TABLE 8-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f,d f,d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d 12-Bit Opcode Description Cycles MSb Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Swap f Exclusive OR W with f LSb Status Affected Notes 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z 1,2,4 2,4 4 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff None None None None 2,4 2,4 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk Z None TO, PD None Z None None None TO, PD None Z 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set LITERAL AND CONTROL OPERATIONS ANDLW CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW k k k k k k k k - f k AND literal with W Call subroutine Clear Watchdog Timer Unconditional branch Inclusive OR Literal with W Move Literal to W Load OPTION register Return, place Literal in W Go into standby mode Load TRIS register Exclusive OR Literal to W 1 3 Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO. (See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers) 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS30453C-page 44 Preliminary 2000 Microchip Technology Inc. PIC16C5X ADDWF Add W and f f,d ANDWF AND W with f Syntax: [ label ] ADDWF Syntax: [ label ] ANDWF Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (W) + (f) (dest) Operation: (W) .AND. (f) (dest) Status Affected: C, DC, Z Encoding: 0001 f,d Status Affected: Z 11df Encoding: ffff 0001 01df ffff Description: Add the contents of the W register and register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. Description: The contents of the W register are AND'ed with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: ADDWF Example: ANDWF FSR, 0 Before Instruction W = FSR = W = 0x17 TEMP_REG = 0xC2 After Instruction 0xD9 0xC2 W = 0x17 TEMP_REG = 0x2 ANDLW And literal with W Syntax: [ label ] ANDLW k Operands: 0 k 255 Operation: (W).AND. (k) (W) Status Affected: Z Encoding: 1110 Description: kkkk 1 Cycles: 1 Example: ANDLW BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 31 0b7 Operation: 0 (f<b>) Encoding: = = bbbf ffff Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Example: BCF 0x5F FLAG_REG, 7 Before Instruction FLAG_REG = 0xC7 0xA3 After Instruction After Instruction W 0100 Description: Before Instruction W f,b Status Affected: None kkkk The contents of the W register are AND'ed with the eight-bit literal 'k'. The result is placed in the W register. Words: 1 Before Instruction 0x17 0xC2 After Instruction W = FSR = FSR, FLAG_REG = 0x47 0x03 2000 Microchip Technology Inc. Preliminary DS30453C-page 45 PIC16C5X BSF Bit Set f f,b BTFSS Bit Test f, Skip if Set Syntax: [ label ] BSF Syntax: [ label ] BTFSS f,b Operands: 0 f 31 0b7 Operands: 0 f 31 0b<7 Operation: 1 (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Encoding: Status Affected: None 0101 bbbf Encoding: ffff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Example: BSF FLAG_REG, Description: 0111 7 FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A If bit 'b' in register 'f' is '1' then the next instruction is skipped. Words: 1 Cycles: 1(2) Example: HERE FALSE TRUE BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 f 31 0b7 Before Instruction skip if (f<b>) = 0 After Instruction * * PC Status Affected: None Encoding: Description: 0110 bbbf ffff If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2-cycle instruction. Before Instruction Operation: bbbf ffff If bit 'b' in register 'f' is 0 then the next instruction is skipped. If FLAG<1> PC if FLAG<1> PC BTFSS GOTO * FLAG,1 PROCESS_CODE = address (HERE) = = = = 0, address (FALSE); 1, address (TRUE) If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2-cycle instruction. Words: 1 Cycles: 1(2) Example: HERE FALSE TRUE BTFSC GOTO FLAG,1 PROCESS_CODE * * * Before Instruction PC = address (HERE) = = = = 0, address (TRUE); 1, address(FALSE) After Instruction if FLAG<1> PC if FLAG<1> PC DS30453C-page 46 Preliminary 2000 Microchip Technology Inc. PIC16C5X CALL Subroutine Call CLRW Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 k 255 Operands: None Operation: (PC) + 1 Top of Stack; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8> Operation: 00h (W); 1Z Status Affected: Z Encoding: Status Affected: None Encoding: Description: 1001 kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two-cycle instruction. 1 Cycles: 2 Example: HERE CALL After Instruction address (THERE) address (HERE + 1) CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 31 Operation: 00h (f); 1Z The W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example: CLRW Before Instruction W = 0x5A 0000 f 1 Cycles: 1 Example: CLRF Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD Encoding: Description: 011f ffff 0x5A 1 1 Example: CLRWDT = = 0x00 1 2000 Microchip Technology Inc. 0100 Before Instruction WDT counter = ? After Instruction WDT counter WDT prescale TO PD After Instruction FLAG_REG Z 0000 The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. Cycles: FLAG_REG = 0000 Words: Before Instruction FLAG_REG 0x00 1 Status Affected: TO, PD The contents of register 'f' are cleared and the Z bit is set. Words: = = CLRWDT Status Affected: Z Description: 0000 THERE address (HERE) Encoding: 0100 Description: W Z Before Instruction PC = TOS = 0000 After Instruction Words: PC = Clear W Preliminary = = = = 0x00 0 1 1 DS30453C-page 47 PIC16C5X COMF Complement f f,d DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF Syntax: [ label ] DECFSZ f,d Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f) (dest) Operation: (f) - 1 d; Status Affected: Z Encoding: Status Affected: None 0010 01df Encoding: ffff Description: The contents of register 'f' are complemented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: COMF = REG1,0 0x13 After Instruction REG1 W = = Description: Decrement f Syntax: [ label ] DECF f,d Operands: 0 f 31 d [0,1] Operation: (f) - 1 (dest) 1 Cycles: 1(2) Example: HERE Description: PC 1 Cycles: 1 Example: DECF Before Instruction CNT Z = = = = CNT, 1 LOOP = address (HERE) CNT if CNT PC if CNT PC 11df CNT, = = = = CNT - 1; 0, address (CONTINUE); 0, address (HERE+1) ffff GOTO Unconditional Branch Syntax: [ label ] Operands: 0 k 511 Operation: k PC<8:0>; STATUS<6:5> PC<10:9> 1 GOTO k Status Affected: None 0x01 0 After Instruction CNT Z DECFSZ GOTO CONTINUE * * * After Instruction Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: ffff Before Instruction Status Affected: Z 0000 11df The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 0x13 0xEC DECF Encoding: 0010 If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. Before Instruction REG1 skip if result = 0 Encoding: 101k kkkk kkkk Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a two-cycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE 0x00 1 After Instruction PC = DS30453C-page 48 Preliminary address (THERE) 2000 Microchip Technology Inc. PIC16C5X INCF Increment f IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 k 255 (f) + 1 (dest) Operation: (W) .OR. (k) (W) Operation: INCF f,d Status Affected: Z Status Affected: Z Encoding: Description: Words: Encoding: 0010 10df ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. 1 Cycles: 1 Example: INCF CNT, = = 1101 kkkk kkkk Description: The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: IORLW 0x35 Before Instruction 1 W Before Instruction CNT Z IORLW k = 0x9A After Instruction 0xFF 0 W Z = = 0xBF 0 After Instruction CNT Z INCFSZ = = 0x00 1 Increment f, Skip if 0 IORWF Inclusive OR W with f Syntax: [ label ] Operands: 0 f 31 d [0,1] (W).OR. (f) (dest) Syntax: [ label ] Operands: 0 f 31 d [0,1] Operation: (f) + 1 (dest), skip if result = 0 Encoding: Operation: INCFSZ f,d Description: 0011 11df If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. 1 Cycles: 1(2) Example: HERE 0001 00df ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Example: IORWF ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: f,d Status Affected: Z Status Affected: None Encoding: IORWF RESULT, 0 Before Instruction RESULT = W = 0x13 0x91 After Instruction INCFSZ GOTO CONTINUE * * * CNT, LOOP 1 RESULT = W = Z = 0x13 0x93 0 Before Instruction PC = address (HERE) After Instruction CNT if CNT PC if CNT PC = = = = CNT + 1; 0, address (CONTINUE); 0, address (HERE +1) 2000 Microchip Technology Inc. Preliminary DS30453C-page 49 PIC16C5X MOVF Move f Syntax: [ label ] Operands: 0 f 31 d [0,1] MOVF f,d Operation: (f) (dest) 0010 Description: Move W to f Syntax: [ label ] Operands: 0 f 31 Operation: (W) (f) Encoding: 00df ffff Description: The contents of register 'f' is moved to destination 'd'. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test a file register since status flag Z is affected. 1 Cycles: 1 Example: MOVF 0000 001f 1 Cycles: 1 Example: MOVWF TEMP_REG W FSR, TEMP_REG = = 0xFF 0x4F = = 0x4F 0x4F After Instruction 0 TEMP_REG W value in FSR register NOP No Operation MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: No operation Operation: k (W) Status Affected: None MOVLW k Status Affected: None Encoding: 1100 Description: ffff Move data from the W register to register 'f'. Words: After Instruction = f Before Instruction Words: W MOVWF Status Affected: None Status Affected: Z Encoding: MOVWF Encoding: kkkk Description: kkkk 0000 NOP 0000 0000 No operation. The eight bit literal 'k' is loaded into the W register. The don't cares will assemble as 0s. Words: 1 Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = DS30453C-page 50 0x5A Preliminary 2000 Microchip Technology Inc. PIC16C5X OPTION Load OPTION Register RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RLF Operands: None Operands: Operation: (W) OPTION 0 f 31 d [0,1] Operation: See description below OPTION Status Affected: None Encoding: 0000 0000 0010 Status Affected: C Description: The content of the W register is loaded into the OPTION register. Words: 1 Cycles: 1 Example Encoding: Description: OPTION 0011 = After Instruction 0x07 RETLW Return with Literal in W Syntax: [ label ] Operands: 0 k 255 Operation: k (W); TOS PC Words: 1 Cycles: 1 Example: RLF 1000 Description: kkkk REG1 C REG1 W C 1 Cycles: 2 Example: CALL TABLE ;W contains ;table offset ;value. * ;W now has table * ;value. * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table W = = = = = 1110 0110 1100 1100 1 RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 31 d [0,1] Operation: See description below RRF f,d Status Affected: C Encoding: Description: 0011 00df ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Words: 1 Cycles: 1 Example: RRF register 'f' REG1,0 Before Instruction 0x07 REG1 C After Instruction W 1110 0110 0 kkkk Words: Before Instruction = = After Instruction The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. TABLE REG1,0 Before Instruction RETLW k Status Affected: None Encoding: ffff register 'f' C 0x07 OPTION = 01df The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. Before Instruction W f,d value of k8 = = 1110 0110 0 After Instruction REG1 W C 2000 Microchip Technology Inc. Preliminary = = = 1110 0110 0111 0011 0 DS30453C-page 51 PIC16C5X SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] Syntax: [label] Operands: None Operands: Operation: 00h WDT; 0 WDT prescaler; 1 TO; 0 PD 0 f 31 d [0,1] Operation: (f) - (W) (dest) SLEEP Status Affected: C, DC, Z Encoding: Status Affected: TO, PD Encoding: Description: 0000 Description: 0000 0011 Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See section on SLEEP for more details. Words: 1 Cycles: 1 Example: SLEEP SUBWF f,d 0000 10df ffff Subtract (2's complement method) the W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example 1: SUBWF REG1, 1 Before Instruction REG1 W C = = = 3 2 ? After Instruction REG1 W C = = = 1 2 1 ; result is positive Example 2: Before Instruction REG1 W C = = = 2 2 ? After Instruction REG1 W C = = = 0 2 1 ; result is zero Example 3: Before Instruction REG1 W C = = = 1 2 ? After Instruction REG1 W C DS30453C-page 52 Preliminary = = = FF 2 0 ; result is negative 2000 Microchip Technology Inc. PIC16C5X SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] Operands: 0 f 31 d [0,1] Operands: 0 k 255 (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) Operation: Operation: (W) .XOR. k (W) Status Affected: Z Encoding: Status Affected: None XORLW k 1111 kkkk kkkk Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Words: 1 Example: XORLW Cycles: 1 Example SWAPF Encoding: Description: 0011 10df ffff Before Instruction REG1, W 0 = = 0xB5 After Instruction Before Instruction REG1 0xAF W 0xA5 = 0x1A After Instruction REG1 W TRIS = = 0xA5 0X5A XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 f 31 d [0,1] Operation: (W) .XOR. (f) (dest) Load TRIS Register Syntax: [ label ] TRIS Operands: f = 5, 6 or 7 f Operation: (W) TRIS register f Status Affected: Z Encoding: Status Affected: None Encoding: 0000 0000 0001 Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example XORWF PORTA Before Instruction W = = REG,1 Before Instruction 0XA5 REG W After Instruction TRISA ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. TRIS register 'f' (f = 5, 6, or 7) is loaded with the contents of the W register. TRIS 10df Description: 0fff Description: Example f,d 0xAF 0xB5 After Instruction 0XA5 REG W 2000 Microchip Technology Inc. = = Preliminary = = 0x1A 0xB5 DS30453C-page 53 PIC16C5X NOTES: DS30453C-page 54 Preliminary 2000 Microchip Technology Inc. PIC16C5X 9.0 DEVELOPMENT SUPPORT MPLAB allows you to: The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASM Assembler - MPLAB-C17 and MPLAB-C18 C Compilers - MPLINK/MPLIB Linker/Librarian * Simulators - MPLAB-SIM Software Simulator * Emulators - MPLAB-ICE Real-Time In-Circuit Emulator - ICEPICTM * In-Circuit Debugger - MPLAB-ICD for PIC16F87 * Device Programmers - PRO MATE II Universal Programmer - PICSTART Plus Entry-Level Prototype Programmer * Low-Cost Demonstration Boards - PICDEM-1 - PICDEM-2 - PICDEM-3 - PICDEM-17 - KEELOQ 9.1 The ability to use MPLAB with Microchip's simulator, MPLAB-SIM, allows a consistent platform and the ability to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 9.2 MPASM Assembler MPASM is a full featured universal macro assembler for all PICmicro MCU's. It can produce absolute code directly in the form of HEX files for device programmers, or it can generate relocatable objects for MPLINK. MPASM has a command line interface and a Windows shell and can be used as a standalone application on a Windows 3.x or greater system. MPASM generates relocatable object files, Intel standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file which contains source lines and generated machine code, and a COD file for MPLAB debugging. MPASM features include: MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a Windows-based application which contains: * Multiple functionality - editor - simulator - programmer (sold separately) - emulator (sold separately) * A full featured editor * A project manager * Customizable tool bar and key mapping * A status bar * On-line help * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file - object code * MPASM and MPLINK are integrated into MPLAB projects. * MPASM allows user defined macros to be created for streamlined assembly. * MPASM allows conditional assembly for multi purpose source files. * MPASM directives allow complete control over the assembly process. 9.3 MPLAB-C17 and MPLAB-C18 C Compilers The MPLAB-C17 and MPLAB-C18 Code Development Systems are complete ANSI `C' compilers and integrated development environments for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display. 2000 Microchip Technology Inc. Preliminary DS30453C-page 55 PIC16C5X 9.4 MPLINK/MPLIB Linker/Librarian MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with precompiled libraries using directives from a linker script. MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and modification of library files. MPLINK features include: * MPLINK works with MPASM and MPLAB-C17 and MPLAB-C18. * MPLINK allows all memory areas to be defined as sections to provide link-time flexibility. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support new PICmicro microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. MPLAB-ICE 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems use the same processor modules and will operate across the full operating speed range of the PICmicro MCU. 9.7 ICEPIC * MPLIB makes linking easier because single libraries can be included instead of many smaller files. * MPLIB helps keep code maintainable by grouping related modules together. * MPLIB commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. ICEPIC is a low-cost in-circuit emulation solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X, and PIC16CXXX families of 8-bit one-timeprogrammable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules or daughter boards. The emulator is capable of emulating without target application circuitry being present. 9.5 9.8 MPLIB features include: MPLAB-SIM Software Simulator The MPLAB-SIM Software Simulator allows code development in a PC host environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. The execution can be performed in single step, execute until break, or trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPLAB-C18 and MPASM. The Software Simulator offers the flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 9.6 MPLAB-ICE High Performance Universal In-Circuit Emulator with MPLAB IDE MPLAB-ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB-ICD, is a powerful, low-cost run-time development tool. This tool is based on the flash PIC16F877 and can be used to develop for this and other PICmicro microcontrollers from the PIC16CXXX family. MPLAB-ICD utilizes the In-Circuit Debugging capability built into the PIC16F87X. This feature, along with Microchip's In-Circuit Serial Programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in real-time. The MPLAB-ICD is also a programmer for the flash PIC16F87X family. The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of MPLAB-ICE is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. DS30453C-page 56 Preliminary 2000 Microchip Technology Inc. PIC16C5X 9.9 PRO MATE II Universal Programmer The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode the PRO MATE II can read, verify or program PICmicro devices. It can also set code-protect bits in this mode. 9.10 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus supports all PICmicro devices with up to 40 pins. Larger pin count devices such as the PIC16C92X, and PIC17C76X may be supported with an adapter socket. PICSTART Plus is CE compliant. 9.11 PICDEM-1 Low-Cost PICmicro Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 2000 Microchip Technology Inc. 9.12 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad. 9.13 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. Preliminary DS30453C-page 57 PIC16C5X 9.14 PICDEM-17 The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 9.15 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters. DS30453C-page 58 Preliminary 2000 Microchip Technology Inc. PIC16CXXX PIC16F62X PIC16C7X PIC16C7XX PIC16C8X PIC16F8XX PIC16C9XX PIC17C4X PIC17C7XX PIC18CXX2 a a a a a a a a a a a a a a a a a a a a a a 13.56 MHz Anticollision microID Developer's Kit a a DS30453C-page 59 MCP2510 CAN Developer's Kit (R) * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB -ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77 ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices. PIC16C5X a a a Demo Boards and Eval Kits a a 125 kHz Anticollision microID Developer's Kit 125 kHz microID Developer's Kit MCP2510 PIC16C6X a a a a a MCRFXXX PIC16C5X a a a a a a HCSXXX PIC14000 a a a a a a 24CXX/ 25CXX/ 93CXX PIC12CXXX a a a a a a Programmers Debugger Emulators Software Tools a a a a DEVELOPMENT TOOLS FROM MICROCHIP a a a a a TABLE 9-1: a a a a a a a a a a PICDEM-14A microIDTM Programmer's Kit a a a a a a a PICDEM-3 KEELOQ Transponder Kit a a a a a a ** PICDEM-2 KEELOQ(R) Evaluation Kit a a a a a ** PICDEM-1 PICDEM-17 a a a a a a PRO MATE II Universal Programmer * * a PICSTARTPlus Low-Cost Universal Dev. Kit ** a a a a (R) MPLAB -ICD In-Circuit Debugger a Preliminary a a ICEPIC Low-Cost In-Circuit Emulator a a MPASM/MPLINK (R) MPLAB -ICE a 2000 Microchip Technology Inc. (R) MPLAB Integrated Development Environment (R) MPLAB C17 Compiler (R) MPLAB C18 Compiler PIC16C5X NOTES: DS30453C-page 60 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.0 ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57 Absolute Maximum Ratings Ambient Temperature under bias ........................................................................................................... -55C to +125C Storage Temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................... 0V to +7.5V Voltage on MCLR with respect to VSS(2) ......................................................................................................... 0V to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.6V to (VDD + 0.6V) Total Power Dissipation(1) ....................................................................................................................................800 mW Max. Current out of VSS pin ..................................................................................................................................150 mA Max. Current into VDD pin .....................................................................................................................................100 mA Max. Current into an input pin (T0CKI only) ....................................................................................................................500 A Input Clamp Current, IIK (VI < 0 or VI > VDD) .................................................................................................................... 20 mA Output Clamp Current, IOK (VO < 0 or VO > VDD) ............................................................................................................ 20 mA Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................20 mA Max. Output Current sourced by a single I/O port (PORTA, B or C).......................................................................40 mA Max. Output Current sunk by a single I/O port (PORTA, B or C) ............................................................................50 mA Note 1: Power Dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2000 Microchip Technology Inc. Preliminary DS30453C-page 61 PIC16C5X 10.1 PIC16C54/55/56/57 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C Sym Min Typ(1) Max Units 3.0 3.0 4.5 4.5 2.5 -- -- -- -- -- -- 6.25 6.25 5.5 5.5 6.25 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 20 MHz FOSC = DC to 40 kHz Conditions Supply Voltage PIC16C5X-RC PIC16C5X-XT PIC16C5X-10 PIC16C5X-HS PIC16C5X-LP VDD RAM Data Retention Voltage(2) VDR 1.5* -- V Device in SLEEP Mode VDD Start Voltage to ensure Power-on Reset VPOR VSS -- V See Section 7.4 for details on Power-on Reset VDD Rise Rate to ensure Power-on Reset SVDD 0.05* -- -- V/ms See Section 7.4 for details on Power-on Reset IDD -- -- -- -- -- -- -- 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 32 mA mA mA mA mA A FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.0V, WDT disabled -- -- 4.0 0.6 12 9 A A VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled Supply Current(3) PIC16C5X-RC(4) PIC16C5X-XT PIC16C5X-10 PIC16C5X-HS PIC16C5X-LP Power-down Current(5) IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30453C-page 62 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.2 DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C Sym Min Typ(1) Max Units 3.0 3.0 4.5 4.5 2.5 -- -- -- -- -- 6.25 6.25 5.5 5.5 6.25 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 20 MHz FOSC = DC to 40 kHz Conditions Supply Voltage PIC16C5X-RCI PIC16C5X-XTI PIC16C5X-10I PIC16C5X-HSI PIC16C5X-LPI VDD RAM Data Retention Voltage(2) VDR -- 1.5* -- V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD Rise Rate to ensure Power-on Reset SVDD 0.05* -- -- V/ms See Section 7.4 for details on Power-on Reset -- -- -- -- -- -- 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 40 mA mA mA mA mA A FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.0V, WDT disabled -- -- 4.0 0.6 14 12 A A VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled Supply Current(3) PIC16C5X-RCI(4) PIC16C5X-XTI PIC16C5X-10I PIC16C5X-HSI IDD PIC16C5X-LPI Power-down Current(5) IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 2000 Microchip Technology Inc. Preliminary DS30453C-page 63 PIC16C5X 10.3 PIC16C54/55/56/57 DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C Sym Min Typ (1) Max Units 3.25 3.25 4.5 4.5 2.5 -- -- -- -- -- 6.0 6.0 5.5 5.5 6.0 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 16 MHz FOSC = DC to 40 kHz Conditions Supply Voltage PIC16C5X-RCE PIC16C5X-XTE PIC16C5X-10E PIC16C5X-HSE PIC16C5X-LPE VDD RAM Data Retention Voltage(2) VDR -- 1.5* -- V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD rise rate to ensure Power-on Reset SVDD 0.05* -- -- V/ms See Section 7.4 for details on Power-on Reset -- -- -- -- -- -- 1.8 1.8 4.8 4.8 9.0 19 3.3 3.3 10 10 20 55 mA mA mA mA mA A FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 16 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.25V, WDT disabled -- -- 5.0 0.8 22 18 A A VDD = 3.25V, WDT enabled VDD = 3.25V, WDT disabled Supply Current(3) PIC16C5X-RCE(4) PIC16C5X-XTE PIC16C5X-10E PIC16C5X-HSE IDD PIC16C5X-LPE Power-down Current(5) IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30453C-page 64 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.4 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial) PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3. DC Characteristics All Pins Except Power Supply Pins Characteristic Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) VIL Input High Voltage I/O ports VIH MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) Hysteresis of Schmitt Trigger inputs Input Leakage Current(2,3) I/O ports VHYS Min Typ(1) Max Units VSS VSS VSS VSS VSS -- -- -- -- -- 0.2 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V V Pin at hi-impedance 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD -- -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD VDD V V V V V V V For all VDD(5) 4.0V < VDD 5.5V(5) VDD > 5.5V 0.15VDD* -- -- V -1 0.5 +1 A -3 -3 0.5 0.5 0.5 +5 +3 +3 A A A A -- -- -- -- 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC VDD - 0.7 VDD - 0.7 -- -- -- -- V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, PIC16C5X-RC IIL -5 MCLR T0CKI OSC1 Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage I/O ports(3) OSC2/CLKOUT VOH Conditions PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP For VDD 5.5V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16C5X-XT, 10, HS, LP * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. 2000 Microchip Technology Inc. Preliminary DS30453C-page 65 PIC16C5X 10.5 PIC16C54/55/56/57 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3. DC Characteristics All Pins Except Power Supply Pins Characteristic Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) VIL Input High Voltage I/O ports VIH MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) Hysteresis of Schmitt Trigger inputs Input Leakage Current (2,3) I/O ports VHYS Min Typ(1) Max Units Vss Vss Vss Vss Vss -- -- -- -- -- 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V V Pin at hi-impedance 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD -- -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD VDD V V V V V V V For all VDD(5) 4.0V < VDD 5.5V(5) VDD > 5.5 V 0.15VDD* -- -- V -1 0.5 +1 A -3 -3 0.5 0.5 0.5 +5 +3 +3 A A A A -- -- -- -- 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC VDD - 0.7 VDD - 0.7 -- -- -- -- V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, PIC16C5X-RC IIL -5 MCLR T0CKI OSC1 Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage I/O ports(3) OSC2/CLKOUT VOH Conditions PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP For VDD 5.5 V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16C5X-XT, 10, HS, LP * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. DS30453C-page 66 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.6 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low T Time mc osc os t0 wdt MCLR oscillator OSC1 T0CKI watchdog timer P R V Z Period Rise Valid Hi-impedance FIGURE 10-1: LOAD CONDITIONS - PIC16C54/55/56/57 Pin CL = 50 pF for all pins except OSC2 CL VSS 2000 Microchip Technology Inc. 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 Preliminary DS30453C-page 67 PIC16C5X 10.7 PIC16C54/55/56/57 Timing Diagrams and Specifications FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57 Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 AC Characteristics Parameter No. Sym FOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Characteristic External CLKIN Frequency(2) Oscillator Frequency(2) Min Typ(1) Max DC -- 4 MHz XT osc mode DC -- 10 MHz 10 MHz mode DC -- 20 MHz HS osc mode (Com/Indust) DC -- 16 MHz HS osc mode (Extended) DC -- 40 kHz DC -- 4 MHz RC osc mode 0.1 -- 4 MHz XT osc mode 4 -- 10 MHz 10 MHz mode 4 -- 20 MHz HS osc mode (Com/Indust) 4 -- 16 MHz HS osc mode (Extended) DC -- 40 kHz Units Conditions LP osc mode LP osc mode * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS30453C-page 68 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 (CON'T) AC Characteristics Parameter No. Sym 1 TOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Characteristic External CLKIN Period(2) Oscillator Period(2) 2 3 4 TCY Instruction Cycle Time(3) TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time Min Typ(1) Max Units 250 -- -- ns XT osc mode 100 -- -- ns 10 MHz mode 50 -- -- ns HS osc mode (Com/Indust) 62.5 -- -- ns HS osc mode (Extended) 25 -- -- s LP osc mode 250 -- -- ns RC osc mode 250 -- 10,000 ns XT osc mode 100 -- 250 ns 10 MHz mode 50 -- 250 ns HS osc mode (Com/Indust) 62.5 -- 250 ns HS osc mode (Extended) 25 -- -- s LP osc mode -- 4/FOSC -- -- 85* -- -- ns XT oscillator 20* -- -- ns HS oscillator 2* -- -- s LP oscillator -- -- 25* ns XT oscillator -- -- 25* ns HS oscillator -- -- 50* ns LP oscillator Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. 2000 Microchip Technology Inc. Preliminary DS30453C-page 69 PIC16C5X PIC16C54/55/56/57 FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57 Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57 AC Characteristics Parameter No. Sym Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Characteristic Min Typ(1) Max Units 10 TosH2ckL OSC1 to CLKOUT(2) -- 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(2) -- 15 30** ns 12 TckR CLKOUT rise time(2) -- 5 15** ns 13 TckF CLKOUT fall time(2) -- 5 15** ns 14 TckL2ioV CLKOUT to Port out valid(2) -- -- 40** ns 15 TioV2ckH Port in valid before CLKOUT(2) 0.25 TCY+30* -- -- ns 16 TckH2ioI Port in hold after CLKOUT(2) 0* -- -- ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(3) -- -- 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) TBD -- -- ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) TBD -- -- ns 20 TioR Port output rise time(3) -- 10 25** ns 21 TioF Port output fall time(3) -- 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 3: See Figure 10-1 for loading conditions. DS30453C-page 70 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING PIC16C54/55/56/57 VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Parameter No. Sym Characteristic Min Typ(1) Max Units 30 TmcL MCLR Pulse Width (low) 100* -- -- ns VDD = 5.0V 31 Twdt Watchdog Timer Time-out Period (No Prescaler) 9* 18* 30* ms VDD = 5.0V (Commercial) 32 TDRT Device Reset Timer Period 9* 18* 30* ms VDD = 5.0V (Commercial) 34 TioZ I/O Hi-impedance from MCLR Low -- -- 100* ns Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. Preliminary DS30453C-page 71 PIC16C5X PIC16C54/55/56/57 FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57 T0CKI 40 41 42 TABLE 10-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Parameter Sym Characteristic No. 40 Min Tt0H T0CKI High Pulse Width- No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width- No Prescaler - With Prescaler 42 Tt0P T0CKI Period Typ(1) Max Units Conditions 0.5 TCY + 20* -- -- ns 10* -- -- ns 0.5 TCY + 20* -- -- ns 10* -- -- ns 20 or TCY + 40* N -- -- ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30453C-page 72 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 11.0 DC AND AC CHARACTERISTICS - PIC16C54/55/56/57 The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation. FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC FOSC (25C) Frequency normalized to +25C 1.10 REXT 10 k CEXT = 100 pF 1.08 1.06 1.04 1.02 1.00 0.98 VDD = 5.5 V 0.96 0.94 VDD = 3.5 V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 11-1: RC OSCILLATOR FREQUENCIES CEXT Average FOSC @ 5 V, 25C REXT 20 pF 3.3 k 5k 10 k 100 k 100 pF 3.3 k 5k 10 k 100 k 300 pF 3.3 k 5.0 k 10 k 160 k The frequencies are measured on DIP packages. 4.973 MHz 3.82 MHz 2.22 MHz 262.15 kHz 1.63 MHz 1.19 MHz 684.64 kHz 71.56 kHz 660 kHz 484.1 kHz 267.63 kHz 29.44 kHz 27% 21% 21% 31% 13% 13% 18% 25% 10% 14% 15% 19% The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviations from the average value for VDD = 5 V. 2000 Microchip Technology Inc. Preliminary DS30453C-page 73 PIC16C5X PIC16C54/55/56/57 FIGURE 11-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF FIGURE 11-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF 5.5 1.8 R = 3.3k R = 3.3k 5.0 1.6 4.5 1.4 R = 5k 3.5 FOSC (MHz) R = 5k 1.2 FOSC (MHz) 4.0 3.0 1.0 0.8 R = 10k R = 10k 2.5 0.6 2.0 0.4 Measured on DIP Packages, T = 25C Measured on DIP Packages, T = 25C 0.2 1.5 R = 100k 0.0 3.0 1.0 4.0 4.5 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 5.0 5.5 6.0 VDD (Volts) R = 100k 0.5 0.0 3.0 3.5 6.0 FIGURE 11-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF 800 700 R = 3.3k 600 R = 5k FOSC (kHz) 500 400 R = 10k 300 200 Measured on DIP Packages, T = 25C 100 R = 100k 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30453C-page 74 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 11-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED FIGURE 11-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED 2.5 20 18 2.0 16 14 T = 25C T = 25C 12 IPD (A) IPD (A) 1.5 1.0 10 8 6 0.5 4 2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 11-6: MAXIMUM IPD vs. VDD, WATCHDOG DISABLED 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 11-8: MAXIMUM IPD vs. VDD, WATCHDOG ENABLED 60 100 50 +125C 10 +85C 40 -55C +70C IPD (A) 0C +85C 30 1 IPD (A) -40C -55C +125C -40C +70C 20 0C 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (Volts) 0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 6.0 6.5 7.0 IPD, with WDT enabled, has two components: The leakage current, which increases with higher temperature, and the operating current of the WDT logic, which increases with lower temperature. At -40C, the latter dominates explaining the apparently anomalous behavior. 2000 Microchip Technology Inc. Preliminary DS30453C-page 75 PIC16C5X PIC16C54/55/56/57 FIGURE 11-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD 2.00 1.80 to -40C Max ( VTH (Volts) 1.60 1.40 +85C 2 Typ (+ ) 5C) 1.20 1.00 4 Min (- 0.80 0.60 2.5 3.0 3.5 0C to +85C 4.0 4.5 VDD (Volts) ) 5.5 5.0 6.0 FIGURE 11-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD 4.5 4.0 3.5 VIH, VIL (Volts) VIH ( max C to -40 C) +85 5C p +2 y t 5 C ) VIH to +8 C (-40 m in VIH 3.0 2.5 2.0 to +85C) VIL max (-40C VIH typ +25C 1.5 1.0 0.5 VIL min (-40C to +8 5C) 0.0 2.5 3.0 3.5 4.0 Note: These input pins have Schmitt Trigger input buffers. 4.5 VDD (Volts) 5.0 5.5 6.0 5.5 6.0 FIGURE 11-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD 3.4 3.2 3.0 ) 5C o +8 t C (-40 Max C) (+25 p y T 2.8 VTH (Volts) 2.6 2.4 2.2 2.0 Min 1.8 C) +85 o t C (-40 1.6 1.4 1.2 1.0 2.5 DS30453C-page 76 3.0 3.5 4.0 4.5 VDD (Volts) Preliminary 5.0 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 11-12: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK, 25C) 10 IDD (mA) 1.0 0.1 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10k 100k 1M External Clock Frequency (Hz) 10M 100M FIGURE 11-13: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK, -40C TO +85C) 10 IDD (mA) 1.0 0.1 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10k 100k 1M 10M 100M External Clock Frequency (Hz) 2000 Microchip Technology Inc. Preliminary DS30453C-page 77 PIC16C5X PIC16C54/55/56/57 FIGURE 11-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK -55C TO +125C) 10 IDD (mA) 1.0 0.1 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10k 100k 1M External Clock Frequency (Hz) FIGURE 11-15: WDT TIMER TIME-OUT PERIOD vs. VDD 10M 100M FIGURE 11-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD 50 9000 45 8000 40 7000 35 6000 30 gm (A/V) WDT period (ms) Max -40C Max +85C 25 5000 Typ +25C 4000 Max +70C 20 3000 Typ +25C Min +85C 15 2000 MIn 0C 10 100 MIn -40C 5 0 2 3 4 5 6 7 2 VDD (Volts) DS30453C-page 78 3 4 5 6 7 VDD (Volts) Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 11-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD FIGURE 11-19: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 45 2500 40 Max -40C Max -40C 2000 35 30 gm (A/V) gm (A/V) 1500 25 Typ +25C 20 Typ +25C 1000 15 Min +85C 500 10 Min +85C 5 0 2 0 2 3 4 5 6 3 7 4 5 6 7 VDD (Volts) VDD (Volts) FIGURE 11-18: IOH vs. VOH, VDD = 3 V FIGURE 11-20: IOH vs. VOH, VDD = 5 V 0 0 Min +85C -5 -10 -10 IOH (mA) IOH (mA) Min +85C Typ +25C -20 Typ +25C -15 Max -40C -30 Max -40C -20 -40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (Volts) 2000 Microchip Technology Inc. Preliminary VOH (Volts) DS30453C-page 79 PIC16C5X PIC16C54/55/56/57 FIGURE 11-21: IOL vs. VOL, VDD = 3 V FIGURE 11-22: IOL vs. VOL, VDD = 5 V 90 45 Max -40C 40 Max -40C 80 35 70 30 60 25 50 IOL (mA) IOL (mA) Typ +25C Typ +25C 20 40 Min +85C 30 15 Min +85C 10 20 5 10 0 0.0 0.5 1.0 1.5 2.0 2.5 0 0.0 3.0 0.5 TABLE 11-2: INPUT CAPACITANCE FOR PIC16C54/56 TABLE 11-3: 1.5 2.0 2.5 3.0 INPUT CAPACITANCE FOR PIC16C55/57 Typical Capacitance (pF) Typical Capacitance (pF) Pin 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. DS30453C-page 80 1.0 VOL (Volts) VOL (Volts) Pin 28L PDIP (600 mil) 28L SOIC RA port 5.2 4.8 RB port 5.6 4.7 RC port 5.0 4.1 MCLR 17.0 17.0 OSC1 6.6 3.5 OSC2/CLKOUT 4.6 3.5 T0CKI 4.5 3.5 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16CR54A 12.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A Absolute Maximum Ratings Ambient Temperature under bias ........................................................................................................... -55C to +125C Storage Temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS(2) ............................................................................................................0 to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.6V to (VDD + 0.6V) Total Power Dissipation(1) ....................................................................................................................................800 mW Max. Current out of VSS pin ..................................................................................................................................150 mA Max. Current into VDD pin .......................................................................................................................................50 mA Max. Current into an input pin (T0CKI only) ....................................................................................................................500 A Input Clamp Current, IIK (VI < 0 or VI > VDD) ................................................................................................................... 20 mA Output Clamp Current, IOK (V0 < 0 or V0 > VDD)............................................................................................................. 20 mA Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................20 mA Max. Output Current sourced by a single I/O port (PORTA or B) ...........................................................................40 mA Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................50 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss. NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2000 Microchip Technology Inc. Preliminary DS30453C-page 81 PIC16C5X 12.1 PIC16CR54A DC Characteristics: PIC16CR54A-04, 10, 20 (Commercial) PIC16CR54A-04I, 10I, 20I (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) DC Characteristics Power Supply Pins Characteristic Sym Min Typ(1) Max Units 6.25 5.5 V V Conditions Supply Voltage RC and XT options HS option VDD RAM Data Retention Voltage(2) VDR -- 1.5* -- V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD Rise Rate to ensure Power-on Reset SVDD 0.05* -- -- V/ms See Section 7.4 for details on Power-on Reset 2.0 0.8 90 4.8 9.0 3.6 1.8 350 10 20 mA mA A mA mA FOSC = 4.0 MHz, VDD = 6.0V FOSC = 4.0 MHz, VDD = 3.0V FOSC = 200 kHz, VDD = 2.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V 1.0 2.0 3.0 5.0 6.0 8.0* 15 25 A A A A VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled 1.0 2.0 3.0 3.0 5.0 8.0 10* 20* 18 45 A A A A A VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 4.0V, WDT enabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled Supply Current(3) RC(4) and XT options 2.5 4.5 IDD HS option Power-down Current(5) Commercial Power-down Current(5) Industrial IPD IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30453C-page 82 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16CR54A 12.2 DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended) DC Characteristics Power Supply Pins Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) Min Typ(1) Max Units 3.25 4.5 -- -- 6.0 5.5 V V VDR -- 1.5* -- V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD Rise Rate to ensure Power-on Reset SVDD 0.05* -- -- V/ms See Section 7.4 for details on Power-on Reset -- -- -- 1.8 4.8 9.0 3.3 10 20 mA mA mA FOSC = 4.0 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 16 MHz, VDD = 5.5V -- -- 5.0 0.8 22 18 A A VDD = 3.25V, WDT enabled VDD = 3.25V, WDT disabled Characteristic Sym Supply Voltage RC, XT and LP options HS options VDD RAM Data Retention Voltage(2) Supply Current(3) RC(4) and XT options HS option IDD Power-down Current(5) IPD Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 2000 Microchip Technology Inc. Preliminary DS30453C-page 83 PIC16C5X 12.3 PIC16CR54A DC Characteristics: PIC16LCR54A-04 (Commercial) PIC16LCR54A-04I (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) DC Characteristics Power Supply Pins Sym Min Typ(1) Max Units Supply Voltage VDD 2.0 -- 6.25 V LP Option RAM Data Retention Voltage(2) VDR -- 1.5* -- V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD Rise Rate to ensure Power-on Reset SVDD 0.05* -- -- V/ms See Section 7.4 for details on Power-on Reset IDD -- 10 20 70 A A FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 6.0V -- -- -- -- 1.0 2.0 3.0 5.0 6.0 8.0* 15 25 A A A A VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled -- -- -- -- -- 1.0 2.0 3.0 3.0 5.0 8.0 10* 20* 18 45 A A A A A VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 4.0V, WDT enabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled Characteristic Supply Current(3) Power-down Current(5) Commercial Power-down Current(5) Industrial Conditions IPD IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30453C-page 84 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16CR54A 12.4 DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial) PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating Voltage VDD range is described in Section 12.1 and Section 12.3. DC Characteristics All Pins Except Power Supply Pins Characteristic Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 VIL Input High Voltage I/O ports VIH MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs Input Leakage Current(3) I/O ports VHYS Min Typ(1) VSS VSS VSS VSS VSS -- -- -- -- -- 2.0 0.6 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.85 VDD -- -- -- -- -- -- 0.15VDD* -- Max 0.2 0.15 0.15 0.15 0.15 VDD VDD VDD VDD VDD Units V V V V V Pin at hi-impedance VDD VDD VDD VDD VDD VDD V V V V V V VDD = 3.0V to 5.5V(5) Full VDD range(5) -- V +1.0 A -3.0 -3.0 0.5 0.5 0.5 +5.0 +3.0 +3.0 A A A A -- -- -- -- 0.5 0.5 V V IOL = 10 mA, VDD = 6.0V IOL = 1.9 mA, VDD = 6.0V, RC option only VDD -0.5 VDD -0.5 -- -- -- -- V V IOH = -4.0 mA, VDD = 6.0V IOH = -0.8 mA, VDD = 6.0V, RC option only IIL -1.0 -5.0 MCLR T0CKI OSC1 Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage(3) I/O ports OSC2/CLKOUT VOH Conditions RC option only(4) XT, HS and LP options RC option only(4) XT, HS and LP options For VDD 5.5V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V(2) VPIN = VDD(2) VSS VPIN VDD VSS VPIN VDD, XT, HS and LP options * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. 2000 Microchip Technology Inc. Preliminary DS30453C-page 85 PIC16C5X 12.5 PIC16CR54A DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended) DC Characteristics All Pins Except Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C Operating Voltage VDD range is described in Section 12.2. Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 VIL Input High Voltage I/O ports VIH MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs Input Leakage Current(3) I/O ports VHYS Min Typ(1) Max Units Vss Vss Vss Vss Vss -- -- -- -- -- 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V V Pin at hi-impedance 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD -- -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD VDD V V V V V V V For all VDD(5) 4.0V < VDD 5.5V(5) VDD > 5.5V 0.15VDD* -- -- V -1.0 0.5 +1.0 A -3.0 -3.0 0.5 0.5 0.5 +5.0 +3.0 +3.0 A A A A -- -- -- -- 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, RC option only VDD -0.7 VDD -0.7 -- -- -- -- V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, RC option only IIL -5.0 MCLR T0CKI OSC1 Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage (3) I/O ports OSC2/CLKOUT VOH Conditions RC option only(4) XT, HS and LP options RC option only(4) XT, HS and LP options For VDD 5.5V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V(2) VPIN = VDD(2) VSS VPIN VDD VSS VPIN VDD, XT, HS and LP options * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. DS30453C-page 86 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16CR54A 12.6 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 12-1: LOAD CONDITIONS Pin CL = 50 pF for all pins except OSC2 CL VSS 2000 Microchip Technology Inc. 15 pF for OSC2 in XT, HS or LP options when external clock is used to drive OSC1 Preliminary DS30453C-page 87 PIC16C5X 12.7 PIC16CR54A Timing Diagrams and Specifications FIGURE 12-2: EXTERNAL CLOCK TIMING - PIC16CR54A Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A AC Characteristics Parameter No. Sym FOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3. Characteristic External CLKIN Frequency(2) Oscillator Frequency(2) Min Typ(1) DC -- 4.0 MHz XT osc mode DC -- 4.0 MHz HS osc mode (04) DC -- 10 MHz HS osc mode (10) DC -- 20 MHz HS osc mode (20) DC -- 200 kHz DC -- 4.0 MHz RC osc mode 0.1 -- 4.0 MHz XT osc mode 4.0 -- 4.0 MHz HS osc mode (04) 4.0 -- 10 MHz HS osc mode (10) 4.0 -- 20 MHz HS osc mode (20) 5.0 -- 200 kHz Max Units Conditions LP osc mode LP osc mode * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS30453C-page 88 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16CR54A TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A (CON'T) AC Characteristics Parameter No. Sym 1 TOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3. Characteristic External CLKIN Period(2) Oscillator Period(2) 2 TCY (3) Instruction Cycle Time Min Typ(1) 250 -- -- ns XT osc mode 250 -- -- ns HS osc mode (04) 100 -- -- ns HS osc mode (10) 50 -- -- ns HS osc mode (20) 5.0 -- -- s LP osc mode 250 -- -- ns RC osc mode 250 -- 10,00 0 ns XT osc mode 250 -- 250 ns HS osc mode (04) 100 -- 250 ns HS osc mode (10) 50 -- 250 ns HS osc mode (20) 5.0 -- 200 s LP osc mode -- 4/FOS -- -- Max Units Conditions C 3 4 TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time 50* -- -- ns XT oscillator 20* -- -- ns HS oscillator 2.0* -- -- s LP oscillator -- -- 25* ns XT oscillator -- -- 25* ns HS oscillator -- -- 50* ns LP oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. 2000 Microchip Technology Inc. Preliminary DS30453C-page 89 PIC16C5X PIC16CR54A FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16CR54A Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 12 18 16 14 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 12-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A AC Characteristics Parameter No. Sym Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3. Characteristic Min Typ(1) Max Units 10 TosH2ckL OSC1 to CLKOUT(2) -- 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(2) -- 15 30** ns 12 TckR CLKOUT rise time(2) -- 5.0 15** ns 13 TckF CLKOUT fall time(2) -- 5.0 15** ns 14 TckL2ioV CLKOUT to Port out valid(2) -- -- 40** ns 15 TioV2ckH Port in valid before CLKOUT(2) 0.25 TCY+30* -- -- ns 16 TckH2ioI Port in hold after CLKOUT(2) 0* -- -- ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(3) -- -- 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) TBD -- -- ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) TBD -- -- ns 20 TioR Port output rise time(3) -- 10 25** ns 21 TioF Port output fall time(3) -- 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 3: See Figure 12-1 for loading conditions. DS30453C-page 90 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16CR54A FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. TABLE 12-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3. Parameter No. Sym Characteristic Min Typ(1) Max Units 30 TmcL MCLR Pulse Width (low) 1.0* -- -- s VDD = 5.0V 31 Twdt Watchdog Timer Time-out Period (No Prescaler) 7.0* 18* 40* ms VDD = 5.0V (Commercial) 32 TDRT Device Reset Timer Period 7.0* 18* 30* ms VDD = 5.0V (Commercial) 34 TioZ I/O Hi-impedance from MCLR Low -- -- 1.0* s Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. Preliminary DS30453C-page 91 PIC16C5X PIC16CR54A FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16CR54A T0CKI 40 41 42 TABLE 12-4: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A AC Characteristics Param No. 40 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3. Sym Characteristic Min Tt0H T0CKI High Pulse Width - No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width - No Prescaler - With Prescaler 42 Tt0P T0CKI Period Typ(1) Max Units Conditions 0.5 TCY + 20* -- -- ns 10* -- -- ns 0.5 TCY + 20* -- -- ns 10* -- -- ns 20 or TCY + 40* N -- -- ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30453C-page 92 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A 13.0 ELECTRICAL CHARACTERISTICS - PIC16C54A Absolute Maximum Ratings Ambient temperature under bias............................................................................................................ -55C to +125C Storage temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS ...............................................................................................................0 to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.6V to (VDD + 0.6V) Total power dissipation(1) .....................................................................................................................................800 mW Max. current out of VSS pin ...................................................................................................................................150 mA Max. current into VDD pin ......................................................................................................................................100 mA Max. current into an input pin (T0CKI only) .....................................................................................................................500 A Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Max. output current sunk by any I/O pin .................................................................................................................25 mA Max. output current sourced by any I/O pin ............................................................................................................20 mA Max. output current sourced by a single I/O port (PORTA or B) .............................................................................50 mA Max. output current sunk by a single I/O port (PORTA or B) ..................................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2000 Microchip Technology Inc. Preliminary DS30453C-page 93 PIC16C5X 13.1 PIC16C54A DC Characteristics: PIC16C54A-04, 10, 20 (Commercial) PIC16C54A-04I, 10I, 20I (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) DC Characteristics Power Supply Pins Characteristic Sym Supply Voltage XT, RC and LP options HS option VDD RAM Data Retention Voltage(2) Min Typ(1) Max Units Conditions 3.0 4.5 -- -- 6.25 5.5 V V VDR -- 1.5* -- V Device in SLEEP mode VDD start voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD rise rate to ensure Power-on Reset SVDD 0.05* -- -- Supply Current(3) XT and RC(4) options HS option IDD -- -- -- -- -- 1.8 2.4 4.5 14 17 2.4 8.0 16 29 37 mA mA mA A A FOSC = 4.0 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.0V, WDT disabled FOSC = 32 kHz, VDD = 3.0V, WDT disabled -- -- -- -- 4.0 0.25 5.0 0.3 12 4.0 14 5.0 A A A A VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled LP option, Commercial LP option, Industrial Power-down Current(5) Commercial Industrial V/ms See Section 7.4 for details on Power-on Reset IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30453C-page 94 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A 13.2 DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) Sym Supply Voltage XT and RC options HS option VDD RAM Data Retention Voltage(2) Min Typ(1) Max Units Conditions 3.5 4.5 -- -- 5.5 5.5 V V VDR -- 1.5* -- V Device in SLEEP mode VDD start voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD rise rate to ensure Power-on Reset SVDD 0.05* -- -- Supply Current(3) XT and RC(4) options HS option IDD -- -- -- 1.8 4.8 9.0 3.3 10 20 mA mA mA FOSC = 4.0 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V Power-down Current(5) XT and RC options IPD -- -- -- -- 5.0 0.8 4.0 0.25 22 18 22 18 A A A A VDD = 3.5V, WDT enabled VDD = 3.5V, WDT disabled VDD = 3.5V, WDT enabled VDD = 3.5V, WDT disabled HS option V/ms See Section 7.4 for details on Power-on Reset * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 2000 Microchip Technology Inc. Preliminary DS30453C-page 95 PIC16C5X 13.3 PIC16C54A DC Characteristics: PIC16LC54A-04 (Commercial) PIC16LC54A-04I (Industrial)) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) DC Characteristics Power Supply Pins Characteristic Sym Supply Voltage XT and RC options LP options VDD RAM Data Retention Voltage(2) Min Typ(1) Max Units Conditions 3.0 2.5 -- -- 6.25 6.25 V V VDR -- 1.5* -- V Device in SLEEP mode VDD start voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD rise rate to ensure Power-on Reset SVDD 0.05* -- -- Supply Current(3) XT and RC(4) options LP option, Commercial LP option, Industrial LP option, Extended IDD -- -- -- -- 0.5 11 11 11 2.5 27 35 37 mA A A A FOSC = 4.0 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 2.5V WDT disabled FOSC = 32 kHz, VDD = 2.5V WDT disabled FOSC = 32 kHz, VDD = 2.5V WDT disabled Power-down Current(5) Commercial IPD -- -- -- -- -- -- 2.5 0.25 2.5 0.25 2.5 0.25 12 4.0 14 5.0 15 7.0 A A A A A A VDD = 2.5V, WDT enabled VDD = 2.5V, WDT disabled VDD = 2.5V, WDT enabled VDD = 2.5V, WDT disabled VDD = 2.5V, WDT enabled VDD = 2.5V, WDT disabled Industrial Extended V/ms See Section 7.4 for details on Power-on Reset * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30453C-page 96 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A 13.4 DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial) PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial) PIC16C54A-04E, 10E, 20E (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -20C TA +85C (industrial - PIC16LV54A-02I) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3. DC Characteristics All Pins Except Power Supply Pins Min Typ(1) Max Units VSS VSS VSS VSS VSS -- -- -- -- -- 0.2 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V Pin at hi-impedance 0.2 VDD+1V 2.0 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD V V V V V V For all VDD(5) 4.0V < VDD 5.5V(5) 0.15VDD* -- -- V MCLR -1.0 -- -5.0 T0CKI OSC1 -3.0 -3.0 0.5 -- -- 0.5 0.5 0.5 +1.0 -- +5.0 +3.0 +3.0 -- A -- A A A A -- -- -- -- 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, RC option only VDD-0.7 VDD-0.7 -- -- -- -- V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, RC option only Characteristic Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 VIL Input High Voltage I/O ports VIH MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs VHYS Input Leakage Current(3) I/O ports IIL Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage I/O ports(3) OSC2/CLKOUT VOH Conditions RC option only(4) XT, HS and LP options RC option only(4) XT, HS and LP options For VDD 5.5V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS +0.25V(2) VPIN = VDD(2) VSS VPIN VDD VSS VPIN VDD, XT, HS and LP options * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. 2000 Microchip Technology Inc. Preliminary DS30453C-page 97 PIC16C5X 13.5 PIC16C54A Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low T Time mc osc os t0 wdt MCLR oscillator OSC1 T0CKI watchdog timer P R V Z Period Rise Valid Hi-impedance FIGURE 13-1: LOAD CONDITIONS - PIC16C54A Pin CL = 50 pF for all pins except OSC2 CL VSS DS30453C-page 98 15 pF for OSC2 in XT, HS or LP options when external clock is used to drive OSC1 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A 13.6 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC16C54A Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A AC Characteristics Parameter No. Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -20C TA +85C (industrial - PIC16LV54A-02I) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3. Sym Characteristic Min Typ(1) FOSC External CLKIN Frequency(2) DC -- 4.0 MHz XT osc mode DC -- 2.0 MHz XT osc mode (PIC16LV54A) DC -- 4.0 MHz HS osc mode (04) DC -- 10 MHz HS osc mode (10) DC -- 20 MHz HS osc mode (20) DC -- 200 kHz DC -- 4.0 MHz RC osc mode DC -- 2.0 MHz RC osc mode (PIC16LV54A) 0.1 -- 4.0 MHz XT osc mode 0.1 -- 2.0 MHz XT osc mode (PIC16LV54A) 4 -- 4.0 MHz HS osc mode (04) 4 -- 10 MHz HS osc mode (10) 4 -- 20 MHz HS osc mode (20) 5 -- 200 kHz Oscillator Frequency(2) Max Units Conditions LP osc mode LP osc mode * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. 2000 Microchip Technology Inc. Preliminary DS30453C-page 99 PIC16C5X TABLE 13-1: PIC16C54A EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A (CON'T) AC Characteristics Parameter No. Sym 1 TOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -20C TA +85C (industrial - PIC16LV54A-02I) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3. Characteristic External CLKIN Period(2) Oscillator 2 TCY Period(2) (3) Instruction Cycle Time Min Typ(1) 250 -- -- ns XT osc mode 500 -- -- ns XT osc mode (PIC16LV54A) 250 -- -- ns HS osc mode (04) 100 -- -- ns HS osc mode (10) 50 -- -- ns HS osc mode (20) 5.0 -- -- s LP osc mode 250 -- -- ns RC osc mode 500 -- -- ns RC osc mode (PIC16LV54A) 250 -- 10,00 0 ns XT osc mode 500 -- -- ns XT osc mode (PIC16LV54A) 250 -- 250 ns HS osc mode (04) 100 -- 250 ns HS osc mode (10) 50 -- 250 ns HS osc mode (20) 5.0 -- 200 s LP osc mode -- 4/FOS -- -- Max Units Conditions C 3 4 TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time 85* -- -- ns XT oscillator 20* -- -- ns HS oscillator 2.0* -- -- s LP oscillator -- -- 25* ns XT oscillator -- -- 25* ns HS oscillator -- -- 50* ns LP oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS30453C-page 100 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A FIGURE 13-3: CLKOUT AND I/O TIMING - PIC16C54A Q1 Q4 Q2 Q3 OSC1 10 11 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A AC Characteristics Parameter No. Sym Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -20C TA +85C (industrial - PIC16LV54A-02I) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3. Characteristic Min Typ(1) Max Units 10 TosH2ckL OSC1 to CLKOUT(2) -- 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(2) -- 15 30** ns 12 TckR CLKOUT rise time(2) -- 5.0 15** ns 13 TckF CLKOUT fall time(2) -- 5.0 15** ns 14 TckL2ioV CLKOUT to Port out valid(2) -- -- 40** ns 15 TioV2ckH Port in valid before CLKOUT(2) 0.25 TCY+30* -- -- ns 16 TckH2ioI Port in hold after CLKOUT(2) 0* -- -- ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(3) -- -- 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) TBD -- -- ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) TBD -- -- ns 20 TioR Port output rise time(3) -- 10 25** ns -- 10 25** ns 21 TioF (3) Port output fall time * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 3: See Figure 14-1 for loading conditions. 2000 Microchip Technology Inc. Preliminary DS30453C-page 101 PIC16C5X PIC16C54A FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54A VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. TABLE 13-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -20C TA +85C (industrial - PIC16LV54A-02I) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3. Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions 30 TmcL MCLR Pulse Width (low) 100* 1s -- -- -- -- ns -- VDD = 5.0V VDD = 5.0V (PIC16LV54A only) 31 Twdt Watchdog Timer Time-out Period (No Prescaler) 9.0* 18* 30* ms VDD = 5.0V (Commercial) 32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Commercial) 34 TioZ I/O Hi-impedance from MCLR Low -- -- -- -- 100* 1s ns -- (PIC16LV54A only) * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30453C-page 102 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC16C54A T0CKI 40 41 42 TABLE 13-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54A AC Characteristics Param No. 40 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -20C TA +85C (industrial - PIC16LV54A-02I) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3. Sym Characteristic Min Tt0H T0CKI High Pulse Width - No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width - No Prescaler - With Prescaler 42 Tt0P T0CKI Period Typ(1) Max Units Conditions 0.5 TCY + 20* -- -- ns 10* -- -- ns 0.5 TCY + 20* -- -- ns 10* -- -- ns 20 or TCY + 40* N -- -- ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. Preliminary DS30453C-page 103 PIC16C5X PIC16C54A NOTES: DS30453C-page 104 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A 14.0 DC AND AC CHARACTERISTICS - PIC16C54A The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution, while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation. FIGURE 14-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC FOSC (25C) Frequency normalized to +25C 1.10 REXT 10 k CEXT = 100 pF 1.08 1.06 1.04 1.02 1.00 0.98 VDD = 5.5 V 0.96 0.94 VDD = 3.5 V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 14-1: RC OSCILLATOR FREQUENCIES CEXT Average Fosc @ 5 V, 25C REXT 20 pF 3.3 k 5k 10 k 100 k 100 pF 3.3 k 5k 10 k 100 k 300 pF 3.3 k 5.0 k 10 k 160 k The frequencies are measured on DIP packages. 4.973 MHz 3.82 MHz 2.22 MHz 262.15 kHz 1.63 MHz 1.19 MHz 684.64 kHz 71.56 kHz 660 kHz 484.1 kHz 267.63 kHz 29.44 kHz 27% 21% 21% 31% 13% 13% 18% 25% 10% 14% 15% 19% The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5 V. 2000 Microchip Technology Inc. Preliminary DS30453C-page 105 PIC16C5X PIC16C54A FIGURE 14-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF 6.00 R=3.3K 5.00 R=5.0K FOSC (MHz) 4.00 3.00 R=10K 2.00 CEXT=20pF, T=25C 1.00 R=100K 0.00 2.5 3 3.5 4 4.5 5 5.5 6 VDD (Volts) FIGURE 14-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF 1.80 R=3.3K 1.60 1.40 R=5.0K FOSC (MHz) 1.20 1.00 0.80 R=10K 0.60 CEXT=100pF, T=25C 0.40 0.20 R=100K 0.00 2.5 3 3.5 4 4.5 5 5.5 6 VDD (Volts) DS30453C-page 106 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A FIGURE 14-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF 700.00 R=3.3K 600.00 500.00 R=5.0K FOSC (kHz) 400.00 300.00 R=10K 200.00 CEXT=300pF, T=25C 100.00 R=100K 0.00 2.5 3 3.5 4 4.5 6 5.5 5 VDD (Volts) FIGURE 14-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C) 2.50 2.00 IPD (A) 1.50 1.00 0.50 0 2.5 3.0 2000 Microchip Technology Inc. 3.5 4.0 4.5 VDD (Volts) Preliminary 5.0 5.5 6.0 DS30453C-page 107 PIC16C5X PIC16C54A FIGURE 14-6: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD 2.00 1.80 to -40C Max ( VTH (Volts) 1.60 1.40 ) +85C 25 Typ (+ C) 1.20 1.00 40 Min (- 0.80 0.60 2.5 3.0 3.5 C to + 85C) 4.0 4.5 VDD (Volts) 5.5 5.0 6.0 FIGURE 14-7: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD 4.5 4.0 3.5 VIH, VIL (Volts) VIH max ( C to -40 C) +85 5C p +2 y t 5C) VIH to + 8 C 0 (-4 m in VIH 3.0 2.5 2.0 C to +85C) VIL max (-40 VIH typ +25C 1.5 1.0 5C) VIL min (-40C to +8 0.5 0.0 2.5 3.0 3.5 4.0 Note: These input pins have Schmitt Trigger input buffers. 4.5 VDD (Volts) 5.0 5.5 6.0 5.5 6.0 FIGURE 14-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD 3.4 3.2 3.0 C) +85 o t C (-40 C) Max (+25 Typ 2.8 VTH (Volts) 2.6 2.4 2.2 2.0 1.8 M ) 5C o +8 t C 40 in (- 1.6 1.4 1.2 1.0 2.5 DS30453C-page 108 3.0 3.5 4.0 4.5 VDD (Volts) Preliminary 5.0 2000 Microchip Technology Inc. PIC16C5X PIC16C54A FIGURE 14-9: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, 25C) 10000 IDD (A) 1000 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 100 10 0.1 1 10 Freq (MHz) FIGURE 14-10: MAXIMUM IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, -40C TO +85C) 10000 IDD (A) 1000 100 10 0.1 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 1 10 Freq (MHz) 2000 Microchip Technology Inc. Preliminary DS30453C-page 109 PIC16C5X PIC16C54A FIGURE 14-11: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, 25C) 10000 IDD (A) 1000 100 10 0.01 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 1 0.1 10 Freq (MHz) FIGURE 14-12: MAXIMUM IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, -40C TO +85C) 10000 IDD (A) 1000 100 10 0.01 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 0.1 1 10 Freq (MHz) DS30453C-page 110 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A FIGURE 14-13: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, 25C) 10000 IDD (A) 1000 100 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 10 0.01 0.1 1 Freq (MHz) FIGURE 14-14: MAXIMUM IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, -40C TO +85C) 10000 IDD (A) 1000 100 10 0.01 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 0.1 1 Freq (MHz) 2000 Microchip Technology Inc. Preliminary DS30453C-page 111 PIC16C5X PIC16C54A FIGURE 14-15: WDT TIMER TIME-OUT PERIOD vs. VDD TABLE 14-2: Typical Capacitance (pF) 50 Pin 45 40 35 WDT period (ms) INPUT CAPACITANCE FOR PIC16C54A/C58A 30 Max +85C 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. 25 Max +70C 20 Typ +25C 15 MIn 0C 10 MIn -40C 5 2 3 4 5 6 7 VDD (Volts) DS30453C-page 112 Preliminary 2000 Microchip Technology Inc. PIC16C5X PIC16C54A FIGURE 14-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD FIGURE 14-18: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 2500 9000 8000 Max -40C Max -40C 2000 7000 1500 5000 gm (A/V) gm (A/V) 6000 Typ +25C 4000 Typ +25C 1000 3000 Min +85C 500 Min +85C 2000 100 0 2 0 2 3 4 5 6 3 4 5 6 7 VDD (Volts) 7 VDD (Volts) FIGURE 14-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD 45 40 Max -40C 35 gm (A/V) 30 25 Typ +25C 20 15 10 Min +85C 5 0 2 3 4 5 6 7 VDD (Volts) 2000 Microchip Technology Inc. Preliminary DS30453C-page 113 PIC16C5X PIC16C54A FIGURE 14-19: IOH vs. VOH, VDD = 3 V FIGURE 14-21: IOL vs. VOL, VDD = 3 V 0 45 Max -40C 40 -5 35 Min +85C IOL (mA) IOH (mA) 30 -10 Typ +25C -15 Max -40C 25 Typ +25C 20 15 Min +85C -20 10 5 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 VOH (Volts) FIGURE 14-20: IOH vs. VOH, VDD = 5 V 0.5 1.0 1.5 2.0 VOL (Volts) 2.5 3.0 FIGURE 14-22: IOL vs. VOL, VDD = 5 V 90 0 Max -40C 80 Min +85C 70 -10 Typ +25C -20 IOL (mA) IOH (mA) 60 Typ +25C 50 40 Min +85C 30 -30 Max -40C 20 -40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 VOH (Volts) 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) DS30453C-page 114 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B 15.0 ELECTRICAL CHARACTERISTICS PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B Absolute Maximum Ratings Ambient temperature under bias............................................................................................................ -55C to +125C Storage temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS ...............................................................................................................0 to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.6V to (VDD + 0.6V) Total power dissipation(1) .....................................................................................................................................800 mW Max. current out of VSS pin ...................................................................................................................................150 mA Max. current into VDD pin ......................................................................................................................................100 mA Max. current into an input pin (T0CKI only) .....................................................................................................................500 A Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Max. output current sunk by any I/O pin .................................................................................................................25 mA Max. output current sourced by any I/O pin ............................................................................................................20 mA Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA Max. output current sunk by a single I/O (Port A, B or C) .......................................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2000 Microchip Technology Inc. Preliminary DS30453C-page 115 PIC16C5X FIGURE 15-1: PIC16C54C VOLTAGE-FREQUENCY GRAPH, 0C TA +70C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 15-2: PIC16C54C VOLTAGE-FREQUENCY GRAPH, -40C TA < 0C, +70C < TA +125C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) 20 25 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. DS30453C-page 116 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B 15.1 DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial) PIC16C54C/C55A/C56A/C57C/C58B-04I, 20I (Industrial) PIC16CR54B/CR/54C/CR56A/CR57C/CR58B-04I, 20I (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) DC Characteristics Power Supply Pins Characteristic Sym Supply Voltage XT, RC, LP and HS options HS option VDD RAM Data Retention Voltage(2) Min Typ(1) Max Units Conditions 3.0 4.5 -- -- 5.5 5.5 V V HS Option from 0 - 10MHz HS Option from 0 - 20MHz VDR -- 1.5* -- V Device in SLEEP mode VDD start voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD rise rate to ensure Power-on Reset SVDD 0.05* -- -- Supply Current(3)(4) IDD -- -- -- -- 1.8 2.6 4.5 14 2.4 3.6 16 32 mA mA mA A -- 17 40 A V/ms See Section 7.4 for details on Power-on Reset FOSC = 4 MHz, VDD = 5.5V, XT mode FOSC = 10 MHz, VDD = 3.0V, HS mode FOSC = 20 MHz, VDD = 5.5V, HS mode FOSC = 32 kHz, VDD = 3.0V, LP mode, Commercial FOSC = 32 kHz, VDD = 3.0V, LP mode, Industrial Power-down Current(5) IPD -- -- -- -- 0.25 0.25 1.8 2.0 4.0 5.0 7.0 8.0 A A A A VDD = 3.0V, WDT disabled, Commercial VDD = 3.0V, WDT disabled, Industrial VDD = 5.5V, WDT disabled, Commercial VDD = 5.5V, WDT disabled, Industrial Watchdog Timer Current IWDT -- -- -- -- 3.75 3.75 8 10 8.0 9.0 20 22 A A A A VDD = 3.0V, Commercial VDD = 3.0V, Industrial VDD = 5.5V*, Commercial VDD = 5.5V*, Industrial * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 2000 Microchip Technology Inc. Preliminary DS30453C-page 117 PIC16C5X 15.2 DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E (Extended) PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) Sym Supply Voltage XT, RC, LP and HS options HS option VDD RAM Data Retention Voltage(2) Min Typ(1) Max Units Conditions 3.0 4.5 -- -- 5.5 5.5 V V HS Option from 0 - 10MHz HS Option from 0 - 20MHz VDR -- 1.5* -- V Device in SLEEP mode VDD start voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD rise rate to ensure Power-on Reset SVDD 0.05* -- -- Supply Current(3) XT and RC(4) options HS option IDD -- -- 1.8 9.0 3.3 20 mA mA FOSC = 4.0 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V Power-down Current(5) IPD -- -- -- 0.3 10 12 17 50 60 A A A VDD = 3.0V, WDT disabled VDD = 4.5V, WDT disabled VDD = 5.5V, WDT disabled Watchdog Timer Current IWDT -- -- 4.5 8 14 14 18 30 A A A VDD = 3.0V VDD = 4.5V* VDD = 5.5V* V/ms See Section 7.4 for details on Power-on Reset * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30453C-page 118 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B 15.3 DC Characteristics: PIC16LC5X-04, PIC16LCR5X-04 (Commercial) PIC16LC5X-04I, PIC16LCR5X-04I (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) DC Characteristics Power Supply Pins Characteristic Sym Supply Voltage XT and RC options LP options VDD RAM Data Retention Voltage(2) Min Typ(1) Max Units Conditions 3.0 2.5 -- -- 5.5 5.5 V V VDR -- 1.5* -- V Device in SLEEP mode VDD start voltage to ensure Power-on Reset VPOR -- VSS -- V See Section 7.4 for details on Power-on Reset VDD rise rate to ensure Power-on Reset SVDD 0.05* -- -- Supply Current(3)(4) IDD -- -- -- 0.4 0.5 11 0.6 2.4 27 mA mA A -- 14 35 A V/ms See Section 7.4 for details on Power-on Reset FOSC = 4.0 MHz, VDD = 2.5V, XT mode FOSC = 4.0 MHz, VDD = 5.5V, XT mode FOSC = 32 kHz, VDD = 2.5V, LP mode, Commercial FOSC = 32 kHz, VDD = 2.5V, LP mode, Industrial Power-down Current(5) IPD -- -- 0.25 0.25 2 3 A A VDD = 2.5V, WDT disabled, Commercial VDD = 2.5V, WDT disabled, Industrial Watchdog Timer Current IWDT -- -- 0.8 1 3 5 A A VDD = 2.5V, Commercial VDD = 2.5V, Industrial * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 2000 Microchip Technology Inc. Preliminary DS30453C-page 119 PIC16C5X 15.4 DC Characteristics: PIC16C54B/C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial, Extended) PIC16LC54B/LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial, Extended) PIC16LCR54B/LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3. DC Characteristics All Pins Except Power Supply Pins Min Typ(1) Max Units VSS VSS VSS VSS VSS -- -- -- -- -- 0.8 V 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V V -- 2.0 0.25 VDD+0.8V 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD V V V V V V 0.15VDD* -- -- V -1.0 0.5 +1.0 A MCLR -5.0 T0CKI OSC1 -3.0 -3.0 -- 0.5 0.5 0.5 +5.0 +3.0 +3.0 -- A A A A -- -- -- -- 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, RC option only VDD-0.7 VDD-0.7 -- -- -- -- V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, RC option only Characteristic Sym Input Low Voltage I/O Ports I/O Ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 VIL Input High Voltage VIH I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs VHYS Input Leakage Current(3) I/O ports IIL Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage I/O ports(3) OSC2/CLKOUT VOH Conditions 4.5V <VDD 5.5V Otherwise RC option only(4) XT, HS and LP options 4.5V < VDD 5.5V Otherwise RC option only(4) XT, HS and LP options For VDD 5.5V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS +0.25V(2) VPIN = VDD(2) VSS VPIN VDD VSS VPIN VDD, XT, HS and LP options * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. DS30453C-page 120 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B 15.5 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low T Time mc osc os t0 wdt MCLR oscillator OSC1 T0CKI watchdog timer P R V Z Period Rise Valid Hi-impedance FIGURE 15-3: LOAD CONDITIONS PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B, PIC16CR5X Pin CL = 50 pF for all pins except OSC2 CL VSS 2000 Microchip Technology Inc. 15 pF for OSC2 in XT, HS or LP options when external clock is used to drive OSC1 Preliminary DS30453C-page 121 PIC16C5X 15.6 Timing Diagrams and Specifications FIGURE 15-4: EXTERNAL CLOCK TIMING - PIC16C5X, PIC16CR5X Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X AC Characteristics Parameter No. Sym FOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3. Characteristic External CLKIN Frequency(2) Oscillator 1 TOSC Frequency(2) (2) External CLKIN Period Oscillator Period(2) Min Typ(1) DC -- 4.0 MHz XT osc mode DC -- 4.0 MHz HS osc mode (04) DC -- 20 MHz HS osc mode (20) DC -- 200 kHz DC -- 4.0 MHz RC osc mode DC -- 4.0 MHz XT osc mode DC -- 4.0 MHz HS osc mode (04) DC -- 20 MHz HS osc mode (20) DC -- 200 kHz LP osc mode 250 -- -- ns XT osc mode 250 -- -- ns HS osc mode (04) 50 -- -- ns HS osc mode (20) 5.0 -- -- s LP osc mode 250 -- -- ns RC osc mode 250 -- 2,200 ns XT osc mode 250 -- 250 ns HS osc mode (04) 50 -- 250 ns HS osc mode (20) 5.0 -- 200 s LP osc mode Max Units Conditions LP osc mode * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS30453C-page 122 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X (CON'T) AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3. Parameter No. Sym Characteristic 2 TCY Instruction Cycle Time(3) 3 4 TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time Min Typ(1) -- 4/FOSC -- -- 50* -- -- ns XT oscillator 20* -- -- ns HS oscillator 2.0* -- -- s LP oscillator -- -- 25* ns XT oscillator -- -- 25* ns HS oscillator -- -- 50* ns LP oscillator Max Units Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. 2000 Microchip Technology Inc. Preliminary DS30453C-page 123 PIC16C5X FIGURE 15-5: CLKOUT AND I/O TIMING - PIC16C5X, PIC16CR5X Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 Note: Refer to Figure 19-1 for load conditions. TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X AC Characteristics Parameter No. 10 11 12 13 14 15 16 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3. Sym Characteristic Min Typ(1) Max Units TosH2ckL OSC1 to CLKOUT(2) -- 15 30** ns TosH2ckH CLKOUT(2) -- 15 30** ns -- 5.0 15** ns -- 5.0 15** ns -- -- 40** ns 0.25 TCY+30* -- -- ns 0* -- -- ns -- -- 100* ns TckR TckF TckL2ioV TioV2ckH TckH2ioI OSC1 to CLKOUT rise time CLKOUT fall (2) time(2) (2) CLKOUT to Port out valid (2) Port in valid before CLKOUT Port in hold after CLKOUT(2) valid(3) 17 TosH2ioV OSC1 (Q1 cycle) to Port out 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) TBD -- -- ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) TBD -- -- ns 20 TioR Port output rise time(3) -- 10 25** ns -- 10 25** ns 21 TioF Port output fall time(3) * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 3: See Figure 15-3 for loading conditions. DS30453C-page 124 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B FIGURE 15-6: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X, PIC16CR5X VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. TABLE 15-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X, PIC16CR5X AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3. Parameter No. Sym Characteristic 30 TmcL MCLR Pulse Width (low) 31 Twdt 32 34 Min Typ(1) Max Units 1000* -- -- ns VDD = 5.0V Watchdog Timer Time-out Period (No Prescaler) 9.0* 18* 30* ms VDD = 5.0V (Commercial) TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Commercial) TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000* ns Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. Preliminary DS30453C-page 125 PIC16C5X FIGURE 15-7: TIMER0 CLOCK TIMINGS - PIC16C5X, PIC16CR5X T0CKI 40 41 42 TABLE 15-4: TIMER0 CLOCK REQUIREMENTS - PIC16C5X, PIC16CR5X AC Characteristics Param No. 40 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3. Sym Characteristic Min Tt0H T0CKI High Pulse Width- No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width - No Prescaler - With Prescaler 42 Tt0P T0CKI Period Typ(1) Max Units Conditions 0.5 TCY + 20* -- -- ns 10* -- -- ns 0.5 TCY + 20* -- -- ns 10* -- -- ns 20 or TCY + 40* N -- -- ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30453C-page 126 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B 16.0 DC AND AC CHARACTERISTICS PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution, while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation. FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC FOSC (25C) Frequency normalized to +25C 1.10 REXT 10 k CEXT = 100 pF 1.08 1.06 1.04 1.02 1.00 0.98 VDD = 5.5 V 0.96 0.94 VDD = 3.5 V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 16-1: RC OSCILLATOR FREQUENCIES CEXT Average Fosc @ 5 V, 25C REXT 20 pF 3.3 k 5k 10 k 100 k 100 pF 3.3 k 5k 10 k 100 k 300 pF 3.3 k 5.0 k 10 k 160 k The frequencies are measured on DIP packages. 4.973 MHz 3.82 MHz 2.22 MHz 262.15 kHz 1.63 MHz 1.19 MHz 684.64 kHz 71.56 kHz 660 kHz 484.1 kHz 267.63 kHz 29.44 kHz 27% 21% 21% 31% 13% 13% 18% 25% 10% 14% 15% 19% The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5 V. 2000 Microchip Technology Inc. Preliminary DS30453C-page 127 PIC16C5X FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF 6.00 R=3.3K 5.00 R=5.0K FOSC (MHz) 4.00 3.00 R=10K 2.00 CEXT=20pF, T=25C 1.00 R=100K 0 2.5 3 3.5 4 5 4.5 5.5 6 VDD (Volts) FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF 1.80 R=3.3K 1.60 1.40 FOSC (MHz) R=5.0K 1.00 R=10K 0.60 CEXT=20pF, T=25C 0.20 R=100K 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD (Volts) DS30453C-page 128 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF 700.0 R=3.3K 600.0 500.0 FOSC (MHz) R=5.0K 400.0 300.0 R=10K CEXT=20pF, T=25C 200.0 100.0 R=100K 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD (Volts) FIGURE 16-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C) 25 20 IPD (uA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD (Volts) 2000 Microchip Technology Inc. Preliminary DS30453C-page 129 PIC16C5X FIGURE 16-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25C) 25 20 IPD (uA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 6 5.5 6 VDD (Volts) FIGURE 16-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (-40C, 85C) 35 30 25 IPD (uA) 20 15 10 (-40C) 5 (+85C) 0 2.5 3 3.5 4 4.5 5 VDD (Volts) DS30453C-page 130 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B FIGURE 16-8: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD 2.00 1.80 VTH (Volts) 1.60 1.40 25 Typ (+ C) 1.20 1.00 0.80 0.60 2.5 3.0 3.5 4.0 4.5 5.5 5.0 6.0 VDD (Volts) FIGURE 16-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD 4.5 4.0 3.5 C) +85 5C p +2 y t 5C) VIH to + 8 C (-40 m in VIH VIH VIH, VIL (Volts) ( max C to -40 3.0 2.5 2.0 to +85C) VIL max (-40C VIL typ +25C 1.5 1.0 5C) VIL min (-40C to +8 0.5 0.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 Note: These input pins have Schmitt Trigger input buffers. 2000 Microchip Technology Inc. Preliminary DS30453C-page 131 PIC16C5X FIGURE 16-10: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT (IN XT, HS AND LP MODES) vs. VDD 3.4 3.2 3.0 2.8 VTH (Volts) 2.6 C) +25 ( p Ty 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 FIGURE 16-11: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, 25C) 10000 IDD(A) 1000 5.5V 100 4.5V 3.5V 2.5V 10 0.1 1 10 Freq(MHz) DS30453C-page 132 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B FIGURE 16-12: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, 25C) 10000 IDD(uA) 1000 5.5V 100 4.5V 3.5V 2.5V 10 0.01 0.1 1 10 Freq(MHz) FIGURE 16-13: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, 25C) 10000 IDD(A) 1000 100 5.5V 4.5V 3.5V 2.5V 10 0.01 2000 Microchip Technology Inc. 0.1 Freq(MHz) Preliminary 1 DS30453C-page 133 PIC16C5X FIGURE 16-14: WDT TIMER TIME-OUT PERIOD vs. VDD TABLE 16-2: Typical Capacitance (pF) Pin 50 45 40 35 WDT period (ms) INPUT CAPACITANCE 30 Typ +125C 25 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. Typ +85C 20 Typ +25C 15 Typ -40C 10 5 2 3 4 5 6 7 VDD (Volts) DS30453C-page 134 Preliminary 2000 Microchip Technology Inc. PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B FIGURE 16-15: IOH vs. VOH, VDD = 3 V FIGURE 16-17: IOL vs. VOL, VDD = 3 V 0 45 Max -40C 40 -5 35 Min +85C IOL (mA) IOH (mA) 30 -10 Typ +25C -15 Max -40C 25 Typ +25C 20 15 Min +85C -20 10 5 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 VOH (Volts) FIGURE 16-16: IOH vs. VOH, VDD = 5 V 0.5 1.0 1.5 2.0 VOL (Volts) 3.0 FIGURE 16-18: IOL vs. VOL, VDD = 5 V 90 0 Max -40C 80 70 -10 60 Typ +125C Typ +25C -20 IOL (mA) IOH (mA) 2.5 Typ +85C Typ +25C -30 50 40 Min +85C Typ -40C 30 20 -40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 VOH (Volts) 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) 2000 Microchip Technology Inc. Preliminary DS30453C-page 135 PIC16C5X NOTES: DS30453C-page 136 Preliminary 2000 Microchip Technology Inc. PIC16C5X 17.0 PACKAGING INFORMATION 18-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .890 .898 .905 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 2000 Microchip Technology Inc. Preliminary MAX 4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15 DS30453C-page 137 PIC16C5X 28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 8.26 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L c .125 .130 .135 3.18 3.30 3.43 .008 .012 .015 0.20 0.29 0.38 1.65 Lead Thickness Upper Lead Width B1 .040 .053 .065 1.02 1.33 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 eB .320 .350 .430 8.13 8.89 10.92 5 10 15 5 10 15 5 10 15 5 10 15 Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 DS30453C-page 138 Preliminary 2000 Microchip Technology Inc. PIC16C5X 28-Lead Plastic Dual In-line (P) - 600 mil (PDIP) E1 D 2 1 n E A2 A L c B1 A1 p B eB Units Dimension Limits n p MIN INCHES* NOM 28 .100 .175 .150 MAX MILLIMETERS NOM 28 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 12.83 13.84 35.43 36.32 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .505 .545 .560 Overall Length D 1.395 1.430 1.465 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .620 .650 .680 5 10 15 Mold Draft Angle Top Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-079 2000 Microchip Technology Inc. Preliminary MAX 4.83 4.06 15.88 14.22 37.21 3.43 0.38 1.78 0.56 17.27 15 15 DS30453C-page 139 PIC16C5X 18-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L c B MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12 MAX .104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15 MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12 MIN MAX 2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 DS30453C-page 140 Preliminary 2000 Microchip Technology Inc. PIC16C5X 28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC) E E1 p D B 2 1 n h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B A1 MIN .093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MAX .104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 MIN MAX 2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 2000 Microchip Technology Inc. Preliminary DS30453C-page 141 PIC16C5X 20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n c A2 A L A1 Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c B MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5 MAX .078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10 MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5 MIN MAX 1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 DS30453C-page 142 Preliminary 2000 Microchip Technology Inc. PIC16C5X 28-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n A c A2 A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B MIN .068 .064 .002 .299 .201 .396 .022 .004 0 .010 0 0 INCHES NOM 28 .026 .073 .068 .006 .309 .207 .402 .030 .007 4 .013 5 5 MAX .078 .072 .010 .319 .212 .407 .037 .010 8 .015 10 10 MILLIMETERS* NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.38 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073 2000 Microchip Technology Inc. Preliminary DS30453C-page 143 PIC16C5X 18-Lead Ceramic Dual In-line with Window (JW) - 300 mil (CERDIP) E1 D W2 2 n 1 W1 E A2 A c L A1 eB B1 p B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Width Window Length * Controlling Parameter Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010 DS30453C-page 144 A A2 A1 E E1 D L c B1 B eB W1 W2 MIN .170 .155 .015 .300 .285 .880 .125 .008 .050 .016 .345 .130 .190 INCHES* NOM 18 .100 .183 .160 .023 .313 .290 .900 .138 .010 .055 .019 .385 .140 .200 Preliminary MAX .195 .165 .030 .325 .295 .920 .150 .012 .060 .021 .425 .150 .210 MILLIMETERS NOM 18 2.54 4.32 4.64 3.94 4.06 0.38 0.57 7.62 7.94 7.24 7.37 22.35 22.86 3.18 3.49 0.20 0.25 1.27 1.40 0.41 0.47 8.76 9.78 3.30 3.56 4.83 5.08 MIN MAX 4.95 4.19 0.76 8.26 7.49 23.37 3.81 0.30 1.52 0.53 10.80 3.81 5.33 2000 Microchip Technology Inc. PIC16C5X 28-Lead Ceramic Dual In-line with Window (JW) - 600 mil (CERDIP) E1 W D 2 n 1 E A2 A L c eB Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Diameter * Controlling Parameter Significant Characteristic JEDEC Equivalent: MO-103 Drawing No. C04-013 2000 Microchip Technology Inc. B1 A1 A A2 A1 E E1 D L c B1 B eB W p B MIN .170 .155 .015 .595 .514 1.430 .125 .008 .050 .016 .610 .270 INCHES* NOM 28 .100 .185 .160 .038 .600 .520 1.460 .138 .010 .058 .020 .660 .280 Preliminary MAX .200 .165 .060 .625 .526 1.490 .150 .012 .065 .023 .710 .290 MILLIMETERS NOM 28 2.54 4.32 4.70 3.94 4.06 0.38 0.95 15.11 15.24 13.06 13.21 36.32 37.08 3.18 3.49 0.20 0.25 1.27 1.46 0.41 0.51 15.49 16.76 6.86 7.11 MIN MAX 5.08 4.19 1.52 15.88 13.36 37.85 3.81 0.30 1.65 0.58 18.03 7.37 DS30453C-page 145 PIC16C5X 17.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX PIC16C56A04I/P456 YYWWNNN 28-Lead Skinny PDIP (.300") 0023CBA Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX PIC16C55A04I/P456 YYWWNNN 28-Lead PDIP (.600") 0023CBA Example XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC PIC16C55A04/P126 0042CDA Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC16C54C04/S0218 YYWWNNN 28-Lead SOIC 0018CDK Example PIC16C57C04/SO XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP 0015CBK Example PIC16C54C 04/218 0020CBP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 28-Lead SSOP Example PIC16C57C04/SS123 XXXXXXXXXXXX XXXXXXXXXXXX 0025CBK YYWWNNN DS30453C-page 146 Preliminary 2000 Microchip Technology Inc. PIC16C5X 18-Lead CERDIP Windowed Example XXXXXXXX XXXXXXXX YYWWNNN PIC16C54C /JW 0001CBA 28-Lead CERDIP Windowed Example PIC16C57C /JW XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: Note: * XX...X YY WW NNN 0038CBA Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2000 Microchip Technology Inc. Preliminary DS30453C-page 147 PIC16C5X NOTES: DS30453C-page 148 Preliminary 2000 Microchip Technology Inc. PIC16C5X APPENDIX A: COMPATIBILITY To convert code written for PIC16CXX to PIC16C5X, the user should take the following steps: 1. 2. 3. 4. 5. 6. 7. Check any CALL, GOTO or instructions that modify the PC to determine if any program memory page select operations (PA2, PA1, PA0 bits) need to be made. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any special function register page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change Reset vector to proper value for processor used. Remove any use of the ADDLW and SUBLW instructions. Rewrite any code segments that use interrupts. 2000 Microchip Technology Inc. Preliminary DS30453C-page 149 PIC16C5X NOTES: DS30453C-page 150 Preliminary 2000 Microchip Technology Inc. PIC16C5X INDEX F A Absolute Maximum Ratings ........................... 61, 81, 93, 115 ALU ...................................................................................... 9 Applications .......................................................................... 5 Architectural Overview ......................................................... 9 Assembler MPASM Assembler .................................................... 55 B Block Diagram On-Chip Reset Circuit ................................................ 36 PIC16C5X Series ....................................................... 10 Timer0 ........................................................................ 27 TMR0/WDT Prescaler ................................................ 30 Watchdog Timer ......................................................... 40 Brown-out Protection Circuit .............................................. 41 C Carry bit ............................................................................... 9 Clocking Scheme ............................................................... 13 CMOS Technology ............................................................... 1 Code Protection ........................................................... 31, 42 Configuration Bits ............................................................... 31 Configuration Word ............................................................ 31 PIC16C54/C54A/C55/C56/C57 .................................. 32 PIC16CR54A/C54C/CR54C/C55A/C56A/ CR56A/C57C/CR57C/C58B/CR58B .......................... 31 D DC and AC Characteristics - PIC16C54/55/56/57 ............. 73 DC and AC Characteristics - PIC16C54A ........................ 105 DC and AC Characteristics - PIC16C54C/CR54C/ C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ............ 127 DC Characteristics ............................................... 82, 94, 117 PIC16C54/55/56/57 ........................... 62, 63, 64, 65, 66 PIC16C54A ................................................................ 94 PIC16CR54A ............................................................. 82 Development Support ........................................................ 55 Device Varieties ................................................................... 7 Digit Carry bit ....................................................................... 9 E Electrical Characteristics PIC16C54/55/56/57 ................................................... 61 PIC16C54A ................................................................ 93 PIC16C54C/CR54C/C55A/C56A/CR56A/ C57C/CR57C/C58B/CR58B .................................... 115 PIC16CR54A ............................................................. 81 Errata ................................................................................... 4 External Power-on Reset Circuit ........................................ 37 2000 Microchip Technology Inc. Family of Devices PIC16C5X .................................................................... 6 FSR ................................................................................... 36 FSR Register ..................................................................... 22 H High-Performance RISC CPU ............................................. 1 I I/O Interfacing .................................................................... 25 I/O Ports ............................................................................ 25 I/O Programming Considerations ...................................... 26 ID Locations ................................................................. 31, 42 INDF .................................................................................. 36 INDF Register .................................................................... 22 Indirect Data Addressing ................................................... 22 Instruction Cycle ................................................................ 13 Instruction Flow/Pipelining ................................................. 13 Instruction Set Summary ................................................... 43 K KeeLoq Evaluation and Programming Tools .................. 58 L Loading of PC .............................................................. 21, 22 M MCLR ................................................................................ 36 Memory Map ...................................................................... 15 PIC16C54/CR54/C55 ................................................ 15 PIC16C56/CR56 ........................................................ 15 PIC16C57/CR57/C58/CR58 ...................................... 15 Memory Organization ........................................................ 15 Data Memory ............................................................. 16 Program Memory ....................................................... 15 MPLAB Integrated Development Environment Software ... 55 O One-Time-Programmable (OTP) Devices ........................... 7 OPTION ............................................................................. 36 OPTION Register ............................................................... 20 OSC selection .................................................................... 31 Oscillator Configurations .................................................... 33 Oscillator Types HS .............................................................................. 33 LP .............................................................................. 33 RC ............................................................................. 33 XT .............................................................................. 33 Preliminary DS30453C-page 151 PIC16C5X P S Package Marking Information .......................................... 146 Packaging Information ..................................................... 137 PC ...................................................................................... 21 PCL .................................................................................... 36 Peripheral Features .............................................................. 1 PIC16C54/55/56/57 Product Identification System .......... 156 PIC16C5X Product Identification System ......................... 155 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 57 PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 57 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 57 PICSTART Plus Entry Level Development System ........ 57 Pin Configurations ................................................................ 2 Pinout Description - PIC16C54s, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, PIC16CR58 ..................................................... 11 Pinout Description - PIC16C55, PIC16C57, PIC16CR57 ........................................................................ 12 POR Device Reset Timer (DRT) ................................... 31, 39 PD ........................................................................ 35, 41 Power-on Reset (POR) .................................. 31, 36, 37 TO ........................................................................ 35, 41 PORTA ......................................................................... 25, 36 PORTB ......................................................................... 25, 36 PORTC ......................................................................... 25, 36 Power-down Mode (SLEEP) .............................................. 42 Prescaler ............................................................................ 30 PRO MATE II Universal Programmer .............................. 57 Program Counter ................................................................ 21 Serialized Quick-Turnaround-Production (SQTP) Devices ................................................................................ 7 SLEEP ......................................................................... 31, 42 Software Simulator (MPLAB-SIM) ..................................... 56 Special Features of the CPU ............................................. 31 Special Function Registers ................................................ 18 Stack .................................................................................. 22 STATUS ............................................................................. 36 STATUS Register .......................................................... 9, 19 Q Q cycles ............................................................................. 13 Quick-Turnaround-Production (QTP) Devices ..................... 7 R T Timer0 Switching Prescaler Assignment ............................... 30 Timer0 (TMR0) Module .............................................. 27 TMR0 with External Clock ......................................... 29 Timing Diagrams and Specifications ............. 68, 88, 99, 122 Timing Parameter Symbology and Load Conditions ............................................. 67, 87, 98, 121 TMR0 ................................................................................. 36 TRIS ................................................................................... 36 TRIS Registers .................................................................. 25 U UV Erasable Devices ........................................................... 7 W W Register ......................................................................... 36 Wake-up from SLEEP ........................................................ 42 Watchdog Timer (WDT) ............................................... 31, 39 Period ........................................................................ 39 Programming Considerations .................................... 39 WWW, On-Line Support ...................................................... 4 Z Zero bit ................................................................................. 9 RC Oscillator ...................................................................... 34 Read Only Memory (ROM) Devices ..................................... 7 Read-Modify-Write ............................................................. 26 Register File Map PIC16C54, PIC16CR54, PIC16C55, PIC16C56, PIC16CR56 ............................................. 16 PIC16C57/CR57 ........................................................ 17 PIC16C58/CR58 ........................................................ 17 Registers Special Function ........................................................ 18 RESET ............................................................................... 35 Reset .................................................................................. 31 RESET on Brown-out ......................................................... 41 DS30453C-page 152 Preliminary 2000 Microchip Technology Inc. PIC16C5X ON-LINE SUPPORT Systems Information and Upgrade Hot Line Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-786-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 991103 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2000 Microchip Technology Inc. Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER, PRO MATE and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. Preliminary DS30453C-page 153 PIC16C5X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C5X Y N Literature Number: DS30453C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30453C-page 154 Preliminary 1998 Microchip Technology Inc. PIC16C5X PIC16C5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X PART NO. Device Temperature Range Device /XX XXX Package Pattern Examples: PIC16C5X(2), PIC16C5XT(3) PIC16LC5X(2), PIC16LC5XT(3) PIC16CR5X(2), PIC16CR5XT(3) PIC16LCR5X(2), PIC16LCR5XT(3) PIC16LV5X(2), PIC16LV5XT(3) Temperature Range b(1) I E = 0C to +70C = -40C to +85C = -40C to +125C Package JW P SO SP SS = Windowed CERDIP = PDIP = SOIC (Gull Wing, 300 mil body) = Skinny PDIP (28-pin, 300 mil body) = SSOP (209 mil body) Pattern 3-digit Pattern Code for QTP, ROM (blank otherwise) 2000 Microchip Technology Inc. (Commercial) (Industrial) (Automotive) Preliminary a) PIC16C54A -04/P 301 = Commercial temp., PDIP package, 4MHz, normal VDD limitis, QTP pattern #301. b) PIC16LC58A - 04I/SO = Industrial temp., SOIC package, 4MHz, Extended VDD limits. c) PIC16CR54A - 10I/P355 = ROM program memory, Industrial temp., PDIP package, 10MHz, normal VDD limits. Note 1: b = blank 2: C = Standard VDD range LC = Extended VDD range CR = ROM Version, Standard VDD range LCR = ROM Version, Extended VDD range LV = Low Voltage VDD range 3: T = in tape and reel - SOIC, SSOP packages only. 4: UV erasable devices are tested to all available voltage/frequency options. Erased devices are oscillator type 04. The user can select 04, 10 or 20 oscillators by programmng the appropriate configuration bits. DS30453C-page 155 PIC16C5X PIC16C54/55/56/57 PRODUCT IDENTIFICATION SYSTEM To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office. PART NO. -XX Device Oscillator Type Device X Temperature Range /XX XXX Package Pattern PIC16C54, PIC16C54T(2) PIC16C55, PIC16C55T(2) PIC16C56, PIC16C56T(2) PIC16C57, PIC16C57T(2) Oscillator Type RC LP XT HS 10 b(1) = Resistor Capacitor = Low Power Crystal = Standard Crystal/Resonator = High Speed Crystal = 10 MHz Crystal = No type for JW(3) devices Temperature Range b(1) I E = 0C to +70C (Commercial) = -40C to +85C (Industrial) = -40C to +125C (Automotive) Package JW P S SO SP SS = Windowed CERDIP = PDIP = Die in Waffle Pack = SOIC (Gull Wing, 300 mil body) = Skinny PDIP (28 pin, 300 mil body) = SSOP (209 mil body) Pattern 3-digit Pattern Code for QTP (blank otherwise) Examples: a) PIC16C54 - XT/PXXX = "XT" oscillator, commercial temp., PDIP, QTP pattern. b) PIC16C55 - XTI/SO = "XT" oscillator, industrial temp., SOIC (OTP device) c) PIC16C55 /JW = Commercial temp. CERDIP with window. d) PIC16C57 - RC/S = "RC" oscillator, commercial temp., dice in waffle pack. Note 1: b = blank 2: T = in tape and reel - SOIC, SSOP packages only. 3: UV erasable devices are tested to all available voltage/frequency options. Erased devices are oscillator type RC. The user can select RC, LP, XT or HS oscillators by programming the appropriate configuration bits. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS30453C-page 156 Preliminary 2000 Microchip Technology Inc. PIC16C5X NOTES: 2000 Microchip Technology Inc. Preliminary DS30453C-page 157 WORLDWIDE SALES AND SERVICE AMERICAS AMERICAS (continued) Corporate Office Toronto Singapore Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Atlanta Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing, 100027, P.R.C. Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston ASIA/PACIFIC China - Beijing ASIA/PACIFIC (continued) Taiwan Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE China - Shanghai Denmark Microchip Technology Unit B701, Far East International Plaza, No. 317, Xianxia Road Shanghai, 200051, P.R.C. Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Hong Kong France Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India Germany Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore, 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Detroit Japan Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Microchip Technology Inc. 2 LAN Drive, Suite 120 Westford, MA 01886 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Dayton Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Italy United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835 05/16/00 San Jose Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 All rights reserved. (c) 2000 Microchip Technology Incorporated. Printed in the USA. 7/00 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30453C-page 158 Preliminary 2000 Microchip Technology Inc.