PIC16C56A-04E/JW - Microchip Technology, Inc.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 1

PIC16C5X

Devices Included in this Data Sheet:

•PIC16C54

• PIC16CR54

•PIC16C55

•PIC16C56

• PIC16CR56

•PIC16C57

• PIC16CR57

•PIC16C58

• PIC16CR58

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All i nstructions are s ingle cycle (200 ns) except f or

progra m bran ch es w hic h are two -cy c le

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 12-bit wide instructions

• 8-bit wide data path

• Seven or eight special function hardware registers

• Two-level deep hardware stack

• Direct, indirect and relative addressing modes for

data and instr u cti on s

Note: 16C5X refers to all revisions of the part

(i.e., 16C54 refers to 16C54, 16C54A, and

16C54C), unless specifically called out

otherwise.

Device Pins I/O EPROM/

ROM RAM

PIC16C54 18 12 512 25

PIC16C54A 18 12 512 25

PIC16C54C 18 12 512 25

PIC16CR54A 18 12 512 25

PIC16CR54C 18 12 512 25

PIC16C55 28 20 512 24

PIC16C55A 28 20 512 24

PIC16C56 18 12 1K 25

PIC16C56A 18 12 1K 25

PIC16CR56A 18 12 1K 25

PIC16C57 28 20 2K 72

PIC16C57C 28 20 2K 72

PIC16CR57C 28 20 2K 72

PIC16C58B 18 12 2K 73

PIC16CR58B 18 12 2K 73

Peripheral Features:

• 8-bit real time cl ock /c oun ter (TM R0) with 8-bit

progra mmab le pres caler

• Power-on Reset (POR )

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip

RC oscillator for reliable operation

• Programmable Code Protection

• Power saving SLEEP mode

• Selectab le os cil la t or opti ons:

- RC: Low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

- LP: Power saving, low-frequency crystal

CMOS Technology:

• Low-power, high-speed CMOS EPROM/ROM

technology

• Fully static design

• Wide-operating voltage and temperature range:

- EPROM Commercial /Industrial 2.0V to 6.25V

- ROM Commercial/In dustrial 2.0V to 6.25V

- EPROM Extended 2.5V to 6.0V

- ROM Extended 2.5V to 6.0V

• Low-power consumption

- < 2 mA typical @ 5V, 4 MHz

-15 µA typical @ 3V, 32 kHz

- < 0.6 µA typic al standby current

(with WDT disabl ed) @ 3V, 0°C to 70°C

Note: In this document, figure and table titles

refer to all varieties of the part number indi-

cated, (i.e., The title "Figure 14-1: Load

Conditions - PIC16C54A", also refers to

PIC16LC54A and PIC16LV54A parts)

unless specifically called out otherwise.

EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

PIC16C5X

DS30453C-page 2 Preliminary  2000 Microchip Technology Inc.

Pin Diagra ms

PDIP, SO IC, Wi nd o wed CE R D IP

PIC16CR54

PIC16C58

PIC16CR58

PIC16C54

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

RA2

RA3

T0CKI

MCLR/VPP

VSS

RB0

RB1

RB2

RB3

•1

SSOP

PIC16C56

PIC16CR56

PIC16CR54

PIC16C58

PIC16CR58

PIC16C54

PIC16C56

PIC16CR56

RA2

RA3

T0CKI

MCLR/VPP

VSS

RB0

RB1

RB2

RB3

•1

910

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

•1

PDIP, SOIC, Wind owe d CERDIP

PIC16C57

PIC16C55

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RB6

RB5

T0CKI

VDD

VSS

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

•1

SSOP

PIC16C55

VDD

VSS

PIC16CR57

T0CKI

VDD

N/C

VSS

N/C

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RB6

RB5

PIC16C57

 2000 Microchip Technology Inc. Preliminary DS30453C-page 3

PIC16C5X

Device Differences

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

Device Voltage

Range

Oscillator

Selection

(Program) Oscillator Process

Technology

(Microns)

ROM

Equivalent MCLR

Filter

PIC16C54 2.5-6.25 Factory See Note 1 1.2 PIC16CR54A No

PIC16C54A 2.0-6.25 User See Note 1 0.9 —No

PIC16C54C 2.5-5.5 User See Note 1 0.7 PIC16CR54C Yes

PIC16C55 2.5-6.25 Factory See Note 1 1.7 —No

PIC16C55A 2.5-5.5 User See Note 1 0.7 —Yes

PIC16C56 2.5-6.25 Factory See Note 1 1.7 —No

PIC16C56A 2.5-5.5 User See Note 1 0.7 PIC16CR56A Yes

PIC16C57 2.5-6.25 Factory See Note 1 1.2 —No

PIC16C57C 2.5-5.5 User See Note 1 0.7 PIC16CR57C Yes

PIC16C58B 2.5-5.5 User See Note 1 0.7 PIC16CR58B Yes

PIC 16CR54A 2.5-6. 25 Fac tory See Note 1 1.2 N/A Yes

PIC16CR54C 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PIC16CR56A 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PIC16CR57C 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PIC16CR58B 2.5-5.5 Factory See Note 1 0.7 N/A Yes

Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties,

please refer to Section 2.0.

PIC16C5X

DS30453C-page 4 Preliminary  2000 Microchip Technology Inc.

Table of C ontents

1.0 General Description................... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. .... .. ....... .. .... .. .. ............................................................... 5

2.0 PIC1 6 C5 X Device Varieties .......................................... ............................. ............................ ...................................................... 7

3.0 Architectural Ov erview ................................................................................................................................................................. 9

4.0 Memory Organization................................................................................................................................................................. 15

5.0 I /O Po r ts ............... ........... .............. ................................ ............... ..................... ......................................................................... 25

6.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 27

7.0 Sp e cial Features of the CPU... ................... ................... ............................. ................................................................................ 31

8.0 Instruction Set Summary............................................................................................................................................................ 43

9.0 Development Support................................................................................................................................................................. 55

10.0 Electrical Characteristics - PIC16C54/55/56/57......................................................................................................................... 61

11.0 DC and AC Characteristics - PIC16C54/55/56/57........... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .......................................... 73

12.0 Electrical Characteristics - PIC16CR54A ................................................................................................................................... 81

13.0 Electrical Characteristics - PIC16C54A...................................................................................................................................... 93

14.0 DC and AC Characteristics - PIC16C54A .......................................... .... .... .. ......... .... .. .... ....... .... .............................................. 105

15.0 Electrical Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B......................................... 115

16.0 DC and AC Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B...................... .. ....... .. .... 127

17.0 Packagin g In fo r mation........... .............................................. ..................................................................................................... 137

Appendix A: Compatibility....................... ....... .. .... .. .. .... ..... .... .. .. .... .. .. ....... .. .... .. .. .... ..... .... .. .. ............................................................... 149

Index .................................................................................................................................................................................................. 151

On-Line Support.............................. .... .. ......... .. .... .... .. ......... .... .. .... .... ....... .... .. .... .... ....... .... ................................................................. 153

Reader Response.............................................................................................................................................................................. 154

PIC16C5X Product Identification System ...................................................... .... .... ........... .... .... ......................................................... 155

PIC16C54/55/56/57 Product Identification System ........................................................................................................................... 156

To Our Valued Customers

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An errata s heet may exist for current devices, describing minor o perational differences (from the data sheet) and rec ommended

workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-

sion of silicon and revision of document to which it applies.

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We appreciate your assistance in making this a better document.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 5

PIC16C5X

1.0 GENERAL DESCRIPTION

The PIC16C5X from Microchip Technology is a family

of low-cost, high performance, 8-bit, fully static,

EPROM/ROM-based CMOS microcontrollers. It

employs a RISC architecture with only 33 single

word/single cycle instructions. All instructions are sin-

gle cycle (200 ns) except for program branches which

take two cycles. The PIC16C5X delivers performance

an or der of magnitu de higher tha n its compe titors in the

same price category. The 12-bit wide instructions are

highly symmetrical resulting in 2:1 code compression

over other 8-bit microcontrollers in its class. The easy

to use and easy to remember instruction set reduces

development time significantly.

The PIC1 6C5X products a re equipped w ith special fe a-

tures tha t reduce system cost and po wer requirements .

The Power-on Reset (POR) and Device Reset Timer

(DRT) eliminate the need for external reset circuitry.

There are four oscill ator c onfigu rations to ch oose from,

including the power-saving LP (Low Power) oscillator

and cost saving RC oscillator. Power saving SLEEP

mode, Watchdog Timer and Code Protection features

improve system cost, power and reliability.

The UV era sable CE RDIP packa ged versi ons are idea l

for code development, while the cost-effective One

Time Programmable (OTP) versions are suitable for

production in any volume. The customer can take full

advantage of Microchip’s price leadership in OTP

microcontrollers, while benefiting from the OTP’s

flexibility.

The PIC16C5X products are supported by a

full-feat ured mac ro assembl er , a software simulato r , a n

in-circuit emulator, a low-cost development program-

mer and a full featured programmer. All the tools are

supported on IBM PC and compatible machines.

1.1 Applications

The PIC16C5X series fits pe rfectly in applications rang-

ing from high-speed automotive and appliance motor

control to low-power remote transmitters/receivers,

pointing devi ces and telecom p rocessors . The EPR OM

technology makes customizing application programs

(transmitter codes, motor speeds, receiver frequen-

cies, etc.) extremely fast and convenient. The small

footprint packages, for through hole or surface mount-

ing, ma ke this microcontroller series perfect for applica-

tions with space limitations. Low-cost, low-power, high

performance, ease of use and I/O flexibility make the

PIC16C5X se ries very versatile even in areas where no

microcontroller use has been considered before (e.g.,

timer functions, replacement of “glue” logic in larger

systems, co-processor applications).

PIC16C5X

DS30453C-page 6 Preliminary  2000 Microchip Technology Inc.

TABLE 1-1: PIC16C5X FAMILY OF DEVICES

PIC16C54 PIC16CR54 PIC16C55 PIC16C56 PIC16CR56

Clock Maximum Frequency

of Operation (MHz) 20 20 20 20 20

Memory

EPROM Program Memory

(x12 words) 512 —512 1K —

ROM Program Mem ory

(x12 words) —512 ——1K

RAM D ata Me mory (bytes) 25 25 24 25 25

Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0

Features

I/O Pins 12 12 20 12 12

Number of Instructions 33 33 33 33 3 3

Packages 18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

28-pin DIP,

SOIC;

28-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

All PICmicro ® Family de vices h ave Pow er-on Rese t, selec table W atc hdog Timer, se lectable Code Pro tect and high I/O

current ca pab ili ty.

PIC16C57 PIC16CR57 PIC16C58 PIC16CR58

Clock Maximum Frequency

of Operation (MHz) 20 20 20 20

Memory

EPROM Pr ogram M emory

(x12 words) 2K —2K —

ROM Program Memory

(x12 words) —2K —2K

RAM Data Memory (bytes) 72 72 73 73

Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0

Features

I/O Pins 20 20 12 12

Number of Instructions 33 33 33 33

Packages 28-pin DIP,

SOIC;

28-pin SSOP

28-pin DIP,

SOIC;

28-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code

Protect and high I/O current capability.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 7

PIC16C5X

2.0 PIC16C5X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are avail able. Depending on application an d production

requirem ents, the p roper device option can b e selected

using the information in this section. When placing

orders, please use the PIC16C5X Product Identifica-

tion Sys tem at the b ack of thi s data sh eet to spe cify the

correct part num be r.

For the PIC16C5X family of devices, there are four

device types, as indicated in the device number:

1. C, as in PIC16C54C. These devices have

EPROM progra m m emo ry an d ope rate over the

standard voltage range.

2. LC, as in PIC16LC54A. These devices have

EPROM program memory and operate over an

extended voltage range.

3. CR, as in PIC16CR54A. These devices have

ROM program memory and operate over the

standard voltage range.

4. LCR, as in PIC16LCR54A. These de vic es hav e

ROM program memory and operate over an

extended voltage range.

2.1 UV Erasable Devices (EPROM)

The UV erasable versions, offered in CERDIP pack-

ages, are optimal for prototype development and pilot

programs.

UV eras able device s can be pro grammed for a ny of the

four oscillator configurations. Microchip’s PICSTART

and PRO MATE programm ers bo th s up port pro gram -

ming of the PIC16C5X. Third party programmers also

are avai lable. R efer to the Th ird Party Guid e for a list of

sources.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers expecting frequent code changes and

updates.

The OTP devices, packaged in plastic packages, per-

mit the user to program them once. In addition to the

program memory, the configuration bits must be pro-

grammed.

2.3 Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for fac-

tory production orders. This service is made available

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devices ar e id enti ca l to t he OT P d evi ce s b ut

with all EPROM locations and configuration bit options

alre ady prog rammed by the factory. Certai n code and

prototype verification procedures apply before produc-

tion shipments are available. Please contact your

Microchip Technology sales office for more details.

2.4 Serialized

Quick-Turnaround-Production

(SQTP ) Devices

Microchip offers the unique programming service

where a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or sequen-

tial. The devices are identical to the OTP devices but

with all EPROM locations and configuration bit options

already programmed by the factory.

Serial programming allows each device to have a

unique number which can serve as an entry code,

password or ID number.

2.5 Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of

the highest volume parts, giving the customer a low

cost option for high volume, mature products.

PIC16C5X

DS30453C-page 8 Preliminary  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Preliminary DS30453C-page 9

PIC16C5X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C5X family can be

attributed to a number of architectural features com-

monly found in RISC microprocessors. To begin with,

the PIC16C5X uses a Harvard architecture in which

program and data are accessed on separate buses.

This improves bandwidth over traditi onal von Neumann

architecture where program and data are fetched on

the same bus. Separating program and data memory

further allows instructions to be sized differently than

the 8-bit wide data word. Instruction opcodes are

12-b its wide making it possi ble to have all sing le word

instructions. A 12-bit wide program memory access

bus fetches a 12-bit instruction in a single cycle. A

two-stage pipeline overlaps fetch and execution of

instructions. Consequently, all instructions (33) execute

in a sin gle cy cl e (200ns @ 20MHz) ex cept for program

branches.

The PIC1 6C54/CR54 and PIC16C 55 address 5 12 x 12

of program memory, the PIC16C56/CR56 address

1K x 12 of program memory, and the PIC16C57/CR 57

and PIC16C58/CR58 address 2K x 12 of program

memor y. All program memory is internal.

The PIC16C5X can directly or indirectly address its

isters i ncluding the pro gram c ounter a re mapp ed in th e

data memory. The PIC16C5X has a highly orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

‘special optimal situations’ make prog rammi ng with th e

PIC16C5X si mple yet ef ficien t. In additi on, the lea rnin g

curve is reduced significantly.

The PIC16 C5X devic e contains an 8-bit ALU and work-

ing register. The ALU is a general purpose arithmetic

unit. It performs arithmetic and Boolean functions

between data in the working register and any register

file.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the W (working) register. The other

operand is either a file register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affe ct the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the ST ATUS regist er . The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

A simplified block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

PIC16C5X

DS30453C-page 10 Preliminary  2000 Microchip Technology Inc.

FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM

WDT TIME

OUT

STACK 1

STACK 2

EPROM/ROM

512 X 12 TO

2048 X 12

INSTRUCTION

DECODER

WATCHDOG

TIMER

CONFIGURATION WORD

OSCILLATOR/

TIMING &

CONTROL

GENERAL

PURPOSE

FILE

(SRAM)

24, 25, 72 or

73 Bytes

WDT/TMR0

PRESCALER

OPTI ON R EG. “OPTION”

“SLEEP”

“CODE

PROTECT”

“OSC

SELECT”

DIRECT ADDRESS

TMR0

FROM W

“TRIS 5”“TRIS 6”“TRIS 7”

FSR

TRISA PORTA TRISB PORTC

TRISC

PORTB

FROM W

T0CKI

9-11

DATA BUS

ALU

STATUS

FROM W

CLKOUT

5-7

OSC1 OSC2 MCLR

LITERALS

PC “DISABLE”

RA<3:0> RB<7:0> RC<7:0>

(28-Pin

Devices O nl y)

DIRECT RAM

ADDRESS

 2000 Microchip Technology Inc. Preliminary DS30453C-page 11

PIC16C5X

TABLE 3-1: PINOUT DESCRIPTION - PIC16C54s, PIC16CR54, PIC16C56, PIC16CR56,

PIC16C58, PIC16CR58

Name DIP, SOIC

No. SSOP

No. I/O/P

Type Input

Levels Description

RA0

RA1

RA2

RA3

I/O

TTL

Bi-directional I/O port

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

I/O

TTL

Bi-directional I/O port

T0CKI 3 3 I ST Clock input to Timer0. Must be tied to VSS or VDD, if not in

use, to reduce current consumption.

MCLR/VPP 4 4 I ST Master cl ear (RESET) input/programming vo lta ge i np ut. T his

pin is an active low RESET to the device. Voltage on the

MCLR/VPP pin must not exceed VDD to avoid unintended

entering of programming mode.

OSC1/CLKIN 16 18 I ST Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 17 O —Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT, whic h h as 1/4 th e fre qu enc y of OSC1 and deno tes

the instruction cycl e rate.

VDD 14 15,16 P —Positive supply for logic and I/O pins.

VSS 55,6P—Ground reference for logic and I/O pins.

Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input

PIC16C5X

DS30453C-page 12 Preliminary  2000 Microchip Technology Inc.

TABLE 3-2: PINOUT DESCRIPTION - PIC16C55, PIC16C57, PIC16CR57

Name DIP, SOIC

No. SSOP

No. I/O/P

Type Input

Levels Description

RA0

RA1

RA2

RA3

I/O

TTL

Bi-direct ion al I/O port

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

I/O

TTL

Bi-direct ion al I/O port

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

I/O

TTL

Bi-direct ion al I/O port

T0CKI 1 2 I ST Clock i npu t to Ti me r0. Mu st be tied to VSS or VDD if not in use

to reduce current consumption.

MCLR 28 28 I ST Master clear (RESET) input. Thi s pi n is an activ e lo w RESET

to the device.

OSC1/CLKIN 27 27 I ST Oscillator crystal input/external clock source input.

OSC2/CLKOUT 26 26 O —Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT w hi ch has 1/ 4 th e freq uen cy of O SC1, and denotes

the instruction cycle r ate.

VDD 23,4P—Positive supply for logic and I/O pins.

VSS 41,14P—Ground reference fo r logic and I/O pins.

N/C 3,5 ———Unused, do not connect.

Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input

 2000 Microchip Technology Inc. Preliminary DS30453C-page 13

PIC16C5X

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram c oun ter is incremente d ev ery Q1 and the instruc-

tion is fetched from program memory and latched into

the instruction register in Q4. It is decoded and exe-

cuted during the following Q1 through Q4. The clocks

and instru c ti o n ex ec ut i on f low are s ho w n i n Fi g ure 3-2

and Example 3-1.

3.2 Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are pipe-

lined such that fetch takes one instruction cycle, while

decode and execute takes another instruction cycle.

However, due to the pipelining, each instruction effec-

tively executes in one c ycle. If a n instructi on causes th e

program counter to change (e.g., GOTO), then two

cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the Instruction Register in cycle Q1. This instruc-

tion is then decoded and executed during the Q2, Q3

and Q4 cycles. Data memory is read during Q2 (oper-

and read) and written during Q4 (destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instr uction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

1. MOVLW 55H Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16C5X

DS30453C-page 14 Preliminary  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Preliminary DS30453C-page 15

PIC16C5X

4.0 MEMORY ORGANIZATION

PIC16C5X m em ory is orga niz ed into pro gram me mo ry

and data memory. For devices with more than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one or two

STA TUS Reg ister bits. F or device s with a da ta memo ry

scheme is used. Data memory banks are accessed

using the File Selection Register (FSR).

4.1 Program Memory Organization

The PIC16C54, PIC16CR54 and PIC16C55 have a

9-bit Program Counter (PC) capable of addressing a

512 x 12 program memory space (Figure 4-1). The

PIC16C56 and PIC16CR56 have a 10-bit Program

Counte r (PC) c apable of addres sing a 1K x 12 progra m

memory space (Figure 4-2). The PIC16CR57,

PIC16C58 and PIC16CR58 have an 11-bit Program

Counter capable of addressing a 2K x 12 program

memory space (Figure 4-3). Accessing a location

above th e physic ally impl emented a ddress will cause a

wraparound.

A NOP at the RESET vector locati on will caus e a restart

at locat ion 000 h. The RESET vector for the PI C16C54,

PIC16CR54 and PIC16C55 is at 1FFh. The RESET

vector for the PIC16C56 and PIC16CR56 is at 3FFh.

The RESET vector for the PIC16C57, PIC16CR57,

PIC16C58, and PIC16CR58 is at 7FFh.

FIGURE 4-1: PIC16C5 4/CR5 4/C5 5

PROGRAM MEMORY MAP

AND STACK

PC<8:0>

Stack Level 1

Stack Level 2

User Memory

Space

CALL, RETLW 9

000h

1FFh

RESET Vector

0FFh

100h

On-chip

Program

Memory

FIGURE 4-2: PIC16C56/CR56 PROGRAM

MEMORY MAP AND STACK

FIGURE 4-3: PIC16C57/CR57/C58/

CR58 PROGRAM MEMORY

MAP AND STACK

PC<9:0>

Stack Level 1

Stack Level 2

User Memo ry

Space

000h

1FFh

RESET Vector

0FFh

100h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

200h

2FFh

300h

3FFh

CALL, RETLW

PC<10:0>

Stack Level 1

Stack Level 2

User Memory

Space

000h

1FFh

RESET Vector

0FFh

100h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

On-chip Program

Memory (Page 2)

On-chip Program

Memory (Page 3)

200h

3FFh

2FFh

300h

400h

5FFh

4FFh

500h

600h

7FFh

6FFh

700h

CALL, RETLW

PIC16C5X

DS30453C-page 16 Preliminary  2000 Microchip Technology Inc.

4.2 Data Memory Organization

Data memory is composed of registers, or bytes of

RAM. Therefore, data memory for a device is specified

by its register file. The register file is divided into two

functional groups: Special Function Registers and

General Purpose Registers.

The Specia l Fun cti on R eg ist ers incl ude the TM R0 reg-

ister, the Program Counter (PC), the Status Register,

the I/O registers (ports) and the File Select Register

(FSR). In addition, Special Purpose Registers are used

to control the I/O port configuration and prescaler

options.

The G ener al Pu rpos e Re giste rs are used for dat a and

control inf ormati on under com mand of the instru ctions .

For the PIC16C54, PIC16CR54, PIC16C56 and

PIC16CR56, the register file is composed of 7 Special

Funct i on Regi s te r s and 25 Gen er a l Pur p os e Reg i st ers

(Figure 4-4).

For the PIC16C55, the register file is composed of 8

Special Function Registers and 24 General Purpose

Registers.

For the PIC16C57 and PIC16CR57, the register file is

compos ed of 8 Spec ial F unctio n Re gister s, 24 Ge neral

Purpose Registers and up to 48 additional General

Purpose Registers that may be addressed using a

banking scheme (Figure 4-5).

For the PIC16C58 and PIC16CR58, the register file is

compos ed of 7 Spec ial F unctio n Re gister s, 25 Ge neral

Purpose Registers and up to 48 additional General

Purpose Registers that may be addressed using a

banking scheme (Figure 4-6).

4.2.1 GENERAL PURPOSE REGISTER FILE

The register file is accessed either directly or indirectly

through the File Select Register (FSR). The FSR Reg-

ister is described in Section 4.7.

FIGURE 4-4: PIC16C54, PIC16CR54,

PIC16C55, P IC1 6C56 ,

PIC16CR56 REGISTER FILE

MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

General

Purpose

Registers

Note 1: Not a physical register. See Section 4.7.

2: PIC16C55 only, in all other devices this is

implemented as a a general purpose register .

0Fh

10h

PORTC(2)

08h

PIC16C5X

DS30453C-page 17 Preliminary  2000 Microchip Technology Inc.

FIGURE 4-5: PIC16C57/CR57 REGISTER FILE MAP

FIGURE 4-6: PIC16C58/CR58 REGISTER FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

0Fh 10h

Bank 0 Bank 1 Bank 2 Bank 3

3Fh

30h

20h

2Fh

5Fh

50h

40h

4Fh

7Fh

70h

60h

6Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

PORTC

08h

Addresses map back to

addresses in Bank 0.

Note 1: Not a physical register. See Section 4.7.

FSR<6:5> 00 01 10 11

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

0Fh 10h

Bank 0 Bank 1 Bank 2 Bank 3

3Fh

30h

20h

2Fh

5Fh

50h

40h

4Fh

7Fh

70h

60h

6Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

Addresses map back to

addresses in Bank 0.

Note 1: Not a physical register. See Section 4.7.

FSR<6:5> 00 01 10 11

PIC16C5X

DS30453C-page 18 Preliminary  2000 Microchip Technology Inc.

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions to control the opera-

tion of the device (Table 4-1).

The Special Registers can be classified into two sets.

The Special Function Registers associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

des c ribed in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

MCLR and

WDT Reset

N/A TRIS I/ O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111

N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 --11 1111

00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111

03h STATUS PA2 PA1 PA0 TO PD ZDCC0001 1xxx 000q quuu

04h FSR Indirect data memory address pointer 1xxx xxxx(3) 1uuu uuuu(3)

05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

07h(2) PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

Legend: Shaded boxes = unimplemented or unused, – = unimplement ed, read as ’0’ (if applicable)

x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5 for an explanation of how to access

these bits.

2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and

PIC16CR58.

3: For the PIC16C54 and PIC16C55, the value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is

111u uuuu.

PIC16C5X

DS30453C-page 19 Preliminary  2000 Microchip Technology Inc.

4.3 STATUS Register

This register contains the arithmetic status of the ALU,

the RESET status, and the page preselect bits for pro-

gram memories larger than 512 words.

The STATUS Register can be the destination for any

instruction, as with any other register. If the STATUS

Regis ter is the desti nation for a n instructi on that affect s

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bi ts are set or cl eared acco rding to the

device logic. Furthermore, the TO and PD bits are not

writabl e. The refore, the result of an instructi on w ith the

STATUS Re g is t er as de s ti n at i on m ay be di ffe ren t t h an

intended.

For example, CLRF STATUS will clear the upper three

bits and se t the Z bit. This le aves the STA TUS Register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and

MOVWF instruc tions be used to alter the STA T US Regis-

ter because these instructions do not affect the Z, DC

or C bits from the STATUS Register. For other instruc-

tions which do affect STATUS Bits, see Section 8.0,

Instruction Set Summary.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

PA2 PA1 PA0 TO PD Z DC C R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7 6 5 4 3 2 1 bit0

bit 7: PA2: This bit unused at this time.

Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward

compatibility with future products.

bit 6-5: PA<1:0>: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(P IC16 C58/CR5 8)

00 = Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58

01 = Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58

10 = Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58

11 = Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58

Each page is 512 words.

Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program

page preselect is not recommended since this may affect upward compatibility with future products.

bit 4: TO: Time- out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred

0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur

0 = A borrow from the 4th low order bit of the result occurred

bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Loaded with LSb or MSb, respectively

0 = A carry did not occur 0 = A borrow occurred

PIC16C5X

DS30453C-page 20 Preliminary  2000 Microchip Technology Inc.

4.4 OPTION Register

The OPTION Register is a 6-bit wide, write-only regis-

ter which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of

the W Reg ist er will be transferred to the OPTION Reg-

ister. A RESET sets the OPTION<5:0> bits.

U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1

— — T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit

U = Unimplemented bit

- n = Value at POR reset

bit7 6 5 4 3 2 1 bit0

bit 7-6: Unimplemented.

bit 5: T0CS: Timer 0 clock source sele ct bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: Tim e r0 source edge select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3: PSA: Prescaler assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to Timer0

bit 2-0: PS<2:0>: Prescaler rate select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

 2000 Microchip Technology Inc. Preliminary DS30453C-page 21

PIC16C5X

4.5 Program Counter

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next pro-

gram instruction to be executed. The PC value is

increased by one, every instruction cycle, unless an

instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The PC Latch (PCL) is

mapped to PC<7:0> (Figure 4-7 and Figure 4-8).

For the PIC16C56, PIC16CR56, PIC16C57,

PIC16CR 57, PIC16C5 8 and PIC16CR58 , a page num-

ber must be supplied as well. Bit5 and bit6 of the STA-

TUS Register provide page information to bit9 and

bit10 of the PC (Figure 4-8 and Figure 4-9).

For a CALL instruction, or any instruction where the

PCL is the destinati on, bits 7: 0 of the PC again are p ro-

vided by the instruction word. However, PC<8> does

not come from the instruction word, but is always

cleared (Figure 4-7 and Figure 4-8).

Instr uctions where the PCL is th e destinatio n, or Modif y

PCL instructions, include MOVWF PC, ADDWF PC, and

BSF PC,5.

For the PIC16C56, PIC16CR56, PIC16C57,

PIC16CR 57, PIC16C5 8 and PIC16CR58 , a page num-

ber again must be supplied. Bit5 and bit6 of the STA-

TUS Register provide page information to bit9 and

bit10 of the PC (Figure 4-8 and Figure 4-9).

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction,

all su bro uti ne ca ll s or computed jumps ar e

limited to t he first 256 locations of any pro-

gram memory page (512 words long).

FIGURE 4-7: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C54, PIC16CR54,

PIC16C55

FIGURE 4-8: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C56/PIC16CR56

87 0

PCL

PC 87 0

PCL

Reset to ’0’

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PA<1:0>

STATUS

PC 87 0

PCL

910

PA<1:0>

STATUS

PC 87 0

PCL

910

Instruction Word

Reset to ‘0’

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PIC16C5X

DS30453C-page 22 Preliminary  2000 Microchip Technology Inc.

FIGURE 4-9: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C57/PIC16CR57, AND

PIC16C58/PIC16CR58

4.5.1 PAGING CONSIDERATIONS –

PIC16C56/CR56, PIC16C57/CR57 AND

PIC16C58/CR58

If the Prog ram Counter is pointi ng to the last address of

a selected memory page, when it increments it will

cause th e progra m to con tinue i n the nex t highe r page.

However, the page preselect bits in the STATUS Reg-

ister will not be updated. Therefore, the next GOTO,

CALL or modify PCL instruction will send the program

to the page s pecified by the page pres elect bits (PA0 or

PA<1:0>).

For example, a NOP at location 1FFh (page 0) incre-

ments the PC to 200h ( page 1). A GOTO xxx at 200h

will return the program to address 0xxh on page 0

(assuming that PA<1:0> are clear).

To prevent this, the page preselect bits must be

updated under program control.

4.5.2 EFFECTS OF RESET

The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the

last page (e.g., the RESET vector).

The STATUS Register page preselect bits are cleared

upon a RESET, which means that page 0 is

pre-selected.

Therefore, upon a RESET, a GOTO instruction at the

RESET vector locatio n will automatically cause the pro-

gram to jump to page 0.

PA<1:0>

STATUS

PC 87 0

PCL

910

PA<1:0>

STATUS

PC 87 0

PCL

910

Instruction Word

Reset to ‘0’

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

4.6 Stack

PIC16C5X devices have a 10-bit or 11-bit wide,

two-level hardware push/pop stack.

A CALL instruction will push the current value of stack

1 into stack 2 and then push the current program

counter value, in cremente d by one, into stac k level 1. If

more than two sequential CALL’s are executed, only the

most recent two return addresses are stored.

A RETLW i nstruction will pop th e c ontents of sta ck level

1 into the program counter and then copy stack level 2

contents into level 1. If more than two sequential

RETLW’s are executed, the stack will be filled with the

address previously stored in level 2. Note that the

W Register will be loaded with the literal value specified

in the instruction. This is particularly useful for the

implementation of data look-up tables within the pro-

gram memory.

For the RETLW instruction, the PC is loaded with the

Top of Stack (TO S) contents. All of t he devices cov ered

in this data sh eet have a two-le vel stac k. Th e stack has

the same bit width as the device PC.

4.7 Indirect Data Addressing; INDF and

FSR Registers

The INDF Register is not a physical register.

Addressing INDF actually addresses the register

whose address is contained in the FSR Register (FSR

is a pointer). This is indi re ct addres sin g.

EXAMPLE 4-1: INDIRECT ADDRESSING

•Register file 08 contains the value 10h

•Register file 09 contains the value 0Ah

•Load the value 08 into the FSR Register

•A read of the INDF Register will return the value

of 10h

•Increment the value of the FSR Register by one

(FSR = 09h)

•A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF Register indirectly results in a

no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

movlw 0x10 ;initialize pointer

movwf FSR ; to RAM

NEXT clrf INDF ;clear INDF Register

incf FSR,F ;inc pointer

btfsc FSR,4 ;all done?

goto NEXT ;NO, clear next

CONTINUE : ;YES, continue

 2000 Microchip Technology Inc. Preliminary DS30453C-page 23

PIC16C5X

The FSR is either a 5-bit (PIC16C54, PIC16CR54,

PIC16C55), 6-bit (PIC16C56, PIC16CR56), or 7-bit

(PIC16C57s, PIC16CR57, PIC16C58, PIC16CR58)

wide register. It is used in conjunction with the INDF

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

PIC16C54, PIC16CR54, PIC16C55: These do not use

banking. FSR<6:5> bits are unimplemented and read

as ’1’s.

PIC16C57, PIC16CR57, PIC16C58, PIC16CR58:

FSR<6:5> are the bank select bits and are used to

select the bank to be addressed (00 = bank 0,

01 =bank 1, 10 = bank 2, 11 = bank 3).

FIGURE 4-10: DIRECT/INDIRECT ADDRESSING

Note 1: For register map detail see Section 4.2.

bank l ocation select

location select

bank select

Indirect Addressing

Direct Addressing

Data

Memory(1) 0Fh

10h

Bank 0 B ank 1 Bank 2 Bank 3

6(FSR)

1000 01 11

00h

1Fh 3Fh 5Fh 7Fh

(opcode) 04

(FSR)

Addresses map back to

addresses in Bank 0.

PIC16C5X

DS30453C-page 24 Preliminary  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Preliminary DS30453C-page 25

PIC16C5X

5.0 I/O PORT S

As with any other register, the I/O Registers can be

written and read und er program contro l. Howeve r , read

instructions (e.g., MOVF PORTB,W) alwa ys r ead t he I/O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are defined as input (inputs are at

hi-impedance) since the I/O control registers (TRISA,

TRISB, TRISC) are all set.

5.1 PORTA

PORTA is a 4-bi t I/O Reg ister. Only t he low order 4 bits

are used (RA<3:0>). Bits 7-4 are unimplemented and

read as '0 's .

5.2 PORTB

PORTB is an 8-bit I/O Register (PORTB<7:0>).

5.3 PORTC

PORTC is an 8-bit I/O Register for PIC16C55,

PIC16C57 and PIC16CR57.

PORTC is a General Purpose Register for PIC16C54,

PIC16CR54, PIC16C56, PIC16C58 and PIC16CR58.

5.4 TRIS Registers

The Output Driver Control R egisters are loaded with

the contents of the W Regi ster by executing the TRIS

f instruction. A '1' from a TRIS Register bit puts the

correspondi ng output drive r in a hi-impeda nce (input)

mode. A '0' puts the contents of the output data latch

on the selected pins, enabling the output buffer.

The TRIS Regi sters are “write-only” and are se t (output

drivers disabled) upon RESET.

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but t he e xt er na l s ys t em is ho l di ng i t lo w, a

read of the port will indicate that the pin is

low.

5.5 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All ports may be used for both input and

output operation. For input operations these ports are

non-latching. Any input must be present until read by

an input instruction (e.g., MOVF PORTB, W). The out-

puts are latched and remain uncha nged until th e output

latch is rewritten. To use a port pin as output, th e corre-

sponding direction control bit (in TRISA, TRISB) must

be cleared (= 0). For use a s an input, the corresponding

TRIS bit must be set. Any I/O pin can be programmed

individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note 1: I/O pins have protection diodes to VDD and VSS.

Data

Bus

CK P

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

pin(1)

Reg

Latch

RESET

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111

05h PORTA ————RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

Legend: Shaded boxes = unimplemented, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged

PIC16C5X

DS30453C-page 26 Preliminary  2000 Microchip Technology Inc.

5.6 I/O Progr amming Considerations

5.6.1 BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCF and BSF instructions, for

exampl e, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

exampl e, a BSF ope rati on o n bi t5 o f PO RTB will cause

all eight bits of POR T B t o be rea d int o the CPU , bit 5 to

be set and the POR TB val ue to be wr itten to the outp ut

latches. If another bi t of PORTB is used as a bi-direc-

tional I/O pin (say bit0) and it is defined as an input at

this tim e, the input sign al present on the p in itself would

be read into the CPU and rewritten to the data latch of

this particular pin, overwriting the previous content. As

long as the pin stays in the input mode, no problem

occurs. However, if bit0 is switched into output mode

later on, the content of the data latch may now be

unknown.

Example 5-1 shows the effect of two sequential

read-modify-write instructions (e.g., BCF, BSF , etc.) on

an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to chang e the l evel on th is pin (“wired-or”, “wired-and”).

The resulting high output currents may damage the

chip.

EXAMPLE 5-1: RE AD-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

;Initial PORT Settings

; PORTB<7:4> Inputs

; PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

; PORT latch PORT pins

; ---------- ----------

BCF PORTB, 7 ;01pp pppp 11pp pppp

BCF PORTB, 6 ;10pp pppp 11pp pppp

MOVLW 03Fh ;

TRIS PORTB ;10pp pppp 10pp pppp

;

;Note that the user may have expected the pin

;values to be 00pp pppp. The 2nd BCF caused

;RB7 to be latched as the pin value (High).

5.6.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actu al write to an I/O port happe ns at the e nd of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-2). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should

allow the pin voltage to stabilize (load dependent)

before the nex t ins truc ti on, w hi ch caus es that fil e to be

read into the CPU, is executed. Otherwise, the previous

state of that pin may be read into the CPU rather than

the new state. When in doubt, it is better to separate

these ins tru cti ons wi th a NOP or an oth er in stru cti on n ot

accessing this I/O port.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

fetched

RB<7:0>

MOVWF PORTB NOP

Port pin

sampled here

NOPMOVF PORTB,W

Instruction

executed MOVWF PORTB

(Write to

PORTB)

NOP

MOVF PORTB, W

This example shows a write

to PORTB followed by a read

from PORTB.

(Read

PORTB)

Port pin

written here

 2000 Microchip Technology Inc. Preliminary DS30453C-page 27

PIC16C5X

6.0 TIMER0 MODULE AND

TMR0 REGISTER

The Timer0 module has the following features:

•8-bit timer/counter register, TMR0

- Readable and writable

•8-bit software programmable prescaler

•Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module , while Figure 6-2 shows the elect rical stru cture

of the Timer0 input.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the Timer0 module will

increm ent ev ery ins tru cti on cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-3 and Figure 6-4).

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

incrementing edge is determined by the source edge

select bit T0SE (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external

clock input are disc ussed in de tail in Section 6.1.

The prescaler assignment is controlled in software by

the control bi t PSA (OPTION<3 >). Clearing the PSA b it

will assign the prescale r to T imer0 . The presca ler is not

readable or writable. When th e prescaler is assi gned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 6.2 details the operation

of the prescaler.

A summary of registers associated with the Timer0

module is found in Table 6-1.

Note: The prescaler may be used by either the

T imer 0 module or the W atchdog Timer , but

not both.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN

Note1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

T0CKI

T0SE(1)

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

Clocks TMR0 reg

PSout

(2 cycle delay)

PSout

Data Bus

PSA(1)

PS2, PS1, PS0(1)

Sync

VSS

RIN

Schmitt Trigger

NInput Buffer

T0CKI

Note1: ESD protection circ uits.

(1) (1)

PIC16C5X

DS30453C-page 28 Preliminary  2000 Microchip Technology Inc.

FIGURE 6-3: TI MER0 TIMING: INTERNAL CLOCK/NO PRESCALE

FIGURE 6-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

MCLR and

WDT Reset

01h TMR0 Timer0 - 8-bit real -time cloc k/counter xxxx xxxx uuuu uuuu

N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111

Legend: Shaded cells: Unimplemented bits, - = unim ple me nte d, x = unknown, u = unchanged.

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

 2000 Microchip Technology Inc. Preliminary DS30453C-page 29

PIC16C5X

6.1 Using Timer0 with an External Clock

When an external cl ock input i s used for T ime r0, it must

meet certain requir ements. The external clo ck require-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also , there is a d ela y in the actua l incr ementin g of

Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION

When no pr escal er is used, t he ex tern al clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI with the internal phase clocks is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-5).

Therefore, it is necessary for T0CKI to be high for at

least 2TOSC (and a small R C delay of 2 0 ns) and low for

at leas t 2TOSC (and a small RC delay of 20 ns). Refer to

the electrical specification of the desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type pres-

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4TOSC (and a small RC dela y of 40 ns) divided by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pu lse width requi rement of 10 ns. Refer to param-

eters 40, 4 1 an d 42 i n the electrical spec ifi ca tio n of th e

desired device.

6.1.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock ed ge occurs to th e time the T im er0 mod-

ule is actuall y increm ented. F igure 6-5 sho ws the delay

from the e xte rnal cl oc k e dge to the timer increm en tin g.

FIGURE 6-5: TI MER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

External Clock/Prescaler

Output After Sampling (3)

Prescaler Output (2)

(1)

Note1: Delay from cl ock input change to Timer0 in crement is 3Tosc to 7Tosc. (D uration of Q = Tosc). The refore,

the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

2: External clock if no prescaler selected, prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

PIC16C5X

DS30453C-page 30 Preliminary  2000 Microchip Technology Inc.

6.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer (WDT), respectively (Section 6.1.2). For simplic-

ity, this counter is being referred to as “prescaler”

througho ut this data sheet . Note tha t the pre scaler may

be used by either the Timer0 module or the WDT, but

not both. Thus, a prescaler assignment for the Timer0

module means that there is no prescaler for the WDT,

and vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1,

MOVWF 1, BSF 1,x, etc.) will clear the prescaler.

When ass igned to WDT, a CLRWDT instr uction will cle ar

the pr esca ler alo ng with the WD T. The presca ler is ne i-

ther readable nor writable. On a RESET, the prescaler

contains all '0's.

6.2.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control

(i.e., it can be changed “on the fly” during program exe-

cution). To avoid an unintended device RESET, the fol-

lowing instruction sequence (Example 6-1) must be

executed when cha nging the prescaler assignment from

Timer0 to the WDT.

EXAMPLE 6-1: CHANGIN G PRESCA LER

(TIMER0→WDT)

1.CLRWDT ;Clear WDT

2.CLRF TMR0 ;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)

4.OPTION ; are required only if

; desired

5.CLRWDT ;PS<2:0> are 000 or

;001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0 mod-

ule, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before switching

the prescaler.

EXAMPLE 6-2: CHANGIN G PRESCA LER

(WDT→TIMER0)

CLRWDT ;Clear WDT and

;prescaler

MOVLW 'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source

OPTION

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

T0CKI

T0SE

TCY ( = FOSC/4)

Sync

Cycles TMR0 reg

8-bit Prescaler

8 - to - 1MUX

MUX

Watchdog

Timer

PSA

WDT

Time-Out

PS<2:0>

Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

PSA

WDT Enable bit

Data Bus

PSA

T0CS

 2000 Microchip Technology Inc. Preliminary DS30453C-page 31

PIC16C5X

7.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits that deal with the needs of

real-time applications. The PIC16C5X family of micro-

controll ers has a host of such features intende d to max-

imize system reliability, minimize cost through

elimination of external components, provide power sav-

ing operating modes and offer code protection. These

features are:

•Oscillator selectio n

•RESET

•Power-on Reset (POR)

•Device Reset Timer (DRT)

•Watchdog Ti mer (WDT)

•SLEEP

•Code Protection

•ID locations

The PIC16C5X Family has a Watchdog Timer, which

can be shut off only through configuration bit WDTE. It

runs off of its own RC oscillator for added reliability.

There is an 18 ms delay provided by the Device Reset

Timer (DRT), intended to keep the chip in RESET until

the crystal oscillator is stable. With this timer on-chip,

most applications need no external RESET circuitry.

The SLEEP mode is designed to offer a very low cur-

rent power-down mode. The user can wake-up from

SLEEP through external RESET or through a Watch-

dog Timer time-out. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of configuration

bits are used to select various options.

7.1 Configuration Bits

Configuration bits can be programmed to select various

device configurations. Two bits are for the selection of

the oscillator type and one bit is the Watchdog Timer

enable bit. Nine bits are code protection bits

(Figure 7-1 and Figure 7-2) for the PIC16C54,

PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, and

PIC16CR58 devices.

QTP or R OM de vic es ha ve the osci lla tor c onfig ur ation

prog rammed a t the f actory a nd thes e parts ar e tested

accordingly (see "Product Identification System" dia-

grams in the back of this data sheet).

FIGURE 7-1: CONFIGURATION WORD FOR PIC16CR54A/C54C/CR54C/C 55A/ C56A/ CR56A /C57 C/

CR57C/C58B/CR58B

CP CP CP CP CP CP CP CP CP WDTE FOSC1 FOSC0 Register: CONFIG

Address(1): FFFh

bit1110987654321bit0

bit 11-3: CP: Code protection bits

1 = Code protection off

0 = Code protection on

bit 2: WDTE: Watchdog timer enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to access the

configuration word.

PIC16C5X

DS30453C-page 32 Preliminary  2000 Microchip Technology Inc.

FIGURE 7-2: CONFIGURATION WORD FOR PIC16C54/C54A/C55/C56/C57

————————CP WDTE FOSC1 FOSC0 Register: CONFIG

Address(1):FFFh

bit1110987654321bit0

bit 11-4: Unimplemented: Read as ’0’

bit 3: CP: Code protection bit.

1 = Code protection off

0 = Code protection on

bit 2: WDTE: Watchdog timer enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits(2)

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the

configuration word.

2: PIC16LV54A supports XT, RC and LP oscillator only.

PIC16LV58A supports XT, RC and LP oscillator only.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 33

PIC16C5X

7.2 Oscillator Configurations

7.2.1 OSCILLATOR TYPES

PIC16C5Xs can be operated in four different oscillator

modes. The user can program two configuration bits

(FOSC<1:0>) to select one of these four mo des :

•LP: Low Power Crystal

•XT: Crystal/Resonator

•HS: High Speed Crystal/Resonator

•RC: Resistor/Capacitor

7.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 7-3). The

PIC16C5X os cillator desi gn requires the us e of a paral-

lel cut crystal. Use of a series cut crystal may give a fre-

quency out of the cry sta l ma nufa ct urers spe ci fic ati ons .

When in XT, LP or HS modes, the device can have an

external clock source drive the OSC1/CLKIN pin

(Figure 7-4).

FIGURE 7-3: CRYSTAL OPERATION

(OR CERAMIC RESONATOR)

(HS, XT OR LP OSC

CONFIGURATION)

Note: Not all os ci ll ator select ion s av ail abl e for al l

parts. Se e Section 7.1.

Note1: See Capacit or Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen

(approx. value = 10 MΩ).

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) SLEEP

To internal

logic

RS(2)

PIC16C5X

FIGURE 7-4: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

TABLE 7-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC16C5X, PIC16CR5X

TABLE 7-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC16C5X, PIC16CR5X

Osc

Type Resonator

Freq Cap. Range

C1 Cap. Range

XT 455 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF

22-100 pF

15-68 pF

HS 4. 0 MHz

8.0 MHz

16.0 MHz

15-68 pF

10-68 pF

10-22 pF

15-68 pF

10-68 pF

10-22 pF

Note: Thes e values are fo r design guida nce only.

Since each resonator has its own charac-

teristics, the user should consult the reso-

nator manufacturer for appropriate values

of external components.

Osc

Type Resonator

Freq Cap.Range

C1 Cap. Range

LP 32 kHz(1)

100 kHz

200 kHz

15 pF

15-30 pF

15 pF

30-47 pF

15-82 pF

XT 100 kHz

200 kHz

455 kHz

1 MHz

2 MHz

4 MHz

15-30 pF

15-47 pF

200-300 pF

100-200 pF

15-100 pF

15-30 pF

15-47 pF

HS 4 MHz

8 MHz

20 MHz

15-30 pF

Note1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

2: These values are for design guidance only.

Rs may be requ ired in H S m ode , as well a s

XT mode, to avoid ove rdri vi ng cry sta ls with

low drive level specification. Since each

crystal has its own characteristics, the user

should co nsu lt the cry st al man ufa ctu rer f or

appropriate values of external components.

Note: If you change from one device to another

device , ple ase ve rify os cilla tor c haract eris -

tics in your application.

Clock from

ext. system OSC1

OSC2PIC16C5X

Open

PIC16C5X

DS30453C-page 34 Preliminary  2000 Microchip Technology Inc.

7.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be use d a s an external crys-

tal oscillator circuit. Prepackaged oscillators provide a

wide operating range and better stability. A

well-designed crystal oscillator will provide good perfor-

mance with TTL gates. Two types of crystal oscillator

circuits can be used: one with parallel resonance or

one with series resonance.

Figure 7-5 shows imple mentation of a parallel res onant

oscillator circuit. The circuit is designed to use the fun-

damental frequency of the crystal. The 74AS0 4 inverter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ters bias the 74AS04 in the linear region. This circuit

could be used for external oscill ator designs.

FIGURE 7-5: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

(USING XT, HS OR LP

OSCILLATOR MODE)

This c ircuit is also designed to use the fu ndame ntal fre-

quency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330 Ω r esisto rs prov ide th e nega tive fe ed-

back to bias the inverters in their linear region.

Note: If you change from one device to another

device , pleas e verif y osci llator c harac teris-

tics in your application.

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04 PIC16C5X

OSC1

To Other

Devices

OSC2

100k

FIGURE 7-6: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

(USING XT, HS OR LP

OSCILLATOR MODE)

7.2.4 RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the resis-

tor (REXT) and capacitor (CEXT) values, and the ope rat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also need s to take int o account

variation due to tolerance of external R and C compo-

nents used.

Figure 7-7 shows how the R/C combination is con-

nected to the PIC16C5X. For REXT values below

2.2 kΩ, the oscillator operation may become unstable,

or stop completely. For very high REXT values

(e.g., 1 MΩ) the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

REXT between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external

capaci tor (CEXT = 0 pF), we recommend using values

above 20 pF for nois e and stabi lity reas ons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or pack-

age lead frame capacitance.

Note: If you change from one device to another

devic e, pleas e verify o scill ator ch aracteri s-

tics in your application.

330

74AS04 74AS04 PIC16C5X

OSC1

To Other

Devices

XTAL

330

74AS04

0.1 µF

OSC2

100k

 2000 Microchip Technology Inc. Preliminary DS30453C-page 35

PIC16C5X

The Electrical Specification sections show RC fre-

quency variation from part to part due to normal pro-

cess variat ion.

Also, s ee the Electri cal Sp ecificat ion se ct ions for v aria-

tion of oscillator frequency due to VDD for given

REXT/CEXT values, as well as frequency variation due

to operating temperature for given R, C and VDD val-

ues.

The oscillator frequency, divided by 4, is available on

the OS C2/CLK OUT pin , and c an be use d for te st pur-

poses or to synchronize other logic.

FIGURE 7-7: RC OSCILLATOR MODE

Note: If you change from one device to another

device , pleas e verif y osci llator c harac teris-

tics in your application.

VDD

REXT

CEXT

VSS

OSC1 Internal

clock

OSC2/CLKOUT

FOSC/4

PIC16C5X

7.3 RESET

PIC16C5X dev ices may be RESET in one of the follow-

ing ways:

•Power-on Reset (POR)

•MCLR Reset (normal operation)

•MCLR Wake-up Reset (from SLEEP)

•WDT Reset (normal operation)

•WDT Wake-up Reset (from SLEEP)

Table 7-3 shows these RESET conditions for the PCL

and STATUS registers.

Some registers are not affected in any RESET condi-

tion. Their status is unknown on POR and unchanged

in any othe r RESET. Most other regist ers are reset to a

“RESET state” on Power-on Reset (POR), MCLR or

WDT Reset. A MCLR or WDT Wake-up from SLEEP

also results in a device RESET, and not a continuation

of operation before SLEEP.

The T O and P D bits (ST ATUS <4:3>) are set or cleare d

depending on the different RESET conditions

(Section 7.7). These bit s may be us ed to determ ine the

nature of the RESET.

Table 7-4 lists a full description of RESET states of all

registers. Figure 7-8 shows a simplified block diagram

of the on-chip RESET circuit.

PIC16C5X

DS30453C-page 36 Preliminary  2000 Microchip Technology Inc.

TABLE 7-3: RESET CONDITIONS FOR SPECIAL REGISTERS

TABLE 7-4: RESET CONDITIONS FOR ALL REGISTERS

FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Condition PCL

Addr: 02h STATUS

Addr: 03h

Power-on Reset 1111 1111 0001 1xxx

MCLR Reset (normal operation) 1111 1111 000u uuuu(1)

MCLR Wake-up (from SLEEP) 1111 1111 0001 0uuu

WDT Reset (normal operation) 1111 1111 0000 uuuu(2)

WDT Wake-up (from SLEEP) 1111 1111 0000 0uuu

Legend: u = unchanged, x = unknown, - = unimplemented read as ’0’.

Note1: TO and PD bits retain their last value until one of the other RESET conditions occur.

2: The CLRWDT instruction will set the TO and PD bits.

WN/A

xxxx xxxx uuuu uuuu

TRIS N/A 1111 1111 1111 1111

OPTION N/A --11 1111 --11 1111

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PCL(1) 02h 1111 1111 1111 1111

STATUS(1) 03h 0001 1xxx 000q quuu

FSR 04h 1xxx xxxx 1uuu uuuu

PORTA 05h ---- xxxx ---- uuuu

PORTB 06h xxxx xxxx uuuu uuuu

PORTC(2) 07h xxxx xxxx uuuu uuuu

General Purpose Re gister Files 07-7Fh xxxx xxxx uuuu uuuu

Legend: u = unchanged, x = unknow n, - = unimplemented, read as ’0’,

q = see tables in Section 7.7 for possible values.

Note1: See Table 7-3 for RESET value for specific conditions.

2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58.

8-bit Asynch

Ripple Counter

(Start-Up Timer)

VDD

MCLR/VPP pin

Power-up

Detect

On-Chip

RC OSC

POR (Power-on Reset )

WDT Time-out

RESET

CHIP RESET

WDT

 2000 Microchip Technology Inc. Preliminary DS30453C-page 37

PIC16C5X

7.4 Power-on Reset (POR)

The PIC16C5X family incorporates on-chip Power-on

Reset (POR) circuitry which provides an internal chip

RESET for most power-up situations. To use this fea-

ture, the user merely ties the MCLR/VPP pin to VDD. A

simplified block diagram of th e on-chip Power-on Reset

circuit is shown in Figure 7-8.

The Power-on Reset circuit and the Device Reset

Timer (Section 7.5) circuit are closely related. On

power-up, the Reset Latch is set and the DRT is

RESET. The DRT timer beg ins count ing once it det ects

MCLR to be high. After the time-out period, which is

typically 18 ms, it will reset the Reset Latch and thus

end the on-chip RESET signal.

A power-up exam ple whe re MCLR is not tied to VDD is

shown in Figure 7-10. VDD is allowed to rise and stabi-

lize before bringing MCLR high. The chip will actually

come out of RESET TDRT msec after MCLR g oes hig h.

In Figure 7-11, the on-chip Power-on Reset feature is

being used (MCLR an d VDD are tied together). The VDD

is sta ble before the start -up timer times out a nd there i s

no problem in getting a proper RESET. However,

Figure 7-12 depicts a problem situation where VDD

rises too slowly. The time between when the DRT

senses a high on the MCLR/VPP pin, and when the

MCLR/VPP pin (and VDD) act ually reac h their full valu e,

is too long. In this situation, when the start-up timer

times out, VDD has not reached the VDD (min) value and

the chip is, therefore, not guaranteed to function cor-

rectl y . For such situa tions, we recommend that external

(RESET) BOR circuits or external RC circuits be used

to achieve longer POR delay times (Figure 7-9).

For more information on PIC16C5X POR, see

Power-Up Considerations - AN522 in the Embedded

Control Handbook.

The POR circuit does not produce an internal RESET

when VDD declines.

Note: When the device starts normal operation

(exits the RESET condition), device oper-

ating p ara meters (voltage, frequ en cy, tem-

perature, etc.) must be met to ensure

operation. If these conditions are not met,

the dev ice must be held in RESET unti l the

operating conditions are met.

FIGURE 7-9: EXAMPLE OF EXTERNAL

POWER-ON RESET CIRCUIT

(FOR SLOW VDD POWER-UP)

MCLR

PIC16C5X

VDDVDD

•External Power-on Reset circuit is required

only if VDD power-up is too slow. The diode D

helps dischar ge the capacitor quickly when

VDD powers down.

•R < 40 kΩ is reco mm end ed to make sure that

voltage drop across R does not violate the

device electrical specification.

•R1 = 100Ω to 1 kΩ will limit any current flow-

ing into M CLR from external capac itor C in the

even t of MCLR pin breakdown due to Electro-

static D ischa rge (ESD ) or Electrical Over -

stress (EOS).

PIC16C5X

DS30453C-page 38 Preliminary  2000 Microchip Technology Inc.

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)

FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TI ME

FIGURE 7-12: TIME-OUT SEQUENCE O N POWER-UP (MCLR TIED TO VDD): SLOW VDD RIS E TIME

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

When VDD ris e s sl ow ly, the TDRT time-out expires long before VDD has reached its final value. In

this example, the chip will RESET properly if, and only if, V1 ≥ VDD min.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 39

PIC16C5X

7.5 Device Reset Timer (DRT)

The Device Reset Timer (DRT) provides a fixed 18 ms

nominal time-out on RESET. The DRT operates on an

internal RC oscillator. The processor is kept in RESET

as long as the DRT is active. The DRT delay allows VDD

to rise above VDD min., and for the oscillator to stabi-

lize.

Oscil lator c ircuits based on crystals or ceramic reson a-

tors requi re a certa in time after power -up to establ ish a

stable o scillati on. The on-c hip DR T keeps th e device in

a RESET condition for approximately 18 ms after the

voltage on the MCLR/VPP pin has reache d a lo gic high

(VIH) level. Thus, external RC networks connected to

the MCLR input are not required in most cases, allow-

ing for sa vings in c ost-sensiti ve and/or s pace restricte d

applications.

The Device Reset time delay will vary from device to

devi ce due to VDD, temper ature, and process variatio n.

See AC parameters for details.

The D RT w ill also be tri ggered upon a Watchdog T im er

time-out. This is particularly important for applications

using the WDT to wake the PIC16C5X from SLEEP

mode automatically.

7.6 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC osci llator whic h does not requ ire any extern al com-

ponents. This RC oscillator is separate from the RC

oscillator of the OSC1/CLKIN pin. That means that the

WDT wil l run even if th e clo ck o n the OSC1/CLKI N an d

OSC2/CLKOUT pins have been stopped, for example,

by execution of a SLEEP instruction. During normal

operation or SLEEP, a WDT Reset or Wake-up Reset

generates a device RESET.

The T O bit (STA TUS<4> ) will be cleared upon a W atch-

dog Timer Reset.

The WDT can be permanently disabled by program-

ming the configuration bit WDTE as a ’0’ (Section 7.1).

Refer to the PIC16C5X Programming Specifications

(Literature Number DS30190) to determine how to

access the configuration word.

7.6.1 WDT PERIOD

The WDT ha s a nomin al time -out perio d of 18 ms (wi th

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by writ-

ing to the OPTION register. Thus, a time-out period of

a nominal 2.3 seconds can be realized. These periods

vary with temperature, VDD and part-to-part process

variations (see DC specs).

Under w orst c ase co ndi tions (V DD = Min., Temperature

= Max., max. WDT prescaler), it may take several sec-

onds before a WDT time-out occurs.

7.6.2 WDT PROGRAMMING CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

post scaler , if assign ed to the WDT, and p revents it from

timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the

post scaler, if assigned to the WDT. This gi ves th e max -

imum SLEEP time before a WDT Wake-up Reset.

PIC16C5X

DS30453C-page 40 Preliminary  2000 Microchip Technology Inc.

FIGURE 7-13: WATC HDOG TIMER BLOCK DIAGRAM

TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address Na me Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

MCLR and

WDT Reset

N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111

Legend: Shaded boxes = Not used by Watchdog Timer, - = unimplemented, read as '0', u = unchanged

From TMR0 Clock Source

To TMR0

Postscaler

WDT Enable

EPROM Bi t

PSA

WDT

Time-out

PS<2:0>

PSA

MUX

8 - to - 1 MUX

Postscaler

Watchdog

Timer

Note: T0CS, T0SE, PSA, PS<2:0>

are bits in the OPTION register.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 41

PIC16C5X

7.7 Time-Out Sequence and Power-down

Status Bits (TO/PD)

The TO and PD bits in the STATUS register can be

tested to determine if a RESET condition has been

caused by a power-up co nditio n, a MCL R or W atc hdog

Timer (WDT) Reset, or a MCLR or WDT Wake-up

Reset.

These STATUS bits are only affected by events listed

in Table 7-7.

Table 7-3 lists the RESET conditions for the Special

Function Registers, while Table 7-4 lists the RESET

conditions for all the registers.

TABLE 7-6: TO/PD ST ATUS AFTER

RESET

TO PD RESET was caused by

Power-up (POR)

MCLR Reset (norm al operation) (1)

MCLR Wake-up Reset (from SLEEP)

WDT Reset (normal operation)

WDT Wake-up Reset (from SLEEP)

Legend: u = unchanged

Note1: The TO and PD bits maintain their status

(u) until a RESET occurs. A low-pulse on

the MCLR input does not change the TO

and PD sta tus bits.

TABLE 7-7: EVENTS AFFECTING TO/PD

STATUS BITS

Event TO PD Remarks

Power-up 11

WDT Time- out 0u

No effect on PD

SLEEP instruction 10

CLRWDT instruction 11

Legend: u = unchanged

Note: A WDT time-out will occur regardless of

the status of the TO bit. A SLEEP instruc-

tion will be executed, regardless of the sta-

tus of the PD bit.

7.8 RESET on Brown-Out

A brown-out is a condition where device power (VDD)

dips bel ow its m inimum val ue, but not to z ero, and the n

recovers. The device should be reset in the event of a

brown-out.

To reset PIC16C5X devices when a brown-out occurs,

external brown-out protection circuits may be built, as

shown in Figure 7-14 and Figure 7-15.

FIGURE 7-14: BROWN-OUT PROTECTION

CIRCUIT 1

FIGURE 7-15: BROWN-OUT PROTECTION

CIRCUIT 2

This circuit will activate RESET when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

33k

10k

40k

VDD

MCLR

PIC16C5X

VDD

This br own -out c irc uit is les s ex pe ns ive , alth ou gh

less accurate. T ransistor Q1 turns off when VDD is

below a certain level such that:

VDD •R1

R1 + R2 = 0.7V

R2 40k

VDD

MCLR

PIC16C5X

VDD

PIC16C5X

DS30453C-page 42 Preliminary  2000 Microchip Technology Inc.

FIGURE 7-16: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 3

7.9 Power-down Mode (SLEEP)

A device may be powered down (SLEEP) and later

powered up (wake-up from SLEEP).

7.9.1 SLEEP

The Power-down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR/VPP pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level.

7.9.2 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. An external RESET input on MCLR/VPP pin.

2. A W atchdog Timer time-out RESET (if WDT was

enabled).

Both of these events cause a device RESET. The TO

and PD bits can be used to determine the cause of

device RESET. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The WDT is cleared when the device wakes from

SLEEP, regardless of the wake-up source.

This brown-out protection circuit employs Micro-

chip Technology’s MCP80 9 microcontroller supe r-

visor. The MCP8XX and MCP1XX families of

supervisors provide push-pull and open collector

outputs with both "active high and active low"

RESET pins. Th ere are 7 dif ferent trip point se lec-

tions to accommodate 5V and 3V systems.

MCLR

PIC16C62X

VDD

Vss

RST

MCP809

VDD

bypass

capacitor VDD

7.10 Program Verification/Code Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verification purposes.

7.11 ID Locations

Four memo ry lo catio ns are des ignat ed as ID locations ,

where the user can store checksum or other

code-identification numbers. These locations are not

accessible during normal execution but are readable

and writab le duri ng prog ram /verify.

Use on ly the lowe r 4 bits of the ID locations and alw ays

program the upper 8 bits as ’1’s.

Note: Microchip does not recommend code pro-

tecting w ind owed devices.

Note: Microchip will assign a unique pattern

number for QTP and SQTP requests and

for ROM devices. This pattern number will

be unique and traceable to the submitted

code.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 43

PIC16C5X

8.0 INSTRUCTION SET SUMMARY

Each PIC16C5X instruction is a 12-bit word divided into an

OPCODE, which specifies the instruction type, and one or

more ope rands whic h further sp ecify the oper ation of the

instruction. The PIC16C5X instruction set summary in

Table 8-2 groups the instructions into byte-oriented, bit-ori-

ented, and li tera l and contr ol op eratio ns. Tab le 8-1 sho ws

the opcode field descriptions.

For byte-oriented instructions, ’f’ represents a file register

designator and ’d’ represents a destination designator . The

file re gi ste r des ign ator i s us ed to spe cif y wh ich on e o f the

32 file registers in that bank is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ’d’ is ’0’, the result is

placed in the W register. If ’d’ is ’1’, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ’b’ represents a bit field

design ator which selec ts th e n um ber of the bi t affected

by the operati on , while ’f’ represents the number of the

file in which the bit is located.

For literal and control operations, ’k’ represents an

8 or 9-bit constant or literal value.

TABLE 8-1: OPCODE FIELD

DESCRIPTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

Don’t care location (= 0 or 1)

The assembler will generate code with x = 0. It is

the recommended form of use for compatibility

with all Microchip software tools.

Destination select;

d = 0 (store result in W)

d = 1 (store result in file register ’f’)

Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

WDT Watchdog Timer Counter

TO Time-out bit

PD Power-down bit

dest Destination, either the W register or the specified

[ ] Options

( ) Contents

→Assigned to

< > Register bit field

∈In the set of

italics User defined term (font is courier)

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles.

One in struction cycle consists of four o scillat or periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time would be 1 µs. If a condi-

tional test is true or the program counte r is c han ge d as

a resu lt o f an ins tru cti on, the instruction ex ec uti on tim e

would be 2 µs.

Figure 8-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal

number:

0xhhh

where ’h’ signifies a hexadecimal digit.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

11 6 5 4 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7 5 4 0

OP C O DE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations - GOTO i nst ruct io n

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

PIC16C5X

DS30453C-page 44 Preliminary  2000 Microchip Technology Inc.

TABLE 8-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles

12-Bit Opcode Status

Affected NotesMSb LSb

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f,d

–

f, d

–

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Incr eme nt f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

Exclusive OR W with f

1(2)

0001

0000

0010

0000

0010

0011

0001

0010

0000

0011

0000

0011

0001

11df

01df

011f

0100

01df

11df

10df

11df

00df

001f

0000

01df

00df

10df

ffff

0000

ffff

0000

ffff

C,DC,Z

None

C,DC,Z

None

1,2,4

2,4

1,4

2,4

1,2,4

2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

0100

0101

0110

0111

bbbf

ffff

None

2,4

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

XORLW

–

AND literal with W

Call subroutine

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

Exclusive OR Literal to W

1110

1001

0000

101k

1101

1100

0000

1000

0000

1111

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0100

kkkk

0010

kkkk

0011

0fff

kkkk

None

TO, PD

None

TO, PD

None

Note1: The 9th bit of the program c ounter will be forced to a ’0’ by any instruction that writes to the PC except for

GOTO. (See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Regis-

ters)

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that

value pre sent on the pins themse lves . For exampl e, if the dat a lat ch is ’1’ for a pi n confi gured as inp ut and is

driven lo w by an external device, the data will be written back with a ’0’.

3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate

latches of POR TA or B respectively. A ’1’ fo rces t he pin t o a hi-i mpeda nce s tate and disab les th e outpu t buf f-

ers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

 2000 Microchip Technology Inc. Preliminary DS30453C-page 45

PIC16C5X

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Encoding: 0001 11df ffff

Description: Add the contents of the W register and

in the W register . If ’d’ is ’1’ the result is

stored back in register ’f’.

Words: 1

Cycles: 1

Example: ADDWF FSR, 0

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W = 0xD9

FSR = 0xC2

ANDLW And literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W).AND. (k) → (W)

Status Affected: Z

Encoding: 1110 kkkk kkkk

Description: The contents of the W register are

AND’ed with the eight-bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example: ANDLW 0x5F

Before Instruction

W= 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Encoding: 0001 01df ffff

Description: The contents of the W register are

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

'1' the result is stored back in register 'f'.

Words: 1

Cycles: 1

Example: ANDWF FSR, 1

Before Instruc tio n

W =0x17

TEMP_R EG = 0xC2

After Instruction

W =0x17

TEMP_ REG = 0x2

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 0100 bbbf ffff

Description: Bit 'b' in register 'f' is cleared.

Words: 1

Cycles: 1

Example: BCF FLAG_REG, 7

Before Instruc tio n

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

PIC16C5X

DS30453C-page 46 Preliminary  2000 Microchip Technology Inc.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 0101 bbbf ffff

Description: Bit ’b’ in register ’f’ is se t.

Words: 1

Cycles: 1

Example: BSF FLAG_REG, 7

Before Instruction

FLAG_R EG = 0x0A

After Instruction

FLAG_R EG = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 0110 bbbf ffff

Description: If bit ’b’ in register ’f’ is 0 then the next

instruction is skipped.

If bit ’b’ is 0 then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a

2-cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address (HERE)

After Instruction

if FLAG<1> = 0,

PC = address (TRUE);

if FLAG<1> = 1,

PC = address(FALSE)

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 0111 bbbf ffff

Description: If bit ’b’ in register ’f’ is ’1’ then the next

instruction is skipped.

If bit ’b’ is ’1’, then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a

2-cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE •

•

Before Instruc tio n

PC = address (HERE)

After Instruction

If FLAG<1> = 0,

PC = address (FALSE);

if FLAG<1> = 1,

PC = address (TRUE)

 2000 Microchip Technology Inc. Preliminary DS30453C-page 47

PIC16C5X

CALL Subroutine Call

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 255

Operation: (PC) + 1→ Top of Stack;

k → PC<7:0>;

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: None

Encoding: 1001 kkkk kkkk

Description: Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from

STATUS<6:5>, PC<8> is cleared.

CALL is a two-cycle instruction.

Words: 1

Cycles: 2

Example: HERE CALL THERE

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS= address (HERE + 1)

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 31

Operation: 00h → (f);

1 → Z

Status Affected: Z

Encoding: 0000 011f ffff

Description: The contents of register ’f’ are cleared

and the Z bit is set.

Words: 1

Cycles: 1

Example: CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00

Z=1

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W);

1 → Z

Status Affected: Z

Encoding: 0000 0100 0000

Description: The W register is cleared. Zero bit (Z)

is set.

Words: 1

Cycles: 1

Example: CLRW

Before Instruc tio n

W = 0x5A

After Instruction

W = 0x00

Z=1

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0100

Description: The CLRWDT instruction resets the

WDT. It also resets the prescaler , if the

prescaler is assigned to the WDT and

not T imer0. Status bits TO and PD are

set.

Words: 1

Cycles: 1

Example: CLRWDT

Before Instruc tio n

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT prescale = 0

TO =1

PD =1

PIC16C5X

DS30453C-page 48 Preliminary  2000 Microchip Technology Inc.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 0010 01df ffff

Description: The contents of register ’f’ are comple-

mented. If ’d’ is 0 the result is stored in

the W register. If ’d’ is 1 the result is

stored back in register ’f’.

Words: 1

Cycles: 1

Example: COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W=0xEC

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – 1 → (dest)

Status Affected: Z

Encoding: 0000 11df ffff

Description: Decrement register ’f’. If ’d’ is 0 the

result is stored in the W register . If ’d’ is

1 the result is stored back in register ’f’.

Words: 1

Cycles: 1

Example: DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – 1 → d; skip if result = 0

Status Affected: None

Encoding: 0010 11df ffff

Description: The contents of register ’f’ are decre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

If the result is 0, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead making

it a two-cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruc tio n

PC = address (HERE)

After Instruction

CNT = CNT - 1;

if CNT = 0,

PC = address (CONTINUE);

if CNT ≠0,

PC = address (HERE+1)

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 511

Operation: k → PC<8:0>;

STATUS<6:5> → PC<10:9>

Status Affected: None

Encoding: 101k kkkk kkkk

Description: GOTO is an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS<6:5>. GOTO is a

two-cycle instruction.

Words: 1

Cycles: 2

Example: GOTO THERE

After Instruction

PC = address (THERE)

 2000 Microchip Technology Inc. Preliminary DS30453C-page 49

PIC16C5X

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) + 1 → (dest)

Status Affected: Z

Encoding: 0010 10df ffff

Description: The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

Words: 1

Cycles: 1

Example: INCF CNT, 1

Before Instruction

CNT = 0xFF

Z=0

After Instruction

CNT = 0x00

Z=1

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Encoding: 0011 11df ffff

Description: The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and a NOP is executed instead

making it a two-cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT + 1;

if CNT = 0,

PC = address (CONTINUE);

if CNT ≠0,

PC = address (HERE +1)

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. (k) → (W)

Status Affected: Z

Encoding: 1101 kkkk kkkk

Description: The contents of the W register are

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example: IORLW 0x35

Before Instruc tio n

W = 0x9A

After Instruction

W= 0xBF

Z=0

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W).OR. (f) → (dest)

Status Affected: Z

Encoding: 0001 00df ffff

Description: Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example: IORWF RESULT, 0

Before Instruc tio n

RESULT = 0x13

W = 0x91

After Instruction

RESULT = 0x13

W = 0x93

Z=0

PIC16C5X

DS30453C-page 50 Preliminary  2000 Microchip Technology Inc.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 0010 00df ffff

Description: The contents of register ’f’ is moved to

destination ’d’. If ’d’ is 0, destination is

the W register . If ’d’ is 1, the destination

is file register ’f’. ’d’ is 1 is useful to test

a file register since status flag Z is

affected.

Words: 1

Cycles: 1

Example: MOVF FSR, 0

After Instruction

W = value in FSR register

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Encoding: 1100 kkkk kkkk

Description: The eight bit literal ’k’ is loaded into the

W register. The don’t cares will assem-

ble as 0s.

Words: 1

Cycles: 1

Example: MOVLW 0x5A

After Instruction

W = 0x5A

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 31

Operation: (W) → (f)

Status Affected: None

Encoding: 0000 001f ffff

Description: Move data from the W register to regis-

ter 'f'.

Words: 1

Cycles: 1

Example: MOVWF TEMP_REG

Before Instruc tio n

TEMP_REG = 0xFF

W = 0x4F

After Instruction

TEMP_REG = 0x4F

W = 0x4F

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operati on: No operati on

Status Affected: None

Encoding: 0000 0000 0000

Descr ipti on : N o ope rati on.

Words: 1

Cycles: 1

Example: NOP

 2000 Microchip Technology Inc. Preliminary DS30453C-page 51

PIC16C5X

OPTION Load OPTION Register

Syntax: [ label ] OPTION

Operands: None

Operation: (W) → OPTION

Status Affected: None

Encoding: 0000 0000 0010

Description: The content of the W register is loaded

into the OPTION register.

Words: 1

Cycles: 1

Example OPTION

Before Instruction

W = 0x07

After Instruction

OPTION = 0x07

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 1000 kkkk kkkk

Description: The W register is loaded with the eight

bit literal ’k’. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example:

TABLE

CALL TABLE ;W contains

;table offset

;value.

• ;W now has table

• ;value.

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 0011 01df ffff

Description: The contents of register ’f’ are rotated

one bit to the left through the Carry

Flag. If ’d’ is 0 the result is placed in the

W register . If ’d’ is 1 the result is stored

back in register ’f’.

Words: 1

Cycles: 1

Example: RLF REG1,0

Before Instruc tio n

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W=1100 1100

C=1

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 0011 00df ffff

Description: The contents of register ’f’ are rotated

one bit to the right through the Carry

Flag. If ’d’ is 0 the result is placed in the

W register . If ’d’ i s 1 t he result is placed

back in register ’f’.

Words: 1

Cycles: 1

Example: RRF REG1,0

Before Instruc tio n

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W=0111 0011

C=0

Cregister ’f’

PIC16C5X

DS30453C-page 52 Preliminary  2000 Microchip Technology Inc.

SLEEP Enter SLEEP Mode

Syntax: [label]SLEEP

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler;

1 → TO;

0 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0011

Description: Time-out status bit (TO) is set. The

power-down status bit (PD) is cleared.

The WDT and its prescaler are

cleared.

The processor is put into SLEEP mode

with the oscillator stopped. See sec-

tion on SLEEP for more details.

Words: 1

Cycles: 1

Example: SLEEP

SUBWF Subtract W from f

Syntax: [label] SUBWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – (W) → (dest)

Status Affected: C, DC, Z

Encoding: 0000 10df ffff

Description: Subtract (2’s complement method) the

W register from register 'f'. If 'd' is 0 the

result is stored in the W register . If 'd' is

1 the result is stored back in register 'f'.

Words: 1

Cycles: 1

Example 1:SUBWF REG1, 1

Before Instruc tio n

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C = 1 ; result is positiv e

Example 2:

Before Instruc tio n

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C = 1 ; result is zero

Example 3:

Before Instruc tio n

REG1 = 1

W=2

C=?

After Instruction

REG1 = FF

W=2

C = 0 ; result is negative

 2000 Microchip Technology Inc. Preliminary DS30453C-page 53

PIC16C5X

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected: None

Encoding: 0011 10df ffff

Description: The upper and lower nibbles of register

’f’ are exchanged. If ’d’ is 0 the result is

placed in W register . If ’d’ is 1 the result

is placed in register ’f’.

Words: 1

Cycles: 1

Example SWAPF REG1, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W = 0X5A

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operands: f = 5, 6 or 7

Operation: (W) → TRIS register f

Status Affected: None

Encoding: 0000 0000 0fff

Description: TRIS register ’f’ (f = 5, 6, or 7) is loaded

with the contents of the W register.

Words: 1

Cycles: 1

Example TRIS PORTA

Before Instruction

W=0XA5

After Instruction

TRISA = 0XA5

XORLW Exclusive OR literal with W

Syntax: [label]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 1111 kkkk kkkk

Description: The contents of the W register are

XOR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruc tio n

W= 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Encoding: 0001 10df ffff

Description: Exclusive OR the contents of the W

result is stored in the W register . If 'd' is

1 the result is stored back in register 'f'.

Words: 1

Cycles: 1

Example XORWF REG,1

Before Instruc tio n

REG = 0xAF

W=0xB5

After Instruction

REG = 0x1A

W=0xB5

PIC16C5X

DS30453C-page 54 Preliminary  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Preliminary DS30453C-page 55

PIC16C5X

9.0 DEV ELOP ME NT SUPPORT

The PICmicro® microcontrollers are supported with a

full ran ge of hardware a nd softwa re develo pment to ols:

•Integrated Development Environment

- MPLAB® IDE Software

•Assemblers/Compilers/Linkers

- MPASM Assembler

- MPLAB-C17 and MPLAB-C18 C Compilers

- MPLINK/MPLIB Linker/Librarian

•Simulators

- MPLAB-SIM Software Simulator

•Emulators

- MPLAB-ICE Real-Time In-Circuit Emulator

- ICEPIC™

•In-Circuit Debugger

- MPLAB-ICD for PIC16F87

•Device Programmers

-PRO MATE

 II Universal Programmer

- PICSTART Plus Entry-L evel Proto typ e

Programmer

•Low-Cost Demonstration Boards

- PICDEM-1

- PICDEM-2

- PICDEM-3

- PICDEM-17

-K

EELOQ

9.1 MPLAB Integrated Develo pment

Environme n t Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a Windows-based applica-

tion whic h con tai ns:

•Multiple functionality

-editor

- simulator

- programmer (sold separat ely)

- emulator (sold separately)

•A full featured editor

•A project manager

•Customizable tool bar and key mapping

•A status bar

•On-line help

MPLA B allows you to:

•Edit your source files (eithe r assembly o r ‘C’)

•One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

proje ct info rma tio n)

•Debug us ing :

- source files

- absolute listi ng file

- object code

The ability to use MPLAB with Microchip’s simulator,

MPLAB-SI M, a ll ows a co ns is ten t pl atfo rm a nd the abil-

ity to easily switch from the cost-effective simulator to

the full featured emulator with minimal retraining.

9.2 MPASM Assembler

MP ASM is a full featured universal macro assembler for

all PICmicro MCU’s. It can produce absolute code

directly in the form of HEX files for device program-

mers, or it can generate relocatable objects for

MPLINK.

MPASM has a command line interface and a Windows

shell and c an be u sed a s a stand alone appli catio n o n a

Windows 3.x or greater system. MPASM generates

relocatable object files, Intel standard HEX files, MAP

files to detail memory usage and symbol reference, an

absolute LST file which con t ai ns so urce li nes an d gen-

erated machine code, and a COD file for MPLAB

debugging.

MPASM features include:

•MPASM and MPLINK are integrated into MPLAB

projects.

•MPASM allows user defined m acros to b e created

for streamlined assembly.

•MPASM allows cond iti ona l as se mbly for multi pur-

pose source files.

•MP ASM directives allow complete control over the

assembly process.

9.3 MPLAB-C17 and MPLAB- C18

C Compilers

The MPLAB- C17 and MP LAB-C18 Code De velop ment

Systems are complete ANSI ‘C’ compilers and inte-

grated development environments for Microchip’s

PIC17CXXX and PIC18CXXX family of microcontrol-

lers, respectively. These compilers provide powerful

integration capabilities and ease of use not found with

other co mpi le r s.

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

PIC16C5X

DS30453C-page 56 Preliminary  2000 Microchip Technology Inc.

9.4 MPLINK/MPLIB Linker/Librarian

MPLINK is a relocatable linker for MPASM and

MPLAB-C17 and MPLAB-C18. It can link relocatable

objects from assembly or C source files along with pre-

compiled libraries using directives from a linker script.

MPLIB is a librarian for pre-compiled code to be used

with MPLINK. When a routine from a library is called

from another so urce file, only the modules that contains

that routine will be linked in with the application. This

allows large libraries to be used efficiently in many dif-

ferent applications. MPLIB manages the creation and

modification of library files.

MPLINK feat ures incl ude:

•MPLINK works with MPASM and MPLAB-C17

and MPLAB-C18.

•MPLINK allows all memory are as to be d efined as

sections to provide link-time flexibility.

MPLIB features incl ud e:

•MPLIB ma ke s l in kin g e as ier because sing le librar-

ies can be included instead of many smaller files.

•MPLIB help s keep co de mainta inable by grouping

related modules together.

•MPLIB commands allow libraries to be created

and modules to be added, listed, replaced,

deleted, or extracted.

9.5 MPLAB-SIM Software Simulator

The MPLAB-SIM Software Simulator allows code

development in a PC host environment by simulating

the PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file or user-defined key press to any of the pins. The

execution can be performed in single step, execute until

break, or trace mode.

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-

ware Simulator offers the flexibility to develop and

debug code outside of the laboratory environment mak-

ing it an excellent multi-project software development

tool.

9.6 MPLAB-ICE High Pe rformance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB-ICE Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro micro contro lle rs (MCUs). Soft ware co ntro l of

MPLAB-ICE is provided by the MPLAB Integrated

Devel op ment Env iron me nt (IDE ), whi ch al lo ws edi tin g,

“make” and download, and source debugging from a

single en v iron ment.

Interchangeable processor modules allow the system

to be easily reconfigured for emulation of different pro-

cessors. The universal architecture of the MPLAB-ICE

allows expansion to support new PICmicro microcon-

trollers.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive devel-

opment tools. The PC platform and Microsoft® Windows

3.x/95/98 environment were chosen to best make these

features available to you, the end user.

MPLAB-ICE 2000 is a full-featured emulator system

with enhanced trace, trigger, and data monitoring fea-

tures. Both systems use the same processor modules

and will operate across the full operating speed range

of the PICmicro MCU.

9.7 ICEPIC

ICEPIC is a low-cost in-circuit emulation solution for the

Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X, a nd PIC16 CXXX f amilies of 8-bi t one-t ime-

programmable (OTP) microcontrollers. The modular

system can support different subsets of PIC16C5X or

PIC16CXXX products through the use of interchange-

able personality modules or daughter boards. The

emulator is capable of emula ting without target applica-

tion circuitry being present.

9.8 MPLAB-ICD In-Circuit Debugger

Microchip’s In-Circuit De bugger , MPLAB-ICD, is a p ow-

erful, low-cost run-time development tool. This tool is

based on the flash PIC16F877 and can be used to

develop for this and other PICmicro microcontrollers

from the PIC16CXXX family. MPLAB-ICD utilizes the

In-Circuit Debugging capability built into the

PIC16F8 7X. This featu re, along with Microchip ’s In-Cir-

cuit Serial Programming protocol, offers cost-effective

in-circuit flash programming and debugging from the

graphical user interface of the MPLAB Integrated

Developm en t Environment. This enabl es a desi gn er to

develop and debug sou rce code by watchin g variables,

single-stepping and setting break points. Running at

full speed enables testing hardware in real-time. The

MPLAB-ICD is also a programmer for the flash

PIC16F87X family.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 57

PIC16C5X

9.9 PRO MATE II Universal Programmer

The P RO MATE II Univer sal Pr ogram mer is a f ull- fea-

tured programmer capable of operating in stand-alone

mode as w el l as PC -h ost ed m od e. PRO M ATE II is CE

compliant.

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for ma xi mum r e li abi lity. It has

an LCD display for instructions and error messages,

keys to enter commands and a modular detachable

socket assembly to support various package types. In

stand-al one mo de the P RO MATE II can read, verif y or

program PICmicro devices. It can also set code-protect

bits in this mode.

9.10 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

progra mmer si mpl e and efficient.

PICSTART Plus supports all PICmicro devices with up

to 40 pins. Larger pin count devices such as the

PIC16C92X, and PIC17C76X may be supported with

an adapter socket. PICSTART Plus is CE compliant.

9.11 PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test firm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE emulator and downlo a d th e

firmware to the emulator for testing. Additional proto-

type area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

9.12 PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PI C S TART - P l u s , an d e a s i l y t e s t f i rm w a r e .

The MPLAB-ICE emulator may also be used with the

PICDEM-2 boa rd to te st firmware. Additional p r oto typ e

area has been provided to the user for adding addi-

tional ha rdware and connecti ng it to the m icrocontr oller

socket(s). Some of the features inc lude a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

usage o f the I2C b us and s eparate he aders for c onnec-

tion to an LCD module and a keypad.

9.13 PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microc ont roll ers w ith a LCD Mod ule. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test firmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test firm-

ware. Additi onal p rototyp e are a has bee n provide d to

the user fo r addin g hardwa re and con necti ng it to th e

microcontroller socket(s). Some of the features include

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a keypad. Als o provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day o f the we ek. The PICDEM -3 pr ovides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplexed LCD signals on a PC. A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

PIC16C5X

DS30453C-page 58 Preliminary  2000 Microchip Technology Inc.

9.14 PICDEM-17

The PICDEM-17 is an evaluation board that demon-

strates the capabilities of several Microchip microcon-

trollers, including PIC17C752, PIC17C756,

PIC17C762, and PIC17C766. All necessary hardware

is inc luded to run ba sic demo p rograms, wh ich are sup-

plied on a 3.5-inch disk. A programmed sample is

includ ed, and the user ma y erase it and prog ram it with

the other sample programs using the PRO MATE II or

PICSTART Pl us devi ce progr ammers and eas ily debu g

and t est the sample code. In addi tion, PICDEM-17 su p-

ports do wn-loading of p rograms to an d executing out of

external FLASH memory on board. The PICDEM-17 is

also usabl e with the MPLAB -ICE or PICMASTER em u-

lator, and all of the sample programs can be run and

modified using either emulator. Additionally, a gener-

ous prototype area is available for user hardware.

9.15 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS eva l-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 59

PIC16C5X

TABLE 9-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12CXXX

PIC14000

PIC16C5X

PIC16C6X

PIC16CXXX

PIC16F62X

PIC16C7X

PIC16C7XX

PIC16C8X

PIC16F8XX

PIC16C9XX

PIC17C4X

PIC17C7XX

PIC18CXX2

24CXX/

25CXX/

93CXX

HCSXXX

MCRFXXX

MCP2510

Software Tools

MPLAB®

Integrated

Development Environment

MPLAB® C17 Compiler

MPLAB® C18 Compiler

MPASM/MPLINK

Emulators

MPLAB®-ICE

ICEPIC



Low-Cost

In-Circuit Emulator

Debugger

MPLAB®-ICD In-Circuit

Debugger

Programmers

PICSTART



Plus

Low-Cost Universal Dev. Kit

PRO MATE



Universal Programmer

Demo Boards and Eval Kits

PICDEM-1

†

PICDEM-2

†

PICDEM-3

PICDEM-14A

PICDEM-17

OQ®

Evaluation Kit

Transpon der Kit

microID™ Programmer’s Kit

125 kHz microID Developer’s Kit

125 kHz Anticollision microID

Developer’s Kit

13.56 MHz Anticollision microID

Developer’s Kit

MCP2510 CAN Developer’s Kit

* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB®-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77

** Contact Microchip Technology Inc. for availability date.

†

Development tool is available on select devices.

PIC16C5X

DS30453C-page 60 Preliminary  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Preliminary DS30453C-page 61

PIC16C54/55/56/57 PIC16C5X

10.0 ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57

Absolute Maximum Ratings†

Ambient Temperature under bias...........................................................................................................–55°C to +125°C

Storage Temperature.............................................................................................................................–65°C to +150°C

Voltage on VDD with respec t to VSS ............................................................................................................... 0V to +7.5V

Voltage on MCLR with respect to VSS(2)......................................................................................................... 0V to +14V

Voltage on al l other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

Total Power Dissipation(1) ....................................................................................................................................800 mW

Max. Current out of VSS pin ........................................................................................................................... .......150 mA

Max. Current into VDD pin .....................................................................................................................................100 mA

Max. Current into an input pin (T0CKI only) ....................................................................................................................±500 µA

Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

Output Clamp Current, IOK (VO < 0 or VO > VDD)............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................20 mA

Max. Output Current sourced by a single I/O port (PORTA, B or C).......................................................................40 mA

Max. Output Current sunk by a single I/O port (PORTA, B or C)............................................................................50 mA

Note 1: Power Dissipation is calculated as follows: Pd is = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

2: V oltage spikes below VSS at the MCLR pin, ind ucing currents gre ater than 80 mA, may cause lat ch-up. Thus,

a series resistor of 50 to 100 Ω should be used when applying a “low” level to the MCLR pin rather than

pulling this pin directly to VSS.

†NOTICE: Stresses abov e t hos e lis te d u nde r “Maximum Ratings” may cause perm anent da ma ge to the devi ce. This

is a stre ss ra ting o nly a nd funct ional operati on of the d evice at th ose o r an y oth er con dition s abo ve th ose i ndica ted in

the operation listings of this specificati on is not implie d. Exposure to ma ximum rati ng conditio ns for extended peri ods

may affect device reliability.

PIC16C5X PIC16C54/55/56/57

DS30453C-page 62 Preliminary  2000 Microchip Technology Inc.

10.1 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)

DC Characteristics

Power Supply Pins Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage

PIC16C5X-RC

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

PIC16C5X-LP

VDD 3.0

3.0

4.5

2.5

—

6.25

5.5

6.25

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 20 MHz

FOSC = DC to 40 kHz

RAM Data Retention Voltage(2) VDR 1.5* —V Device in SLEEP Mode

VDD Start Voltage to ensure

Power-on Reset VPOR VSS —V See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for de tails on

Power-on Reset

Supply Current(3)

PIC16C5X-RC(4)

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

PIC16C5X-LP

IDD —

—

1.8

4.8

9.0

3.3

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

Power-down Current(5) IPD —

—4.0

0.6 12

9µA

µAVDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

Note1: Data in the T ypical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type , bus rate, inte rnal code executio n pattern and temp erature also hav e an impact on the

current co nsumptio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 63

PIC16C54/55/56/57 PIC16C5X

10.2 DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)

DC Characteristics

Power Supply Pins Standard Operating Conditions (unless otherwise specified)

Operating Temperatur e –40°C ≤ TA ≤ +85°C

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage

PIC16C5X-RCI

PIC16C5X-XTI

PIC16C5X-10I

PIC16C5X-HSI

PIC16C5X-LPI

VDD 3.0

3.0

4.5

2.5

—

6.25

5.5

6.25

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 20 MHz

FOSC = DC to 40 kHz

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for details on

Power-on Reset

Supply Current(3)

PIC16C5X-RCI(4)

PIC16C5X-XTI

PIC16C5X-10I

PIC16C5X-HSI

PIC16C5X-LPI

IDD —

—

1.8

4.8

9.0

3.3

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

Power-down Current(5) IPD —

—4.0

0.6 14

12 µA

µAVDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

Note1: Data in the T ypical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type , bus rate, inte rnal code executio n pattern and temp erature also hav e an impact on the

current co nsumptio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

PIC16C5X PIC16C54/55/56/57

DS30453C-page 64 Preliminary  2000 Microchip Technology Inc.

10.3 DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)

DC Characteristics

Power Supply Pins Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C

Characteristic Sym Min Typ (1) Max Units Conditions

Supply Voltage

PIC16C5X-RCE

PIC16C5X-XTE

PIC16C5X-10E

PIC16C5X-HSE

PIC16C5X-LPE

VDD 3.25

3.25

4.5

2.5

—

6.0

5.5

6.0

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 16 MHz

FOSC = DC to 40 kHz

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Reset

VDD rise rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for de tails on

Power-on Reset

Supply Current(3)

PIC16C5X-RCE(4)

PIC16C5X-XTE

PIC16C5X-10E

PIC16C5X-HSE

PIC16C5X-LPE

IDD —

—

1.8

4.8

9.0

3.3

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 16 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.25V,

WDT disabled

Power-down Current(5) IPD —

—5.0

0.8 22

18 µA

µAVDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

* These parameters are characterized but not tested.

Note1: Data in the T ypical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type , bus rate, inte rnal code executio n pattern and temp erature also hav e an impact on the

current co nsumptio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 65

PIC16C54/55/56/57 PIC16C5X

10.4 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)

PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)

DC Characteristics

All Pins Except

Power Supply Pins

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (indus tria l)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and

Section 10.3.

Characteristic Sym Min Typ(1) Max Units Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIL VSS

VSS

—

0.2 VDD

0.15 VDD

0.3 VDD

Pin at hi-impeda nce

PIC16C5X-RC only(4)

PIC16C5X-XT, 10, HS, LP

Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIH 0.45 VDD

2.0

0.36 VDD

0.85 VDD

0.7 VDD

—

VDD

For all VDD(5)

4.0V < VDD ≤ 5.5V(5)

VDD > 5.5V

PIC16C5X-RC only(4)

PIC16C5X-XT, 10, HS, LP

Hysteresis of Schmitt

Trigger inputs VHYS 0.15VDD*—— V

Input Leakage Current(2,3)

I/O ports

MCLR

T0CKI

OSC1

IIL –1

–5

–3

0.5

µA

For VDD ≤ 5.5V

VSS ≤ VPIN ≤ VDD,

Pin at hi-impeda nce

VPIN = VSS + 0.25V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

PIC16C5X-XT, 10, HS, LP

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

Output High Voltage

I/O ports(3)

OSC2/CLKOUT

VOH VDD – 0.7

VDD – 0.7 —

——

—V

VIOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

* These parameters are characterized but not tested.

Note1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified

levels repr esent norma l operating c onditions . Higher leaka ge current ma y be measured at di ffe rent input vol t-

age.

3: Negative current is defined as coming out of the pin.

4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

5: The user may use the better of the two specifications.

PIC16C5X PIC16C54/55/56/57

DS30453C-page 66 Preliminary  2000 Microchip Technology Inc.

10.5 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Extended)

DC Characteristics

All Pins Except

Power Supply Pins

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and

Section 10.3.

Characteristic Sym Min Typ(1) Max Units Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIL Vss

Vss

—

0.15 VDD

0.3 VDD

Pin at hi-impedance

PIC16C5X-RC only(4)

PIC16C 5X-XT, 10, HS, LP

Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIH 0.45 VDD

2.0

0.36 VDD

0.85 VDD

0.7 VDD

—

VDD

For all VDD(5)

4.0V < VDD ≤ 5.5V(5)

VDD > 5.5 V

PIC16C5X-RC only(4)

PIC16C 5X-XT, 10, HS, LP

Hysteresis of Schmitt

Trigger inputs VHYS 0.15VDD*——V

Input Leakage Current (2,3)

I/O ports

MCLR

T0CKI

OSC1

IIL –1

–5

–3

0.5

µA

For VDD ≤ 5.5 V

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

PIC16C 5X-XT, 10, HS, LP

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

Output High Voltage

I/O ports(3)

OSC2/CLKOUT

VOH VDD – 0.7

VDD – 0.7 —

——

—V

VIOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

* These parameters are characterized but not tested.

Note1: Data in the T ypical (“Typ”) column is based on characterization re sults at 25°C. This data is for design guidance

only and is not tested.

2: The leakag e current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is defined as coming out of the pin.

4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

5: The user may use the better of the two specifications.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 67

PIC16C54/55/56/57 PIC16C5X

10.6 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase subscripts (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O po rt wdt watchdog timer

Uppercase letters and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

FIGURE 10-1: LOAD CONDITIONS - PIC16C54/55/56/57

VSS

Pin CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes wh en extern al clo ck

is used to drive OSC1

PIC16C5X PIC16C54/55/56/57

DS30453C-page 68 Preliminary  2000 Microchip Technology Inc.

10.7 Timing Diagrams and Specifications

FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics Standard Operating Conditions (unless otherwis e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

FOSC External CLKIN Frequency(2) DC —4MHzXT osc mode

DC —10 MHz 10 MHz mode

DC —20 MHz HS os c mode (Com/Indust)

DC —16 MHz HS osc mode (Extended)

DC —40 kHz LP osc mode

Oscill ator Frequency(2) DC —4 MHz RC osc mode

0.1 —4MHzXT osc mode

4—10 MHz 10 MHz mode

4—20 MHz HS os c mode (Com/Indust)

4—16 MHz HS osc mode (Extended)

DC —40 kHz LP osc mode

* These parameters are characterized but not tested.

Note1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless oth erwise st ated. The se param eters are for desi gn

guidance only and are not tested.

2: All speci fied va lu es are based on chara ct eriz ati on data for that particula r oscillator type under s tan dard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruct ion cycle period (TCY) equals four times the input oscillator time base period.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

 2000 Microchip Technology Inc. Preliminary DS30453C-page 69

PIC16C54/55/56/57 PIC16C5X

1TOSC External CLKIN Period(2) 250 ——ns XT osc mode

100 ——ns 10 MHz mode

50 ——ns HS osc mode (Com/Indust)

62.5 ——ns HS osc mode (Extended)

25 ——µsLP osc mode

Oscill ator Perio d(2) 250 ——ns RC osc mode

250 —10,000 ns XT osc mode

100 —250 ns 10 MHz mode

50 —250 ns HS osc mode (Com/Indust)

62.5 —250 ns HS osc mode (Extended)

25 ——µsLP osc mode

CY Instructi on Cycle Time(3) —4/FOSC ——

3 TosL, TosH Clock in (OSC1 ) Low or High

Time 85* ——ns XT oscillator

20* ——ns HS oscillator

2* ——µs LP oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall

Time —— 25* ns XT oscil la tor

—— 25* ns HS oscillator

—— 50* ns LP oscillator

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 (CON’T)

AC Characte ristic s Standard Operating Conditions (unle ss other wis e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

* These parameters are characterized but not tested.

Note1: Data in the Typi cal (“Typ”) column is at 5.0V, 25°C unless othe rwise st ated. The se param eters are for desi gn

guidance only and are not tested.

2: All speci fied va lu es are based on chara ct eriz ati on data for that particula r os ci lla tor ty pe und er s tan dard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruct ion cycle period (TCY) equals four times the input oscillator time base period.

PIC16C5X PIC16C54/55/56/57

DS30453C-page 70 Preliminary  2000 Microchip Technology Inc.

FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57

TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and

Section 10.3

Parameter

No. Sym Characteristic Min Typ(1) Max Units

10 TosH2ckL OSC1↑ to CLKOUT↓(2) —15 30** ns

11 TosH2ckH OSC1↑ to CLKOUT↑(2) —15 30** ns

12 TckR CLKOUT rise time(2) —515**ns

13 TckF CLKOUT fall time(2) —515**ns

14 TckL2ioV CLKOUT↓ to Port out valid(2) ——40** ns

15 TioV2ckH Port in valid before CLKOUT↑(2) 0.25 TCY+30* ——ns

16 TckH2ioI Port in hold after CLKOUT↑(2) 0* ——ns

17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(3) ——100* ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time) TBD ——ns

19 TioV2osH Port input valid to OSC1↑

(I/O in setup time) TBD ——ns

20 TioR Port output rise time(3) —10 25** ns

21 TioF Port output fall time(3) —10 25** ns

* These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note1: Data in the Typical ( “Typ”) colum n is at 5.0V, 25°C unless othe rwise stat ed. The se pa ramete rs are for de sign

guidance only and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 10-1 for loading conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

12 16

Old Value New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 71

PIC16C54/55/56/57 PIC16C5X

FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -

PIC16C54/55/56/57

TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (ex tend ed )

Operating Voltage VDD range is described in Section 10.1, Sect ion 10.2 and Section 10.3

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

30 TmcL MCLR Pulse Width (low) 100* ——ns VDD = 5.0V

31 Twdt Watchdog Timer Time-out Period

(No Prescaler) 9* 18* 30* ms VDD = 5.0V ( Comme rcial)

32 TDRT Device Reset Timer Period 9* 18* 30* ms VDD = 5.0V (Commercial)

34 TioZ I/O Hi-impedance from MCLR Low ——100* ns

* These parameters are char acterized but n ot te sted.

Note1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O pin

32 32

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

PIC16C5X PIC16C54/55/56/57

DS30453C-page 72 Preliminary  2000 Microchip Technology Inc.

FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57

TABLE 10-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57

AC Char ac te ristics Standard O pera t in g Co nditions (unless otherwise speci fie d)

Operat in g Temperatu re 0°C ≤ TA ≤ +7 0°C (com mercia l)

–40°C ≤ TA ≤ +8 5°C (industrial)

–40°C ≤ TA ≤ +1 25°C (e xt en de d)

Operating Voltage VDD range i s de s cri be d in Se ction 10.1, Sec ti on 10.2 a nd

Section 10.3

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

40 Tt0H T0CKI High Pulse Width- No Prescaler 0.5 TCY + 20* ——ns

- With Pre s ca le r 1 0* ——ns

41 Tt0L T0CKI Lo w Pu ls e Wi dth- No Pres c al er 0.5 TCY + 20* ——ns

- With Pre s ca le r 1 0* ——ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N ——ns Whichever is greater.

N = Prescale Value

(1, 2, 4 ,. .., 256)

* These pa ramet ers are ch arac teriz ed but not t ested.

Note 1: Data i n t he Typical (“Typ”) co lu m n i s at 5. 0V, 25°C u nl es s o the rw i se st at ed . T he se p ara me te rs are for design

guidanc e on ly and a re no t te s ted.

T0CKI

40 41

 2000 Microchip Technology Inc. Preliminary DS30453C-page 73

PIC16C54/55/56/57 PIC16C5X

11.0 DC AND AC CHARACTERISTICS - PIC16C54/55/56/57

The grap hs and t ables pro vided i n this s ection a re for des ign guid ance and are not t ested. In some g raphs or tables , the

data pr esente d is outside speci fied ope rating ran ge (e. g., outsi de specifi ed VDD range). This is for informa tion onl y and

devices will operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)

respectively, where σ is standard deviation.

FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

TABLE 11-1: RC OSCILLATOR FREQUENCIES

CEXT REXT Average

FOSC @ 5 V, 25°C

20 pF 3.3 k 4.973 MHz ± 27%

5 k 3.82 MHz ± 21%

10 k 2.22 MHz ± 21%

100 k 262.15 kHz ± 31%

100 pF 3.3 k 1 .63 MHz ± 13%

5 k 1.19 MHz ± 13%

10 k 684.64 kHz ± 18%

100 k 71.56 kHz ± 25%

300 pF 3.3 k 660 kHz ± 10%

5.0 k 484.1 kHz ± 14%

10 k 267.63 kHz ± 15%

160 k 29.44 kHz ± 19%

The frequencies are measured on DIP packages.

The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is ±3 standard deviations from the average value for VDD = 5 V.

FOSC

FOSC (25°C)

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

01020253040506070

T(°C)

Frequency normalized to +25°C

VDD = 5.5 V

VDD = 3.5 V

REXT ≥ 10 kΩ

CEXT = 100 pF

0.88

PIC16C5X PIC16C54/55/56/57

DS30453C-page 74 Preliminary  2000 Microchip Technology Inc.

FIGURE 11-2: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

CEXT = 20 PF

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

OSC

(MHz)

R = 3.3k

R = 5k

R = 10k

R = 100k

Measured on DIP Packages, T = 25°C

FIGURE 11-3: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

CEXT = 100 PF

FIGURE 11-4: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

CEXT = 300 PF

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

OSC

(MHz)

R = 3.3k

R = 5k

R = 10k

R = 100k

Measured on DIP Packages, T = 25°C

800

700

600

500

400

300

200

100

3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

OSC

(kHz)

R = 3.3k

R = 5k

R = 10k

R = 100k

Measured on DIP Packages, T = 25°C

 2000 Microchip Technology Inc. Preliminary DS30453C-page 75

PIC16C54/55/56/57 PIC16C5X

FIGURE 11-5: TYPICAL IPD vs. VDD,

WATC HDOG DISABLED

FIGURE 11-6: MAXIMUM IPD vs. VDD,

WATC HDOG DISABLED

2.5

2.0

1.5

1.0

0.5

0.02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(

VDD (Volts)

T = 25°C

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(µA)

VDD (Volts)

6.5 7.0

100

+85°C

0°C

–40°C

–55°C

+125°C

+70°C

FIGURE 11-7: TYPICAL IPD vs. VDD,

WA TCHDOG ENABLED

FIGURE 11-8: MAXIMUM IPD vs. VDD,

WA TCHDOG ENABLED

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(

VDD (Volts)

T = 25°C

+70°C

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(

VDD (Volts) 6.5 7.0

+85°C

–40°C

–55°C

+125°C

0°C

IPD, with WDT enabled, has two components:

The leakage current, which increases with higher tempera-

ture, and the operating current of the WDT logic, which

increases with lower temperature. At –40°C, the latter domi-

nates explaining the apparently anomalous behavior.

PIC16C5X PIC16C54/55/56/57

DS30453C-page 76 Preliminary  2000 Microchip Technology Inc.

FIGURE 11-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD

FIGURE 11-10: VIH, VIL OF M CLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD

FIGURE 11-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT

(IN XT, HS, AND LP MODES) vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Vo lts )

Min (–40°C to +85°C)

0.80

0.60 5.5 6.0

Max (–40°C to +85°C)

Typ (+25°C)

(Volts)

3.5

3.0

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Vo lts)

0.5

0.0 5.5 6.0

, V

(Volts)

4.0

4.5

min (–40°C to +85°C)

max (–40°C to +85°C)

typ +25°C

min (–40°C to +85°C)

max (–40°C to +85°C)

typ +25°C

Note: These input pins have Schmitt Trigger input buffers.

2.4

2.2

2.0

1.8

1.6

1.4

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

1.2

1.0 5.5 6.0

Typ (+25°C)

(Volts)

2.6

2.8

3.0

3.2

3.4

Max (–40°C to +85°C)

Min (–40°C to +85°C)

 2000 Microchip Technology Inc. Preliminary DS30453C-page 77

PIC16C54/55/56/57 PIC16C5X

FIGURE 11-12: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK, 25°C)

FIGURE 11-1 3: MAXIMU M IDD vs. FR EQUENCY (EXTERNAL CLOCK, –40°C TO +85°C)

10k 100k 1M 10M 100M

0.01

0.1

1.0

(mA)

External C lock Freq uency (Hz)

5.0

4.5

4.0

2.5

3.0

3.5

5.5

6.0

6.5

7.0

10k 100k 1M 10M 100M

0.01

0.1

1.0

(mA)

External Clock Frequency (Hz)

5.0

4.5

4.0

3.5

5.5

6.0

6.5

7.0

2.5

3.0

PIC16C5X PIC16C54/55/56/57

DS30453C-page 78 Preliminary  2000 Microchip Technology Inc.

FIGURE 11-1 4: MAXIMU M IDD vs. FR EQUENCY (EXTERNAL CLOCK –55°C TO +125°C)

10k 100k 1M 10M 100M

0.01

0.1

1.0

(mA)

Extern al Clo ck Frequency (Hz)

5.0

4.5

4.0

2.5

3.0

3.5

5.5

6.0

6.5

7.0

FIGURE 11-15: WD T TIMER TIME-OUT

PERIOD vs. VDD FIGURE 11-16: TRANSCONDUCTANCE (gm)

OF HS OSCILLATOR vs. VDD

5234567

VDD (Volts)

WDT peri od (ms)

Max +85°C

Max +70°C

Typ +25°C

MIn 0°C

MIn –40°C

9000

8000

7000

6000

5000

4000

3000

2000

100

0234567

VDD (Volts)

gm (

A/V)

Min +85°C

Max –40°C

Typ +25°C

 2000 Microchip Technology Inc. Preliminary DS30453C-page 79

PIC16C54/55/56/57 PIC16C5X

FIGURE 11-17: TRAN SCONDUC TANCE (gm)

OF LP OSCILLATOR vs. VDD

FIGURE 11-18: IOH vs. VOH, VDD = 3 V

0234567

VDD (Volts)

gm (

A/V)

Min +85°C

Max –40°C

Ty p +25°C

–5

–10

–15

–20

–250 0.5 1.0 1.5 2.0 2.5

VOH (Volts)

(mA)

Min +85°C

3.0

Typ +25°C

Max –40°C

FIGURE 11-19: TRANSCONDUCTANCE (gm)

OF XT OSCILLATOR vs. VDD

FIGURE 11-20: IOH vs. VOH, VDD = 5 V

2500

2000

1500

1000

500

0234567

VDD (Volts)

gm (

A/V)

Min +85°C

Max –40°C

Typ +25°C

–10

–20

–30

–401.5 2.0 2.5 3.0 3.5 4.0

VOH (Volts)

(mA)

Min +85°C

Max –40°C

4.5 5.0

Typ +25°C

PIC16C5X PIC16C54/55/56/57

DS30453C-page 80 Preliminary  2000 Microchip Technology Inc.

FIGURE 11-21: IOL vs. VOL, VDD = 3 V

TABLE 11-2: INPUT CAPACITANCE FOR

PIC16C54/56

Pin Typical Capacitance (pF)

18L PDIP 18L SOIC

RA port 5.0 4.3

RB port 5.0 4.3

MCLR 17.0 17.0

OSC1 4.0 3.5

OSC2/CLKOUT 4.3 3.5

T0CKI 3.2 2.8

All capacitance values are typical at 25°C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

0.0 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

(mA)

Min +85°C

Max –40°C

Typ +25°C

3.0

FIGURE 11-22: IOL vs. VOL, VDD = 5 V

TABLE 11-3: INPUT CAPACITANCE FOR

PIC16C55/57

Typical Capacitance (pF)

28L PDIP

(600 mil) 28L SOIC

RA port 5.2 4.8

RB port 5.6 4.7

RC port 5. 0 4.1

MCLR 17.0 17.0

OSC1 6.6 3.5

OSC2/CLKOUT 4.6 3.5

T0CKI 4.5 3.5

All capacitance values are typical at 25°C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

00.00.51.01.52.02.5

VOL (Volts)

(mA)

Min +85°C

Max –40°C

Typ +25°C

3.0

 2000 Microchip Technology Inc. Preliminary DS30453C-page 81

PIC16CR54A PIC16C5X

12.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A

Absolute Maximum Ratings†

Ambient Temperature under bias...........................................................................................................–55°C to +125°C

Storage Temperature.............................................................................................................................–65°C to +150°C

Voltage on VDD with respec t to VSS ..................................................................................................................0 to +7.5V

Voltage on MCLR with respect to VSS(2)............................................................................................................0 to +14V

Voltage on al l other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

Total Power Dissipation(1) ....................................................................................................................................800 mW

Max. Current out of VSS pin ........................................................................................................................... .......150 mA

Max. Current into VDD pin .......................................................................................................................................50 mA

Max. Current into an input pin (T0CKI only) ....................................................................................................................±500 µA

Input Clamp Current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA

Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................20 mA

Max. Output Current sourced by a single I/O port (PORTA or B) ...........................................................................40 mA

Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................50 mA

Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

2: V olta ge spikes below Vss at the MCLR pin, inducing cu rrents greater than 80 mA ma y cause latch-up . Thus,

a series resistor o f 50 to 100Ω sho uld be u sed when ap plying a l ow level to th e MCLR pi n rather than pulling

this pin directly to Vss.

†NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a s tress rating only and funct ional op eration of th e dev ice at tho se or any other co nditio ns ab ove t hose indi-

cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C5X PIC16CR54A

DS30453C-page 82 Preliminary  2000 Microchip Technology Inc.

12.1 DC Characteristics: PIC16CR54A-04, 10, 20 (Commercial)

PIC16CR54A-04I, 10I, 20I (Industrial)

DC Characteristics

Power Supply Pins

Standard Operating Conditi ons (unle ss otherw is e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (co mmercia l)

–40°C ≤ TA ≤ +85°C (indus tria l)

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage

RC and XT options

HS option

VDD 2.5

4.5 6.25

5.5 V

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for details on

Power-on Reset

Supply Current(3)

RC(4) and XT options

HS option

IDD 2.0

0.8

4.8

9.0

3.6

1.8

350

µA

FOSC = 4.0 MHz, VDD = 6.0V

FOSC = 4.0 MHz, VDD = 3.0V

FOSC = 200 kHz, VDD = 2.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

Power-down Current(5)

Commercial IPD

1.0

2.0

3.0

5.0

6.0

8.0*

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

Power-down Current(5)

Industrial IPD

1.0

2.0

3.0

5.0

8.0

10*

20*

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 4.0V, WDT enabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) col umn is based on characterization resu lts at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type, bus rate, interna l code executio n pattern and temperatu re also have an impac t on the

current co nsumptio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 83

PIC16CR54A PIC16C5X

12.2 DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)

DC Characteristics

Power Supply Pins Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (extended)

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage

RC, XT and LP options

HS options

VDD 3.25

4.5 —

—6.0

5.5 V

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for details on

Power-on Reset

Supply Current(3)

RC(4) and XT options

HS option

IDD —

—

1.8

4.8

9.0

3.3

FOSC = 4.0 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 16 MHz, VDD = 5.5V

Power-down Current(5) IPD —

—5.0

0.8 22

18 µA

µAVDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

PIC16C5X PIC16CR54A

DS30453C-page 84 Preliminary  2000 Microchip Technology Inc.

12.3 DC Characteristics: PIC16LCR54A-04 (Commercial)

PIC16LCR54A-04I (Industrial)

DC Characteristics

Power Supply Pins

Standard Operating Conditi ons (unle ss otherw is e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (co mmercia l)

–40°C ≤ TA ≤ +85°C (indus tria l)

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage VDD 2.0 —6.25 V LP Option

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for details on

Power-on Reset

Supply Current(3) IDD —10 20

70 µA

µAFOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 6.0V

Power-down Current(5)

Commercial IPD

—

1.0

2.0

3.0

5.0

6.0

8.0*

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

Power-down Current(5)

Industrial IPD

—

1.0

2.0

3.0

5.0

8.0

10*

20*

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 4.0V, WDT enabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) col umn is based on characterization resu lts at 25 °C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 85

PIC16CR54A PIC16C5X

12.4 DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)

PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)

DC Characteristics

All Pins Except

Power Supply Pins

Standard Operating Conditions (unless otherwise specified)

Operati ng Temperatu re 0°C ≤ TA ≤ +70°C (commercial )

–40°C ≤ TA ≤ +85°C (industrial)

Operati ng Voltage VDD range is described in Section 12.1 and Section 12.3.

Characteristic Sym Min Typ(1) Max Units Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIL VSS

VSS

—

0.2 VDD

0.15 VDD

Pin at hi-impedance

RC option only(4)

XT, HS and LP options

Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIH 2.0

0.6 VDD

0.85 VDD

—

VDD

VDD = 3.0V to 5.5V(5)

Full VDD range(5)

RC option only(4)

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs VHYS 0.15VDD*—— V

Input Leakage Current(3)

I/O ports

MCLR

T0CKI

OSC1

IIL –1.0

–5.0

–3.0

0.5

+1.0

+5.0

+3.0

µA

For VDD ≤ 5.5V

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25V (2)

VPIN = VDD(2)

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL —

——

—0.5

0.5 V

VIOL = 10 mA, VDD = 6.0V

IOL = 1.9 mA, VDD = 6.0V,

RC option only

Output High Voltage(3)

I/O ports

OSC2/CLKOUT

VOH VDD –0.5

VDD –0.5 —

——

—V

VIOH = –4.0 mA, VDD = 6.0V

IOH = –0.8 mA, VDD = 6.0V,

RC option only

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) column is based on characterization results at 25°C. This data is for design guidanc e

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is defined as coming out of the pin.

4: For the RC option, the OSC1/CLKIN pi n is a Schmitt T rigg er input. It is not recomme nded that the PIC 16C5X

be driven with external clock in RC mode.

5: The user may use the better of the two specifications.

PIC16C5X PIC16CR54A

DS30453C-page 86 Preliminary  2000 Microchip Technology Inc.

12.5 DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)

DC Characteristics

All Pins Except

Power Supply Pins

Standard Operating Conditi ons (unle ss otherw is e speci fied)

Operating Temperature –40°C ≤ TA ≤ +125°C

Operating Voltage VDD range is described in Section 12.2.

Characteristic Sym Min Typ(1) Max Units Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIL Vss

Vss

—

0.15 VDD

0.3 VDD

Pin at hi-impedance

RC option only(4)

XT, HS and LP options

Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIH 0.45 VDD

2.0

0.36 VDD

0.85 VDD

0.7 VDD

—

VDD

For all VDD(5)

4.0V < VDD ≤ 5.5V(5)

VDD > 5.5V

RC option only(4)

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs VHYS 0.15VDD*—— V

Input Leakage Current(3)

I/O ports

MCLR

T0CKI

OSC1

IIL –1.0

–5.0

–3.0

0.5

+1.0

+5.0

+3.0

µA

For VDD ≤ 5.5V

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25V(2)

VPIN = VDD(2)

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC option only

Output High Voltage (3)

I/O ports

OSC2/CLKOUT

VOH VDD –0.7

VDD –0.7 —

——

—V

VIOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

RC option only

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) colum n is bas ed on cha racterization results at 25 °C. Th is data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is defined as coming out of the pin.

4: For the RC option , the OSC1/C LKIN pin is a Schmitt Trigger input. It is not recom mend ed that the PIC16C5X

be driven with external clock in RC mode.

5: The user may use the better of the two specifications.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 87

PIC16CR54A PIC16C5X

12.6 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

F Frequency T Time

Lowercase subscripts (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O po rt wdt watchdog timer

Uppercase letters and their meanings:

FFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

FIGURE 12-1: LOAD CONDITIONS

VSS

Pin CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

options when external clock

is used to drive OSC1

PIC16C5X PIC16CR54A

DS30453C-page 88 Preliminary  2000 Microchip Technology Inc.

12.7 Timing Diagrams and Specifications

FIGURE 12-2: EXTERNAL CLOCK TIMING - PIC16CR54A

TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A

AC Characteristics Standard Operating Conditions (unless otherwis e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3.

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

FOSC External CLKIN Frequency(2) DC —4.0 MHz XT osc mode

DC —4.0 MHz H S osc mode (04)

DC —10 MHz HS osc mode (10)

DC —20 MHz HS osc mode (20)

DC —200 kHz LP osc mode

Oscill ator Frequency(2) DC —4.0 MHz RC osc mode

0.1 —4.0 MHz XT osc mode

4.0 —4.0 MHz HS osc mode (04)

4.0 —10 MHz HS osc mode (10)

4.0 —20 MHz HS osc mode (20)

5.0 —200 kHz LP osc mode

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parame ters are for design

guidance only and are not tested.

2: All speci f ie d v al ues a re b as ed on ch arac terization data fo r that particular os cil la tor t yp e u nde r s tandard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruct ion cycle period (TCY) equals four times the input oscillator time base period.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

 2000 Microchip Technology Inc. Preliminary DS30453C-page 89

PIC16CR54A PIC16C5X

1TOSC External CLKIN Period(2) 250 ——ns XT osc mod e

250 ——ns HS osc mode (04)

100 ——ns HS osc mode (10)

50 ——ns HS osc mode (20)

5.0 ——µsLP osc mode

Oscill ator Perio d(2) 250 ——ns RC osc mode

250 —10,00

0ns XT osc mode

250 —250 ns HS osc mode (04)

100 —250 ns HS osc mode (10)

50 —250 ns HS osc mode (20)

5.0 —200 µsLP osc mode

CY Instructi on Cycle Time(3) —4/FOS

C——

3 TosL, TosH Clock in (OSC1 ) Low or High

Time 50* ——ns XT oscilla tor

20* ——ns HS oscillator

2.0* ——µs LP oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall

Time ——25* ns XT oscillator

——25* ns HS oscillator

——50* ns LP oscillator

TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A (CON’T)

AC Characte ristic s Standard Operating Conditions (unle ss other wis e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3.

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parame ters are fo r design

guidance only and are not test ed.

2: All speci f ie d v al ues a re b as ed on ch arac terization data fo r that particular os cil la tor t yp e u nde r s tandard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruct ion cycle period (TCY) equals four times the input oscillator time base period.

PIC16C5X PIC16CR54A

DS30453C-page 90 Preliminary  2000 Microchip Technology Inc.

FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16CR54A

TABLE 12-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 12.1, Section 12.2 and

Section 12.3.

Parameter

No. Sym Characteristic Min Typ(1) Max Units

10 TosH2ckL OSC1↑ to CLKOUT↓(2) —15 30** ns

11 TosH2ckH OSC1↑ to CLKOUT↑(2) —15 30** ns

12 TckR CLKOUT rise time(2) —5.0 15** ns

13 TckF CLKOUT fall time(2) —5.0 15** ns

14 TckL2ioV CLKOUT↓ to Port out valid(2) ——40** ns

15 TioV2ckH Port in valid before CLKOUT↑(2) 0.25 TCY+30* ——ns

16 TckH2ioI Port in hold after CLKOUT↑(2) 0* ——ns

17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(3) ——100* ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time) TBD ——ns

19 TioV2osH Port input valid to OSC1↑

(I/O in setup time) TBD ——ns

20 TioR Port output rise time(3) —10 25** ns

21 TioF Port output fall time(3) —10 25** ns

* These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parame ters are for design

guidance only and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 12-1 for loading conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

20, 21

Old Value New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

19 12

 2000 Microchip Technology Inc. Preliminary DS30453C-page 91

PIC16CR54A PIC16C5X

FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A

TABLE 12-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (ex tend ed )

Operating Voltage VDD range is described in Section 12.1, Sect ion 12.2 and Section 12.3 .

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

30 TmcL MCLR Pulse Wid th (low) 1.0* ——µsVDD = 5.0V

31 Twdt Watchdog Timer Time-out Period

(No Prescaler) 7.0* 18* 40* ms VDD = 5.0V (Commer cial)

32 TDRT Device Reset Timer Period 7.0* 18* 30* ms VDD = 5.0V (Commercial)

34 TioZ I/O Hi-impedance from MCLR Low ——1.0* µs

* These parameters are char acterized but n ot te sted.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parame ters are fo r design

guidance only and are not test ed.

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O pin

32 32

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

PIC16C5X PIC16CR54A

DS30453C-page 92 Preliminary  2000 Microchip Technology Inc.

FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16CR54A

TABLE 12-4: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operati ng Temperatu re 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +8 5°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 12.1, Section 12.2 and

Section 12.3.

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

40 Tt0H T0CKI High Pulse Width- No Prescaler 0.5 TCY + 20* ——ns

- With Prescaler 10* ——ns

41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* ——ns

- With Prescaler 10* ——ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N ——ns Whichever is greater.

N = Pre scale Value

(1, 2, 4,..., 256)

* These parameters are char acterized but n ot te sted.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parame ters are for design

guidance only and are not tested.

T0CKI

40 41

 2000 Microchip Technology Inc. Preliminary DS30453C-page 93

PIC16C54A PIC16C5X

13.0 ELECTRICAL CHARACTERISTICS - PIC16C54A

Absolute Maximum Ratings†

Ambient temperature under bias............................................................................................................–55°C to +125°C

Storage temperature............................................................................................................................. –65°C to +150°C

Voltage on VDD with respec t to VSS ..................................................................................................................0 to +7.5V

Voltage on MCLR with respect to VSS ...............................................................................................................0 to +14V

Voltage on al l other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

Total power dissipation(1) .....................................................................................................................................800 mW

Max. current out of VSS pin.......... ...... ..... ...... ..... ...................................................................................................150 mA

Max. current into VDD pin......................................................................................................................................100 mA

Max. current into an input pin (T0C KI onl y).....................................................................................................................±500 µA

Input clamp current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

Output clamp cur rent, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA

Max. output current sunk by any I/O pin .................................................................................................................25 mA

Max. output current sourced by any I/O pin............................................................................................................20 mA

Max. output current sourced by a single I/O port (PORTA or B).............................................................................50 mA

Max. output current sunk by a single I/O port (PORTA or B) ..................................................................................50 mA

Note 1: Power dissipation is calcu la ted as fol low s : Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a s tres s ra ting onl y an d fu nctional operatio n of th e de vi ce at those or any oth er co nd itio ns abo ve those in di -

cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C5X PIC16C54A

DS30453C-page 94 Preliminary  2000 Microchip Technology Inc.

13.1 DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)

PIC16C54A-04I, 10I, 20I (Industrial)

DC Character ist ics

Power Supply Pins

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage

XT, RC and LP options

HS option

VDD 3.0

4.5 —

—6.25

5.5 V

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD start voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Rese t

VDD rise rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for details on

Power-on Rese t

Supply Current(3)

XT and RC(4) options

HS option

LP option, Commercial

LP option, Industrial

IDD —

—

1.8

2.4

4.5

2.4

8.0

µA

FOSC = 4.0 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

Power-down Current(5)

Commercial

Industrial

IPD —

—

4.0

0.25

5.0

0.3

4.0

5.0

µA

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 95

PIC16C54A PIC16C5X

13.2 DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended)

DC Character ist ics

Power Supply Pins Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (extended)

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage

XT and RC options

HS option

VDD 3.5

4.5 —

—5.5

5.5 V

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD start voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Rese t

VDD rise rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for details on

Power-on Rese t

Supply Current(3)

XT and RC(4) options

HS option

IDD —

—

1.8

4.8

9.0

3.3

FOSC = 4.0 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

Power-down Current(5)

XT and RC options

HS option

IPD —

—

5.0

0.8

4.0

0.25

µA

VDD = 3.5V, WDT enabled

VDD = 3.5V, WDT disabled

VDD = 3.5V, WDT enabled

VDD = 3.5V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) column is based on characterization results at 25 °C. This data is for design guidanc e

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

PIC16C5X PIC16C54A

DS30453C-page 96 Preliminary  2000 Microchip Technology Inc.

13.3 DC Characteristics: PIC16L C5 4A-04 (Comme rci al)

PIC16LC54A-04I (Industrial))

DC Character ist ics

Power Supply Pins

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage

XT and RC options

LP options

VDD 3.0

2.5 —

—6.25

6.25 V

RAM Data Retention Voltage(2) VDR —1.5* —V Device in SLEEP mode

VDD start voltage to ensure

Power-on Reset VPOR —VSS —V See Section 7.4 for details on

Power-on Rese t

VDD rise rate to ensure

Power-on Reset SVDD 0.05* ——V/ms See Section 7.4 for details on

Power-on Rese t

Supply Current(3)

XT and RC(4) options

LP option, Commercial

LP option, Industrial

LP option, Extended

IDD —

—

0.5

2.5

µA

FOSC = 4.0 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 2.5V WDT disabled

Power-down Current(5)

Commercial

Industrial

Extended

IPD —

—

2.5

0.25

2.5

0.25

2.5

0.25

4.0

5.0

7.0

µA

VDD = 2.5V, WDT enabled

VDD = 2.5V, WDT disabled

VDD = 2.5V, WDT enabled

VDD = 2.5V, WDT disabled

VDD = 2.5V, WDT enabled

VDD = 2.5V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) column is based on characterization results at 25 °C. This data is for design guidanc e

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in kΩ.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 97

PIC16C54A PIC16C5X

13.4 DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial)

PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial)

PIC16C54A-04E, 10E, 20E (Extended)

DC Character ist ics

All Pins Except

Power Supply Pins

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and

Section 13.3.

Characteristic Sym Min Typ(1) Max Units Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt T r igge r)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIL VSS

VSS

—

0.2 VDD

0.15 VDD

0.3 VDD

Pin at hi-impedance

RC option only(4)

XT, HS and LP options

Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIH 0.2 VDD+1V

2.0

0.85 VDD

0.7 VDD

—

VDD

For all VDD(5)

4.0V < VDD ≤ 5.5V(5)

RC option only(4)

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs VHYS 0.15VDD*——V

Input Leakage Current(3)

I/O ports

MCLR

T0CKI

OSC1

IIL -1.0

—

-5.0

-3.0

0.5

—

0.5

+1.0

—

+5.0

+3.0

—

µA

—

µA

For VDD ≤ 5.5V

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS +0.25V(2)

VPIN = VDD(2)

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC option only

Output High Voltage

I/O ports(3)

OSC2/CLKOUT

VOH VDD-0.7

VDD-0.7 —

——

—V

VIOH = -5.4 mA, VDD = 4.5V

IOH = -1.0 mA, VDD = 4.5V,

RC option only

* These parameters are characterized but not tested.

Note 1: Data in the T ypical (“Typ”) column is based on cha racterization results at 25°C. This d ata is for desi gn guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified

levels re present norm al operati ng condi tions. High er leakage current ma y be meas ured at dif feren t input vo lt-

age.

3: Negative current is defined as coming out of the pin.

4: For the RC opti on, the OSC 1/CLKIN pin is a Schmit t T rigger input . It is not reco mmended that the PIC1 6C5X

be driven with external clock in RC mode.

5: The user may use the better of the two specifications.

PIC16C5X PIC16C54A

DS30453C-page 98 Preliminary  2000 Microchip Technology Inc.

13.5 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the foll owing formats:

FIGURE 13-1: LOAD CONDITIONS - PIC16C54A

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase subscripts (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O po rt wdt watchdog timer

Uppe rcase letters and their meanings :

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

VSS

Pin CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

options w hen extern al clo ck

is used to drive OSC1

 2000 Microchip Technology Inc. Preliminary DS30453C-page 99

PIC16C54A PIC16C5X

13.6 Timing Diagrams and Specifications

FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC16C54A

TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A

AC Characte ristic s Standard Operating Conditions (unle ss other wis e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

FOSC External CLKIN Frequency(2) DC —4.0 MHz XT osc mode

DC —2.0 MHz XT osc mode (PIC16LV54A)

DC —4.0 MHz HS osc mode (04)

DC —10 MHz HS osc mode (10)

DC —20 MHz HS osc mode (20)

DC —200 kHz LP osc mode

Oscill ator Frequency(2) DC —4.0 MHz RC osc mode

DC —2.0 MHz RC osc mode (PIC16LV54A)

0.1 —4.0 MHz XT osc mode

0.1 —2.0 MHz XT osc mode (PIC16LV54A)

4—4.0 MHz HS osc mode (04)

4—10 MHz HS osc mode (10)

4—20 MHz HS osc mode (20)

5—200 kHz LP osc mode

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unles s otherwise stated. The se paramete rs are for design

guidance only and are not test ed.

2: All specifi ed valu es are bas ed on ch aracteriz ation da ta for that par ticula r oscil lator typ e under st andard o per-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruct ion cycle period (TCY) equals four times the input oscillator time base period.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

PIC16C5X PIC16C54A

DS30453C-page 100 Preliminary  2000 Microchip Technology Inc.

1TOSC External CLKIN Period(2) 250 ——ns XT osc mode

500 ——ns XT osc mode (PIC16LV54A)

250 ——ns HS osc mode (04)

100 ——ns HS osc mode (10)

50 ——ns HS osc mode (20)

5.0 ——µs LP osc mode

Oscill ator Perio d(2) 250 ——ns RC osc mode

500 ——ns RC osc mode (PIC16LV54A)

250 —10,00

0ns XT osc mode

500 ——ns XT osc mode (PIC16LV54A)

250 —250 ns HS osc mode (04)

100 —250 ns HS osc mode (10)

50 —250 ns HS osc mode (20)

5.0 —200 µs LP osc mode

CY Instructi on Cycle Time(3) —4/FOS

C——

3 TosL, TosH Clock in (OSC1 ) Low or High

Time 85* ——ns XT oscillator

20* ——ns HS oscillator

2.0* ——µs LP oscillat or

4 TosR, TosF Clock in (OSC1) Rise or Fall

Time ——25* ns XT oscillator

——25* ns HS oscillator

——50* ns LP oscillat or

TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A (CON’T)

AC Characteristics Standard Operating Conditions (unless otherwis e speci fied)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unles s otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specifi ed valu es are bas ed on ch aracteriz ation da ta for that par ticula r oscil lator typ e under st andard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruct ion cycle period (TCY) equals four times the input oscillator time base period.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 101

PIC16C54A PIC16C5X

FIGURE 13-3: CLKOUT AND I/O TIMING - PIC16C54A

TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and

Section 13.3.

Parameter

No. Sym Characteristic Min Typ(1) Max Units

10 TosH2ckL OSC1↑ to CLKOUT↓(2) —15 30** ns

11 TosH2ckH OSC1↑ to CLKOUT↑(2) —15 30** ns

12 TckR CLKOUT rise time(2) —5.0 15** ns

13 TckF CLKOUT fall time(2) —5.0 15** ns

14 TckL2ioV CLKOUT↓ to Port out valid(2) ——40** ns

15 TioV2ckH Port in valid before CLKOUT↑(2) 0.25 TCY+30* ——ns

16 TckH2ioI Port in hold after CLKOUT↑(2) 0* ——ns

17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(3) ——100* ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time) TBD ——ns

19 TioV2osH Port input valid to OSC1↑

(I/O in setup time) TBD ——ns

20 TioR Port output rise time(3) —10 25** ns

21 TioF Port output fall time(3) —10 25** ns

* These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unles s otherwise stated. The se paramete rs are for design

guidance only and are not test ed.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 14-1 for loading conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

12 16

Old Value New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

PIC16C5X PIC16C54A

DS30453C-page 102 Preliminary  2000 Microchip Technology Inc.

FIGURE 13-4: RESET, WATC HDOG TIMER, AND

DEVICE RESET TIMER TIMING - PIC16C54A

TABLE 13-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

30 TmcL MCLR Pulse Width (low) 100*

1µs —

——

—ns

—VDD = 5.0V

VDD = 5.0V (PIC16LV54A only)

31 Twdt Watc hd og Timer T ime-out

Period (No Prescaler) 9.0* 18* 30* ms VDD = 5.0V (Commercial)

32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Commercial)

34 TioZ I/O Hi-impedance from MCLR

Low —

——

—100*

1µs ns

—(PIC16LV54A only)

* These parameters are char acterized but n ot te sted.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated . These paramete rs are fo r design

guidance only and are not tested.

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O pin

32 32

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 103

PIC16C54A PIC16C5X

FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC16C54A

TABLE 13-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54A

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial )

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (exten ded )

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and

Section 13.3.

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* ——ns

- With Prescaler 10* ——ns

41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* ——ns

- With Prescaler 10* ——ns

42 Tt0P T0CKI Peri od 20 or TCY + 40 *

N ——ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

* These parameters are char acterized but n ot te sted.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unles s otherwise stated. The se paramete rs are for design guid-

ance only and are not tested.

T0CKI

40 41

PIC16C5X PIC16C54A

DS30453C-page 104 Preliminary  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Preliminary DS30453C-page 105

PIC16C54A PIC16C5X

14.0 DC AND AC CHARACTERISTICS - PIC16C54A

The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables,

the data pr ese nte d is ou tsi de sp ec ifi ed ope rati ng ran ge (e.g., outsid e specif ied VDD range). This is for information only

and devices will operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” represents the mean of the distribution, while “max” or “min” represents (mean + 3σ) and (mean – 3σ)

respectively, where σ is standard deviation.

FIGURE 14-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

TABLE 14-1: RC OSCILLATOR FREQUENCIES

CEXT REXT Average

Fosc @ 5 V, 25°C

20 pF 3.3 k 4.973 MHz ± 27%

5 k 3.82 MHz ± 21%

10 k 2.22 MHz ± 21%

100 k 262.15 kHz ± 31%

100 pF 3.3 k 1 .63 MHz ± 13%

5 k 1.19 MHz ± 13%

10 k 684.64 kHz ± 18%

100 k 71.56 kHz ± 25%

300 pF 3.3 k 660 kHz ± 10%

5.0 k 484.1 kHz ± 14%

10 k 267.63 kHz ± 15%

160 k 29.44 kHz ± 19%

The frequencies are measured on DIP packages.

The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is ±3 standard deviation from average value for VDD = 5 V.

FOSC

FOSC (25°C)

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

01020253040506070

T(°C)

Frequency normalized to +25°C

VDD = 5.5 V

VDD = 3.5 V

REXT ≥ 10 kΩ

CEXT = 100 pF

0.88

PIC16C5X PIC16C54A

DS30453C-page 106 Preliminary  2000 Microchip Technology Inc.

FIGURE 14-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF

FIGURE 14-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF

6.00

5.00

4.00

3.00

1.00

0.00 33.54 4.5 5 5.5 6

2.5 VDD (Volts)

2.00

OSC

(MHz)

2.00

CEXT=20pF, T=25°C

R=3.3K

R=5.0K

R=10K

R=100K

6.00

5.00

4.00

3.00

1.00

0.00 33.54 4.5 5 5.5 6

2.5 VDD (Volts)

2.00

6.00

5.00

4.00

3.00

1.00

0.00 33.54 4.5 5 5.5 6

2.5 VDD (Volts)

2.00

OSC

(MHz)

CEXT=100pF, T=25°C

R=3.3K

R=5.0K

R=10K

R=100K

1.80

1.60

1.00

0.40

0.00 33.5

4 4.5 5 5.5 6

2.5 VDD (Volts)

0.60

1.20

0.80

0.20

1.40

 2000 Microchip Technology Inc. Preliminary DS30453C-page 107

PIC16C54A PIC16C5X

FIGURE 14-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF

FIGURE 14-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)

OSC

(kHz)

700.00

600.00

500.00

400.00

300.00

200.00

100.00

0.002.5 3 3.5 4 4.5 55.5 6

CEXT=300pF, T=25°C

R=3.3K

R=5.0K

R=10K

R=100K

VDD (Volts)

2.50

2.00

1.50

1.00

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.50

05.5 6.0

(

PIC16C5X PIC16C54A

DS30453C-page 108 Preliminary  2000 Microchip Technology Inc.

FIGURE 14-6: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD

FIGURE 14-7: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD

FIGURE 14-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT

(IN XT, HS, AND LP MODES) vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

Min (–40°C to +85°C)

0.80

0.60 5.5 6.0

Max (–40°C to +85°C)

Typ (+25°C)

(Volts)

3.5

3.0

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.5

0.0 5.5 6.0

, V

(Volts)

4.0

4.5

min (–40°C to +85°C)

max (–40°C to +85°C)

typ +25°C

min (–40°C to +85°C)

max (–40°C to +85°C)

typ +25°C

Note: These input pins have Schmitt Trigger input buffers.

2.4

2.2

2.0

1.8

1.6

1.4

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

1.2

1.0 5.5 6.0

Typ (+25°C)

(Volts)

2.6

2.8

3.0

3.2

3.4

Max (–40°C to +85°C)

Min (–40°C to +85°C)

 2000 Microchip Technology Inc. Preliminary DS30453C-page 109

PIC16C54A PIC16C5X

FIGURE 14-9: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, 25°C)

FIGURE 14-10 : MAXIMU M IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, –40°C TO +85°C)

10000

1000

100

100.1 110

(

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Freq (MHz)

10000

1000

100

10 110

(

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

0.1 Freq (MHz)

PIC16C5X PIC16C54A

DS30453C-page 110 Preliminary  2000 Microchip Technology Inc.

FIGURE 14-11: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, 25°C)

FIGURE 14-12 : MAXIMU M IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, –40°C TO +85°C)

10000

1000

100

0.01 110

(

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Freq (MHz)

0.1

10000

1000

100

0.01 110

(

Freq (MHz)

0.1

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

 2000 Microchip Technology Inc. Preliminary DS30453C-page 111

PIC16C54A PIC16C5X

FIGURE 14-13: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, 25°C)

FIGURE 14-14 : MAXIMU M IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, –40°C TO +85°C)

10000

1000

100

0.01 0.1 1

(

Freq (MHz)

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

10000

1000

100

0.01 0.1

(

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Freq (MHz)

PIC16C5X PIC16C54A

DS30453C-page 112 Preliminary  2000 Microchip Technology Inc.

FIGURE 14-15 : WDT TIMER TIME-OUT

PERIOD vs. VDD TABLE 14-2: INPUT CAPACITANCE FOR

PIC16C54A/C58A

5234567

VDD (Volts)

WDT peri od (ms)

Max +85°C

Max +70°C

Typ +25°C

MIn 0°C

MIn –40°C

Pin Typical Capacitance (pF)

18L PDIP 18L SOIC

RA port 5.0 4.3

RB port 5.0 4.3

MCLR 17.0 17.0

OSC1 4.0 3.5

OSC2/CLKOUT 4.3 3.5

T0CKI 3.2 2.8

All capacitance values are typical at 25°C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

 2000 Microchip Technology Inc. Preliminary DS30453C-page 113

PIC16C54A PIC16C5X

FIGURE 14-16: TRAN SCONDUC TANCE (gm)

OF HS OSCILLATOR vs. VDD

FIGURE 14-17: TRAN SCONDUC TANCE (gm)

OF LP OSCILLATOR vs. VDD

9000

8000

7000

6000

5000

4000

3000

2000

100

0234567

VDD (Volts)

gm (

A/V)

Min +85°C

Max –40°C

Typ +25°C

0234567

VDD (Volts)

gm (

A/V)

Min +85°C

Max –40°C

Typ +25°C

FIGURE 14-18: TRANSCONDUCTANCE (gm)

OF XT OSCILLATOR vs. VDD

2500

2000

1500

1000

500

0234567

VDD (Volts)

gm (

A/V)

Min +85°C

Max –40°C

Typ +25°C

PIC16C5X PIC16C54A

DS30453C-page 114 Preliminary  2000 Microchip Technology Inc.

FIGURE 14-19 : IOH vs. VOH, VDD = 3 V

FIGURE 14-20 : IOH vs. VOH, VDD = 5 V

–5

–10

–15

–20

–250 0.5 1.0 1.5 2.0 2.5

VOH (Volts)

(mA)

Min +85°C

3.0

Typ +25°C

Max –40°C

–10

–20

–30

–401.5 2.0 2.5 3.0 3.5 4.0

VOH (Volts)

(mA)

Min +85°C

Max –40°C

4.5 5.0

Ty p +25 °C

FIGURE 14-21: IOL vs. VOL, VDD = 3 V

FIGURE 14-22: IOL vs. VOL, VDD = 5 V

0.0 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

(mA)

Min +85°C

Max –40°C

Typ +25°C

3.0

00.00.51.01.52.02.5

VOL (Volts)

(mA)

Min +85°C

Max –40°C

Typ +25°C

3.0

 2000 Microchip Technology Inc. Preliminary DS30453C-page 115

PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B

15.0 ELECTRICAL CHARACTERISTICS -