Do] c) ILC DATA DEVICE CORPORATIONS BU-65170/61580 and BU-61585 DESCRIPTION DDC's BU-65170, BU-61580 and BU-61585 BC/RT/MT Advanced Com- munication Engine (ACE) terminal comprises a complete integrated interface between a host processor and a MIL-STD- 1553 A and B or STANAG 3838 bus. The ACE series is packaged in a 1.9 square inch 70-pin, low-profile, cofired MCM ceramic package that is well suited for applications with stringent height requirements. The BU-61585 ACE integrates dual transceiver, protocol, memory man- agement, processor interface logic, and a total of 12K words of RAM ina choice of DIP or flat pack packages. The BU-61585 requires +5 V power and either -15 V or -12 V power. The BU-61585 internal RAM can be configured as 12K x 16 or 8K x 17. The 8K x17 RAM feature provides capability for memory integrity checking by implementing RAM parity genera- tion and verification on all accesses. To minimize board space and glue logic, the ACE provides ultimate flexibility in interfacing to a host processor and internal/external RAM. The advanced functional architecture of the ACE terminals provides soft- ware compatibility to DDCs AIM series hybrids, while incorporating a multiplicity of architectural enhance- ments. It allows flexible operation while off-loading the host processor, ensuring data sample consistency, and supporting bulk data transfers. The ACE hybrids may be operated at either 12 or 16 MHz. Wire bond op- tions allow for programmable RT address (hardwired is standard) and external transmitter inhibit inputs. MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT, ADVANCED COMMUNICATION ENGINE (ACE) ACE Users Guide Also Available FEATURES Fully integrated Bus Interface Terminal Flexible Processor/Memory Interface @ Standard 4K x 16 RAM and Optional 12K x 16 or 8K x 17 RAM Available Optional RAM Parity Generation/Checking Automatic BC Retries Programmable BC Gap Times @ BC Frame Auto-Repeat Flexible RT Data Buffering @ Programmable Iilegalization Selective Message Monitor Simultaneous RT/Monitor Mode TRANSCEIVER K THA A T RAK PRANSCEIVER. a SHAREO * : RAM ' , 1 ' = t 1 ATA PROCESSOR CATA BUS acrrens DATA BUS DUAL ENCODE A-DECODER : MUL TIPROTOCOL | BC.AT-MONITOR ' PROTOCOL t MEMORY : MANAGEMENT A a PROCESSOR < AODRESS BUS * eorrene ADDRESS BLS, 1 RT ACUREDSS J-18 ATADS ATADO ATADP PAOGESSOA aN AY INTERFACE LOGIC + HiGER MEMENA OUT, READY: int 1 > ee | TRANSPARENT GUFFERED, STRBD SELECT 'ROWA, MEWAEG TRIGGER SEL-MEMENA IN 'MSBAS-OTGRT PROCESSOR MEMORY CONTROL | ADOA, LAT: MEMOE, ZERO_WAITMEMWR 116 BITDTREQ POLARITY SELOTACK NTEARUPT REQUEST ie SEE ORDERING INFORMATION FOR AVAILABLE MEMORY FIGURE 1. ACE BLOCK DIAGRAMBOG ILC DATA DEVICE CORPORATION? BU-65170/61580 and BU-61585 TABLE 9. (continued) MISCELLANEOUS (7) DESCRIPTION SIGNAL NAME | PIN CLOCK IN (i) 19 | 16MHz (or 12MHZz) clock input. MSTCLR (I) 7 {Master Clear. Negative true Reset input, normally asserted low following power turn-on. Requires a minimum 100ns negative pulse to reset all internal logic to its power turn-on state. INCMD (0) 45 |In Command. In BC mode, asserted low throughout processing cycle for each message. In RT mode or Message Monitor mode, asserted low following receipt of Command Word and kept low until completion of current message sequence. In Word Monitor mode, goes low following MONITOR START command, kept low while monitor is on-line, goes high following RESET command. SSFLAG (i) 27 |Subsystem Flag or External Trigger input. in the Remote Terminal mode, asserting this input , will set the Subsystem EXT TRIG (I) Flag bit in the BU-65170/61580's RT Status Word. A low on the SSFLAG input overrides a togic 1" of the respective bit (bit 8) of Configuration Register #1. In the Bus Controller mode, an enabled external BC Start option (bit 7 of Configuration Register #1) and a low-to-high transition on this input will issue a BC Start command, starting execution of the current BC frame. In the Word Monitor mode, an enabled external trigger (bit 7 of Configuration Register #1) anda low-to-high transition on this input will issue a monitor trigger. TAG_CLK (1) 63 | External Time Tag Clock input. Use may be designated by bits 7, 8, and 9 of Configuration Register #2. When used it increments the internal Time Tag Register/Counter. If not used, should be connected to +5V or ground. TX_INH_A (ft) 70_|Option for BU-65170/61580X6 and the BU-61585X6. Inhibits (disables) the respective (A/B) MIL-STD-1553 transmitter TX_INH_B (I) 36 |/when asserted to logic 1. TABLE 10. BU-65170/65171, TABLE 10. BU-65170/65171, TABLE 10. BU-65170/65171, BU-61580/61581/61585/61586 BU-61580/61581/61585/61586 BU-61580/61581/61585/61586 PIN LISTINGS PIN LISTINGS PIN LISTINGS (S or V package) ( or V package) (S or V package) PIN NAME PIN NAME PIN NAME 1 TX/RX-A 28 _|MEMENA_OUT 55 [008 2 | TX/RXA 29 _|MEMOE/ADOR_LAT 56 _|Do9 3 SELECT 30 _|MEMWRA/ZERO_WAIT 57 |D10 4 _|STRED 31 |[OTREQ/16/8 58 |p11 5 _|MEM/REG 32__ |DTACK/POLARITY_SEL 59 |D12 6 _|RDWR 33. |MEMENA_IN/TRIGGER_SEL 60 |D13 7___|MSTCLR 34 | TX/RX-B 61 |D14 8 |A15 35 | TX/RX-B 62 _|D15 9 Al4 36 -VB (see note) 63 TAG_CLK 10 [A193 37__|GNDB 64 _|TRANSPARENT/BUFFERED 11 lai2 38 [+5VB 65__ [iNT i2 [Att 39 _|RTADO 66 _|READYD 13 [A10 40 _|ATAD1 67__|IOEN 14 AQQ 41 RTAD2 68 +5VA 15 |A08 42 _|RTADS 69 _|GNDA 16 | A07 43 |RTAD4 70 __|-VA (see note) 17__|A06 44 |RTADP Notes: 18 |GND 45 |INGMD -15V for BU-65170/61580X1. -12V for BU-65170/61580X2. 19 J CLK 46__|D00 N/C for BU-65170/61580X3. 20 | A05 47___|Do1 | 21 [aoa 48 |D02 For BU-65170/61580X6: in 36 is TX_INH_B - aoe - ns nin 70 is TX_INH_A 24 |A01 51 |D05 25 |A00 52 _|D06 26 _|DTGRT/MSB/LSB 53 _|b07 27__ | SSFLAG/EXT_TRIG 54 _|+5VLOGIC J-19O0G BU-65170/61580 and BU-61585 CORPORATION? ORDERING INFORMATION BU-61580 $ 3-110 - -- Test Criteria: | Ji i. 0 = None | | | | |. Sereening: | 0 = Commercial Screening 1 u Fully compliant to MIL-STD-883 and DESC [i I 2 = Screened to MIL-STD-883 but without | | QC testing 3 = 883B and DESC and PIND testing i 4 = 883B and DESC and Solder Dip 5 = 883B and DESC and PIND and Solder Dip ---- Temperature Range: 1 = -55 to +125C it 3 = Oto +70C | te Voltage/Transceiver Option: QO = Transceiverless 1 = +5/-15 V (1760 compliant) 1 2 = +5/-12V 3 = +5 V only 6 = +5 V only with Tx Inhibits brought out on negative supply pins ~-oome~- Package: S= Dip ! V = Flat Pack -~----- Product Type: 65170 = 70-pin RT 65171 = 70-pin RT with latched RT address option 61580 = 70-pin BC/RT/MT 61581 = 70-pin BC/RT/MT with latchable RT address option 61585 = 70-pin BC/RT/MT with BK x 17 RAM 61586 = 70-pin BC/RT/MT with 8K x 17 RAM and RT address option * Contact factory about 1760 compliance. Note: The "ACE" series is also available to DESC drawing number 5962-93065. D-ABR J-20