CYD04S18V-167BBC - Cypress Semiconductor Corp

FLEx18™ 3.3V 64K/128K/256K/512K x 18

Synchronous Dual-Port RAM

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-06077 Rev. *C Revised May 5, 2005

Features

• True dual-ported memory cells that allow simultaneous

access of the same memory location

• Synchronous pipelined operation

• Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits

devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

• 3.3V low power

— Active as low as 225 mA (typ)

— Standby as low as 55 mA (typ)

• Mailbox function for message passing

• Global mas t er reset

• Separate byte enables on both port s

• Commerc ia l a nd industrial tem pe r ature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 256-ball FBGA (1 mm pitch)

• Counter wrap -around control

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block re transmit operation

• Counter readback on ad dress lines

• Mask register readback on address lines

• Dual Chip Enables on both ports for easy depth

expansion

• Seamless migration to next-generation dual-port family

Functional Description

The FLEx18™ family includes 1-Mbit, 2-Mbit, 4-Mbit and

9-Mbit pipelined, synchronous, true dual-port static RAMs that

are high-speed, low-power 3.3V CMOS. Two ports are

provided, permitting independent, simultaneous access to any

location in memory. The result of writing to the same location

by more than one port at the same time is undefined. Registers

on control, address, and data lines allow for minimal set-up

and hold time.

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal Write pulse width is

independent of the duration of the R/W input signal. The

internal Write pulse is self-timed to allow the shortest possible

cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

The CYD09S18V device in this family has limited features.

Please see Address Counter and Mask Register Operations

on page 5 for details.

Seamless Migration to Next Generation Dual Port Family

Cypress offers a migration path for all devices in this family to

the next-generation devices in the Dual-Port family with a

compatible footprint. Please contact Cypress Sales for more

details.

Table 1. Product Selection Guide

Density 1 Mbit

(64K x 18) 2 Mbit

(128K x 18) 4 Mbit

(256K x 18) 9 Mbit

(512K x 18)

Part Number CYD01S18V CYD02S18V CYD04S18V CYD09S18V

Max. Speed (MHz) 167 167 167 133

Max. Access Time – Clock to Data (ns) 4.0 4.0 4.0 4.7

Typical operating current (mA) 225 225 225 270

Package 256FBGA

(17 mm x 17 mm) 256FBGA

(17 mm x 17 mm)

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 2 of 26

Note:

1. CYD01S18V has 16 address bits, CYD02S18V has 17 address bits, CY04 S18V has 18 address bits and CYD09S18V has 19 address bits.

Logic Block Diagram[1]

A (18:0)L

CNT/MSK

ADSL

CNTENL

CNTRSTL

RETL

CNTINT

WRPL

A (18:0)R

CNT/MSK

ADSR

CNTENR

CNTRSTR

RETR

CNTINT

WRPR

Address &

Counter Logic Address &

Counter Logic

INTL

TRST

TMS

TDI

TDO

TCK

JTAG

MRST

READY

LowSPDR

READYL

LowSPDL

RESET

LOGIC

INTR

BUSYLBUSYR

Mailboxes

Arbitration Logic

FTSELL

PORTSTD(1:0)L

DQ (17:0)L

BE (1:0)

CE0L

CE1L

OEL

R/W

FTSELR

PORTSTD(1:0)R

DQ (17:0)R

BE (1:0)

CE0R

CE1R

OER

R/W

CONFIG Block CONFIG Block

Control IO

Control

Dual Ported Array

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 3 of 26

Pin Configurations

256-ball BGA Top View

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

12 3 4 56 7 8910111213141516

ANC NC NC DQ17LDQ16LDQ13LDQ12LDQ9LDQ9RDQ12RDQ13RDQ16RDQ17RNC NC NC

BNC NC NC NC DQ15LDQ14LDQ11LDQ10LDQ10RDQ11RDQ14RDQ15RNC NC NC NC

CNC NC RETL

[2,3] INTLNC

[2,5] NC

[2,5] REVL

[2,4] TRST

[2,5] MRST NC

[2,5] NC

[2,5] INTRRETR

[2,3] NC NC

DA0LA1LWRPL

[2,3] VREFL

[2,4] FTSELL

[2,3] LowSPDL

[2,4] VSS VTTL VTTL VSS LowSPDR

[2,4] FTSELR

[2,3] VREFR

[2,4] WRPR

[2,3] A1RA0R

EA2LA3LCE0L

[10] CE1L

[9] VDDIOLVDDIOLVDDIOLVCORE VCORE VDDIORVDDIORVDDIORCE1R

[9] CE0R

[10] A3RA2R

FA4LA5LCNTINTL

[11] NC VDDIOLVSS VSS VSS VSS VSS VSS VDDIORNC CNTINTR

[11] A5RA4R

GA6LA7LBUSYL

[2,5] NC REVL

[2,3] VSS VSS VSS VSS VSS VSS VDDIORNC BUSYR

[2,5] A7RA6R

HA8LA9LCLVTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CRA9RA8R

JA10LA11LVSS PortSTD1L

[2,4] VCORE VSS VSS VSS VSS VSS VSS VCORE PortSTD1R

[2,4] VSS A11RA10R

KA12LA13LOELBE1LVDDIOLVSS VSS VSS VSS VSS VSS VDDIORBE1ROERA13RA12R

LA14LA15LADSL

[10] BE0LVDDIOLVSS VSS VSS VSS VSS VSS VDDIORBE0RADSR

[10] A15RA14R

MA16L

[6] A17L

[7] RWLREVL

[2,4] VDDIOLVDDIOLVDDIOLVCORE VCORE VDDIORVDDIORVDDIORREVR

[2,4] RWRA17R

[7] A16R

[6]

NA18L

[8] NC CNT/

MSKL

[9] VREFL

[2,4] PortSTD0L

[2,4] READYL

[2,5] REVL

[2,3] VTTL VTTL REVR

[2,3] READYR

[2,5] PortSTD0R

[2,4] VREFR

[2,4] CNT/

MSKR

[9] NC A18R

[8]

PNC NC CNTENL

[10] CNTRSTL

[9] NC

[2,5] NC

[2,5] TCK TMS TDO TDI NC

[2,5] NC

[2,5] CNTRSTR

[9] CNTENR

[10] NC NC

RNC NC NC NC DQ6LDQ5LDQ2LDQ1LDQ1RDQ2RDQ5RDQ6RNC NC NC NC

TNC NC NC DQ8LDQ7LDQ4LDQ3LDQ0LDQ0RDQ3RDQ4RDQ7RDQ8RNC NC NC

Notes:

2. This ball will represent a next generation FLEx18-E Dual-Port feature. For more information about this feature, cont act Cypress Sales.

3. Connect this ball to VDDIO. For more information about this next generation FLEx18-E Dual-Port feature contact Cypress Sales.

4. Connect this ball to VSS. For more information about this nex t generation FLEx18-E Dual-Port feature, contact Cypress Sales.

5. Leave this ball unconnected. For more information about this feat ure, contact Cypress Sale s.

6. Leave this ball unconnected for a 64K x 18.

7. Leave this ball unconnected for a 128K x 18 and 64K x 18.

8. Leave this ball unconnected for a 256K x 18, 128K x 18 and 64K x 18.

9. These balls are not applicable for CYD09S18V device. They need to be tied to VDDIO.

10.These balls are not applicable for CYD09S18V device. They need to be tied to VSS.

11.These balls are not applicable for CYD09S18V device. They need to be no connected.

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 4 of 26

Pin Definitions

Lef t Port Right Port Description

A0L–A18L A0R–A18R Address Inputs.

BE0L–BE1L BE0R–BE1R Byte Enable Inputs. Asserting these signals enables Read and Write operations to

the corresponding bytes of the memory array.

BUSYL[2,5] BUSYR[2,5] Port Busy Output. When the collision is detected, a BUSY is asserted.

CLCRInput Clock Signal.

CE0L[10] CE0R[10] Active Low Chip Enab le Inpu t.

CE1L[9] CE1R[9] Act ive High Chip Enab le Input .

DQ0L–DQ17L DQ0R–DQ17R Data Bus Input/Output.

OELOEROutput Enable Input. This asynchronous signal must be asserted LOW to enable

the DQ data pins during Read operations.

INTLINTRMailbox Interrupt Flag Output. The mailbox permits communications between ports.

The upper two memory locations can be used for message passing. INTL is asserted

LOW when the right port writes to the mailbox location of the left port, and vice versa.

An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.

LowSPDL[2,4] LowSPDR[2,4] Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD

disables the port DLL.

PORTSTD[1:0]L[2,4] PORTSTD[1:0]R[2,4] Port Address/Control/Data I/O Standa rd Select Input.

R/WLR/WRRead/W rite Enable Input. Assert this pin LOW to write to, or HIGH to read from the

dual-port memory array.

READYL[2,5] READYR[2,5] Port Ready Output. This signal will be asserted wh en a port is ready for normal

operation.

CNT/MSKL[9] CNT/MSKR[9] Port Counter/Mask Select Input. Counter control input.

ADSL[10] ADSR[10] Port Counter Address Load Strobe Input. Counter control input.

CNTENL[10] CNTENR[10] Port Counter Enable Input. Counter control input.

CNTRSTL[9] CNTRSTR[9] Port Counter Reset Input. Counter control input.

CNTINTL[11] CNTINTR[11] Port Counter Interrupt Output. This pin is asserted LOW when the unmasked

portion of the counter is incremented to all “1s”.

WRPL[2,3] WRPR[2,3] Port Counter Wrap Input. After the burst counter reaches the maximum count, if

WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be

loaded with the value stored in the mirror register.

RETL[2,3] RETR[2,3] Port Counter Retransmit Input. Counter control input.

FTSELL[2,3] FTSELR[2,3] Flow-Through Mode Select Input.

VREFL[2,4] VREFR[2,4] Port External High-Speed IO Reference Input.

VDDIOLVDDIORPort IO Power Supply.

REVL[2,4] REVR[2,4] Reserved pins for future features.

MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports.

A master reset operation is required at power-up.

TRST[2,5] JTAG Reset In put.

TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine.

State machine transitions occur on the rising edge of TCK.

TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected

registers.

TCK JTAG Test Clock Input.

TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is

normally three-stated except when captured data is shifted out of the JTAG TAP.

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 5 of 26

Master Reset

The FLEx18 family devices undergo a complete reset by

taking its MRST input LOW. The MRST input can switch

asynchronously to the clocks. The MRST initializes the

internal burst counters to zero, and the counter mask registers

to all ones (completely unmasked). The MRST also forces the

Mailbox Interrupt (INT) flags and the Counter Interrupt

(CNTINT) flags HIGH. The MRST must be performed on the

FLEx18 family devices after power-up.

Mailbox Interrupts

The upper two memory locations may be used for message

passing and permit communications between ports. Table

shows the interrupt operation for both ports of CYD09S18V.

The highest memory location, 7FFFF is the mailbox for the

right port and 7FFFE is the mailbox for the left port. Table

shows that in order to set the INTR flag, a Write opera tion by

the left port to address 7FFFF will assert INTR LOW. At least

one byte has to be acti ve fo r a Write to generate an interrupt.

A valid Read of the 7FFFF locati on by th e right p ort will reset

INTR HIGH. At least one byte has to be active in order for a

Read to reset the interrupt. When one port Writes to the other

port’s mailbox, the INT of the port that the mailbox belongs to

is asserted LOW . The INT is reset when the owner (port) of the

mailbox Reads th e con tents of the mail box. T he inte rrupt flag

is set in a flow-thru mode (i.e., it follows the clock edge of the

writing port). Also, the flag is reset in a flow-thru mode (i.e., it

follows the clock edge of the reading port).

Each port can read the other po rt’s mailbox without resetting

the interrupt. And each port can write to its own mailbox

without setting the interrupt. If an application does not require

message passing, INT pins should be left open.

Address Counter and Mask Register

Operations

This section describes the features only apply to 1-Mbit,

2-Mbit, and 4-Mbit devices. It does not apply to a 9-Mbit

device. Each port of these devices has a programmable burst

address counter . The burst counter contains three registers: a

counter register, a mask register, and a mirror register.[17]

The counter register contains the address used to access the

RAM array . It is changed only by the Counter Load, Increment,

Counter Reset, and by master reset (MRST) operations.

The mask register value affects the Increment and Counter

Reset operations by preventing the corresponding bits of the

counter register from changing. It also affects the counter

interrupt output (CNTINT). The mask register is changed only

by the Mask Load and Mask Reset operations, and by the

MRST. The mask register defines the counting range of the

counter register. It divides the counter register into two

regions: zero or more “0s” in the most significant bits define

the masked region, one or more “1s” in the least significant bits

define the unmasked region. Bit 0 may also be “0,” masking

the least significant counter bit and causing the counter to

increment by two instead of one.

The mirror register is used to reload the counter register on

increment operations (see “retransmit,” below). It always

contains the value last loaded into the counter register , and is

changed only by the Counter Load, and Counter Reset opera-

tions, and by the MRST.

Table 3 summarizes the operation of these registers and the

required input control signals. The MRST control signal is

asynchronous. All the other control signals in Table 3

(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the

port’s CLK. All these counter and mask operations are

independent of the port’s chip enable inputs (CE0 and CE1).

VSS Ground In puts.

VCORE[12] Core Power Supply.

VTTL LVTTL Power Supply.

Pin Definitions (continued)

Lef t Port Right Port Description

Table 2. Interrupt Operatio n Example [1, 13, 14, 15, 16]

Function

Lef t Port Right Port

R/WLCELA0L–18LINTLR/WRCERA0R–18R INTR

Set Right INTR Flag L L 7FFFF X X X X L

Reset Right INTR Flag X X X X H L 7FFFF H

Set Left INTL Flag X X X L L L 7FFFE X

Reset Left INTL Flag H L 7FFFE H X X X X

Notes:

12.This family of Dual -Ports does not use V CORE, and th ese pi ns are intern ally NC. The next gener a tion Dua l-Por t fa mily, the FLEx18- E™, wil l use VCORE of 1.5V

or 1.8V. Please contact local Cypress FAE for more information.

13.CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operati on, CE only needs t o be asserted once at th e rising edge of the CLK

and can be deasserted after that. Data will be out after the f ollowing CLK edge and will be three-stated after the next CLK edge.

14.OE is “Don’t Care” for mailbox operation.

15.At least one of BE0, BE1 must be LOW.

16.A18x is a NC for CYD04S18V , therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CYD02S18V , therefore the Interrupt addresses

are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CYD01S18V, therefore the Interrupt Addresses are FFFF and FFFE.

17.This section describes the CYD04S18V, CYD02S18V, CYD01S18V 18, 17, and 16 address bits .

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 6 of 26

Counter enable (CNTEN) inputs are provided to stall the

operation of the address input and utilize the internal address

generated by the internal counter for fast, interleaved memory

applications. A port’s burst counter is loade d when the port’s

address strobe (ADS) and CNTEN signals are LOW . When the

port’s CNTEN is asserted and the ADS is deasserted, the

address counter will increment on each LOW to HIGH

transition of that port’s clock signal. This will Read/Write one

word from/into each successive address location until CNTEN

is deasserted. The counter can address the entire memory

array, and will loop back to the start. Counter reset (CNTRST)

is used to reset the unmasked portion of the burst counter to

0s. A counter-mask register is used to control the counter

wrap.

Counter Reset Operation

All unmasked bits of the counter and mirror registers are reset

to “0.” All masked bits remain unchanged. A Mask Reset

followed by a Counter Reset will reset the counter and mirro r

registers to 00000, as will master reset (MRST).

Counter Load Operation

The address counter and mirror registers are both loaded with

the address value presented at the address lines.

Counter Increment Operation

Once the address counter register is initially loaded with an

external address, the counter can internally increment the

address value, potentially addressing the entire memory array .

Only the unmasked bits of the counter register are incre-

mented. The corresponding bit in the mask register must be

a “1” for a counter bit to change. The counter register is incre-

mented by 1 if the least si gnificant bit is unmasked, and by 2

if it is masked. If all unmasked bits are “1,” the next increment

will wrap the counter back to the initially loaded value. If an

Increment results in all the unmasked bits of the counter being

“1s,” a counter interrupt flag (CNTINT) is asserted.

The next Increment will retu rn the counter register to its initial

value, which was stored in the mirror register. The counter

address can instead be forced to loop to 00000 b y externally

connecting CNTINT to CNTRST.[20] An increment that results

in one or more of the unmasked bits of the counter being “0”

will deassert the counter interrupt flag. The example in

Figure 2 shows the counter mask register loaded with a mask

value of 0003Fh unmasking th e first 6 bits with bit “0” as the

LSB and bit “16” as the MSB. The maximum va lue the mask

memory space. The address counter is then loaded with an

initial value of 8h. The base address bits (in this case, the 6th

address through the 16th address) are loaded with an address

value but do not incre ment once the counter is configu red for

increment operation. The counter address will start at address

8h. The counter will increment its internal add ress value till it

reaches the mask register value of 3Fh. The counter wraps

around the memory block to location 8h at the next count.

CNTINT is issued when the counter reaches its maximum

value.

Counter Hold Operation

The value of all th ree registers can be constantly maintained

unchanged for an unlimited number of clock cycles. Such

operation is useful in applications where wait states are

needed, or when address is available a few cycles ahead of

data in a shared bus interface.

Notes:

18.“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.

19.Counter operation and mask register operation is independent of chip enables.

20.CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.

Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [18, 19]

CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description

X L X X X X Master Reset Reset address counter to all 0s and mask

H H L X X Counter Reset Reset counter unmasked portion to all 0s.

H H H L L Counter Load Load counter with external address value

presented on address lines.

H H H L H Counter Readback Read out counter internal value on address

lines.

H H H H L Counter Increment Internally incre m ent address counter value.

H H H H H Counter Hold Constantly hold the address val ue for

multiple clock cycles.

H L L X X Mask Reset Reset mask register to all 1s.

H L H L L Mask Load Load mask register with value presented on

the address lines.

H L H L H Mask Readback Read out mask register value on address lines.

H L H H X Reserved Operation undefined

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 7 of 26

Counter Interrupt

The counter interrupt (CNTINT) is asserted LOW when an

increment operation results in the unmasked portion of the

counter register being all “1s.” It is deasserted HIGH when an

Increment operation results in any other value. It is also

deasserted by Counter Reset, Counter Load, Mask Reset and

Mask Load operations, and by MRST.

Counter Readback Operation

The internal value of the counter register can be read out on

the address lines. Readback is pi pelined; the address will be

valid tCA2 after the next rising edge of the port’s clock. If

address readback occurs while the port is enabled (CE0 LOW

and CE1 HIGH), the data lines (DQs) will be three-stated.

Figure 1 shows a block diagram of the operation.

Retransmit

Retransmit is a feature that allows the Read of a block of

memory more than once without the need to reload the initial

address. This eliminates the need for external logic to store

and route data. It also reduces the complexity of the system

design and saves board space. An internal “mirror register” is

used to store the initially loaded address counter value. When

the counter unmasked portion reaches its maximum value set

by the mask register , it wraps back to the initial value stored in

this “mirror register.” If the counter is conti nuously configured

in increment mode, it incre ments again to its maximum value

and wraps back to the value initially stored into the “mirror

allowed without the need for any external logic.

Mask Reset Operation

The mask register is reset to all “1s,” which unmasks every bit

of the counter. Master reset (MRST) also resets the mask

Mask Load Operation

The mask register is loaded with the address value presented

at the address lines. Not all values permit correct increment

operations. Permitted values are of the form 2n – 1 or 2n – 2.

From the most significant bit to the least significant bit,

permitted values have zero or more “0s,” one or more “1s,” or

one “0.” Thus 3FFFF, 003FE, and 00001 are permitted values,

but 3F0FF, 003FC, and 0000 0 are not.

Mask Readback Operation

The internal value of the mask register can be read out on the

address lines. Readback is pipelined; the address will be valid

tCM2 after the next rising edge of the port’s clock. If mask

readback occurs while the port is enabled (CE0 LOW and CE1

HIGH), the data lines (DQs) will be three-stated. Figure 1

shows a block diagram of the operation.

Counting by Two

When the least significant bit of the mask register is “0,” the

counter increments by two. This may be used to connect the

x18 devices as a 36-bit single port SRAM in which the counter

of one port counts even addresses and the counter of the other

port counts odd addresses. This even-odd address scheme

stores one half of the 36-bit data in even memory locations,

and the other half in odd memory locations.

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 8 of 26

From

Mask

Mirror Counter

Address

Decode RAM

Array

Wrap

Increment

Logic

Wrap

Detect

From

Mask

From

Counter

Bit 0

Wrap

Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]

17 17

Load/Increment

CNT/MSK

CNTEN

ADS

CNTRST

CLK

Decode

Logic

Bidirectional

Address

Lines Mask

Counter/

Address

From

Address

Lines To Readback

and Address

Decode

MRST

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 9 of 26

IEEE 1149.1 Serial Boundary Scan (JTAG)[22]

The FLEx18 family devices in corporate an IEEE 1149.1 serial

boundary scan test access port (TAP). The TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1-compliant TAPs. The TAP

operates using JEDEC-standard 3.3V I/O logic levels. It is

composed of three input connections and one output

connection required by the test logic defined by the standard.

Performing a TAP Reset

A reset is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This reset does not affect the operation of the

devices, and may be performed while the device is operating.

An MRST must be performed on the devices after power-up.

Performing a Pause/Restart

When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the

scan chain will output the next bit in the chain twice. For

example, if the value expected from the chain is 1010101, the

device will outp ut a 11010101. This extra bi t will cause some

testers to report an erroneous failure for the devices in a scan

test. Therefore the te ster should be con figured to never ente r

the PAUSE-DR state.

Boundary Scan Hierarchy fo r 9-Mbit Device

Internally, the CYD09S18V have two DIEs. Each DIE contains

all the circuitry required to support boundary scan testing. The

circuitry includes th e TAP, TAP controller, instruction register,

and data registers. The circuity and operation of the DIE

boundary scan are described in detail below. The scan chain

of each DIEs are connected serially to form the scan chain of

the CYD09S18V as shown in Figure 3. TMS and TCK are

connected in parallel to each DIE to drive all TAP controllers

in unison. In ma ny cases, each DIE will be sup plied with the

same instruction. In o ther cases, it might be useful to supply

different instructions to each DIE. One example would be

testing the device ID of one DIE while bypassing the others.

Each pin of the FLEx18 9-Mb device is typically connected to

two DIEs. For connectivity testing with the EXTEST

instruction, it is desirable to check the internal connections

between DIEs as well as the external connections to the

package. This can be accomplished by mergi ng the netlist of

the devices with the netlist of the user’s circuit board. To facil-

itate boundary scan testing of the devices, Cypress provides

the BSDL file for each DIE, the internal netlist of the device,

and a description of the device scan chain. The user can use

these materials to easily integrate the devices into the board’s

boundary scan environment. Further information can be found

in the Cypress application note Using JTAG Boundary Scan

For System In a Package (SIP) Dual-Port SRAMs.

Notes:

21.The “X” in this diagram represent s the counter upper bits.

22.Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.

216 215 2621

2522

242320

216 215 2621

2522

242320

216 215 2621

2522

242320

216 215 2621

2522

242320

0s 1

0101

Xs 1

X0X0

Xs 1

X1X1

Xs 1

X0X0

Masked Address Unmasked Address

Mask

bit-0

Address

Counter

bit-0

CNTINT

Example:

Load

Counter-Mask

Load

Address

Counter = 8

Max

Address

Max + 1

Address

Figure 2. Programmable Counter-Mask Register Operation[1, 21]

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 10 of 26

Table 4. Ide ntific ation Register Definitions

Instruction Field Value Description

Revision Number (31:28) 0h Reserved for version number.

Cypress Device ID (27:12) C090h Defines Cypress part number for CYD04S18V and CYD09S18V DIE

C091h Defines Cypress part number for CYD02S18V

C093h Defines Cypress part number for CYD01S18V

Cypress JEDEC ID (11:1) 034h Allows unique identification of the DP family device vendor.

ID Register Presence (0) 1 Indicates the presence of an ID register.

Table 5. Scan Register Sizes

Instruction 4

Bypass 1

Identification 32

Boundary Scan n[23]

Table 6. Instruction Identification Codes

Instruction Code Description

EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.

BYPASS 1111 Places the BYR between TDI and TDO.

IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO.

HIGHZ 0111 Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.

CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO.

SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO.

NBSRST 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO.

RESERVED All other codes Other combinations are reserved. Do not use other than the above.

Note:

23.See details in the de vice BSDL file.

TDO

TDI

TDO

TDI

TDO

Figure 3. Scan Chain for 9-Mbit Device

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 11 of 26

Maximum Ratings[24]

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ................................. –65 °C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +4.6V

DC Voltage Applied to

Outputs in High-Z State...........................–0.5V to VDD +0.5V

DC Input Voltage..................... ... .......–0.5V to VDD + 0.5V[25]

Output Current into Outputs (LOW).............................20 mA

Static Discharge V o ltage...........................................> 2000V

(JEDEC JESD22-A114-2000B)

Latch-up Current.....................................................> 200 mA

Operating Range

Range Ambient

Temperature VDDIO/VTTL VCORE[12]

Commercial 0°C to +70°C 3.3V±165 mV 1.8V±100 mV

Industrial –40°C to +85°C 3.3V±165 mV 1.8V±100 mV

Electrical Characteristics Over the Operating Range

Parameter Description

-167 -133 -100

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

VOH Output HIGH V oltage (V DD = Min., IOH= –4.0 mA) 2.4 2.4 2.4 V

VOL Output LOW V oltage (VDD = Min., IOL= +4.0 mA) 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.0 2.0 2.0 V

VIL Input LOW Voltage 0.8 0.8 0.8 V

IOZ Output Leakage Current –10 10 –10 10 –10 10 µA

IIX1 Input Leakage Current Except TDI, TMS, MRST –10 10 –10 10 –10 10 µA

IIX2 Input Leakage Current TDI, TMS, MRST –1.0 0.1 –1.0 0.1 –1.0 0.1 mA

ICC Operating Current for

(VDD = Max.,IOUT = 0 mA),

Outputs Disabled

CYD01S18V

CYD02S18V

CYD04S18V

225 300 225 300 mA

CYD09S18V 270 400 200 310 mA

ISB1[26] Standby Current (Both Ports TTL Level)

CEL and CER ≥ VIH, f = fMAX 90 115 90 115 mA

ISB2[26] Standby Current (One Port TTL Level)

CEL | CER ≥ VIH, f = fMAX 160 210 160 210 mA

ISB3[26] Standby Current (Both Ports CMOS Level)

CEL and CER ≥ VDD – 0.2V, f = 0 55 75 55 75 mA

ISB4[26] Standby Current (One Port CMOS Level)

CEL | CER ≥ VIH, f = fMAX 160 210 160 210 mA

ISB5 Operating Current (VDDIO =

Max, Iout=0mA,f=0)

Outputs Disabled

CYD09S18V 75 75 mA

ICORE[12] Core Operating Current for (VDD = Max.,

IOUT = 0 mA), Outputs Disabled 00 00 00mA

Capacitance[27]

Part Number Parameter Description Test Conditions Max. Unit

CYD01S18V

CYD02S18V

CYD04S18V

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V 13 pF

COUT Output Capacitance 10 pF

CYD09S18V CIN Input Capacitance 22 pF

COUT Output Capacitance 20 pF

Notes:

24.The voltage on any input or I/O pin can not exceed the power pin during power-up.

25.Pulse width < 20 ns.

26.ISB1, ISB2, ISB3 and ISB4 are not applicable for CYD09S18V because it can not be powered down by using chip enable pins.

27.COUT also references CI/O

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 12 of 26

AC Test Load and Waveforms

R1 = 590Ω

R2 = 435Ω

C = 5 pF

(b) Three-state Delay (Load 2)

90%

10%

3.0V

Vss

90%

10%

<2ns <2ns

ALL INPUT PULSES

VTH = 1.5V

R = 50Ω

Z0 = 50Ω

(a) Normal Load (Load 1)

C = 10 pF

OUTPUT

Switching Characteristics Over the Operating Range

Parameter Description

-167 -133 -100

Unit

CYD01S18V

CYD02S18V

CYD04S18V

CYD01S18V

CYD02S18V

CYD04S18V CYD09S18V CYD09S18V

Min. Max. Min. Max. Min. Max. Min. Max.

fMAX2 Maximum Operating Frequency 167 133 133 100 MHz

tCYC2 Clock Cycle Time 6.0 7.5 7.5 10 ns

tCH2 Clock HIGH Time 2.7 3.0 3.0 4.0 ns

tCL2 Clock LOW Time 2.7 3.0 3.0 4.0 ns

tR[28] Clock Rise Time 2.0 2.0 2.0 3.0 ns

tF[28] Clock Fall Time 2.0 2.0 2.0 3.0 ns

tSA Address Set-up Time 2.3 2.5 2.5 3.0 ns

tHA Address Hold Time 0.6 0.6 0.6 0.6 ns

tSB Byte Select Set-up Time 2.3 2.5 2.5 3.0 ns

tHB Byte Select Hold Time 0.6 0.6 0.6 0.6 ns

tSC Chip Enable Set-up Time 2.3 2.5 NA NA ns

tHC Chip Enable Hold Time 0.6 0.6 NA NA ns

tSW R/W Set-up Time 2.3 2.5 2.5 3.0 ns

tHW R/W Hold Time 0.60.60.60.6ns

tSD Input Data Set-up Time 2.3 2.5 2.5 3.0 ns

tHD Input Data Hold Time 0.6 0.6 0.6 0.6 ns

tSAD ADS Set-up Time 2.3 2.5 NA NA ns

tHAD ADS Hold Time 0.6 0.6 NA NA ns

tSCN CNTEN Set-up Time 2.3 2.5 NA NA ns

tHCN CNTEN Hold Time 0.6 0.6 NA NA ns

tSRST CNTRST Set-up Time 2.3 2.5 NA NA ns

tHRST CNTRST Hold Time 0.6 0.6 NA NA ns

tSCM CNT/MSK Set-up Time 2.3 2.5 NA NA ns

tHCM CNT/MSK Hold Ti me 0.6 0.6 NA NA ns

tOE Output Enable to Data Valid 4.0 4.4 4.7 5.0 ns

tOLZ[29, 30] OE to Low Z 0000ns

Notes:

28.Except JTAG signals (tr and tf < 10 ns [max.]).

29.This parameter is guaranteed by design, but it is not production tested.

30.Test conditions used are Load 2.

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 13 of 26

tOHZ[29, 30] OE to High Z 04.004.404.705.0ns

tCD2 Clock to Data Valid 4.0 4.4 4.7 5.0 ns

tCA2 Clock to Counter Address Valid 4.0 4.4 NA NA ns

tCM2 Clock to Mask Register Readback

Valid 4.0 4.4 NA NA ns

tDC Data Output Hold After Clock HIGH 1.0 1.0 1.0 1.0 ns

tCKHZ[29,30] Clock HIGH to Output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns

tCKLZ[29, 30] Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns

tSINT Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns

tRINT Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns

tSCINT Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns

tRCINT Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns

Port to Port Delays

tCCS Clock to Clock Skew 5.2 6.0 6.0 8.0 ns

Master Reset Timing

tRS Master Reset Pulse Width 5.0 5.0 5.0 5.0 cycles

tRS Master Reset Set-up Time 6.0 6.0 6.0 8.5 ns

tRSR Master Reset Recovery Time 5.0 5.0 5.0 5.0 cycles

tRSF Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns

tRSINT Master Reset to Counter and Mailbox

Interrupt Flag Reset Time 10.0 10.0 NA NA ns

Switching Characteristics Over the Operating Range (continued)

Parameter Description

-167 -133 -100

Unit

CYD01S18V

CYD02S18V

CYD04S18V

CYD01S18V

CYD02S18V

CYD04S18V CYD09S18V CYD09S18V

Min. Max. Min. Max. Min. Max. Min. Max.

JTAG Timing and Switching Waveforms

Parameter Description

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V UnitMin. Max.

fJTAG Maximum JTAG TAP Controller Frequency 10 MHz

tTCYC TCK Clock Cycle Time 100 ns

tTH TCK Clock HIGH Time 40 ns

tTL TCK Clock LOW Time 40 ns

tTMSS TMS Set-up to TCK Clock Rise 10 ns

tTMSH TMS Hold After TCK Clock Rise 10 ns

tTDIS TDI Set-up to TCK Clock Rise 10 n s

tTDIH TDI Hold After TCK Clock Rise 10 ns

tTDOV TCK Clock LOW to TDO Valid 30 ns

tTDOX TCK Clock LOW to TDO Invalid 0 ns

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 14 of 26

Test Clock

Test Mode Select

TCK

TMS

Test Data-In

TDI

Test Data-Out

TDO

tTCYC

tTMSH

tTL

tTH

tTMSS

tTDIS tTDIH

tTDOX tTDOV

Switching Waveforms

Master Reset

MRST

tRSR

tRS

INACTIVE ACTIVE

TMS

TDO

INT

CNTINT

tRSF

tRSS

ALL

ADDRESS/

DATA

LINES

ALL

OTHER

INPUTS

tRSINT

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 15 of 26

Read Cycle[13, 31, 32, 33, 34]

Notes:

31.OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.

32.ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.

33.The output is disabled (high-impedance state) by CE = VIH fo llowing the next rising edge of the clock.

34.Addresses do not ha ve to b e accesse d sequenti ally since ADS = CNTEN = V IL with CNT/MSK = VIH const a ntl y loads t he address on t he ri si ng ed ge of th e CLK.

Numbers are for reference only.

Switching Waveforms (continued)

tCH2 tCL2

tCYC2

tSC tHC

tSW tHW

tSA tHA

AnAn+1

CLK

R/W

ADDRESS

DATAOUT

An+2 An+3

tSC tHC

tOHZ

tOE

tOLZ

tDC

tCD2

tCKLZ

QnQn+1 Qn+2

1 Latency

BE0–BE1

tSB tHB

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 16 of 26

Bank Select Read[35, 36]

Read-to-Write-to-Read (OE = LOW)[34, 37, 38, 39, 40]

Notes:

35.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank co nsists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1)

= ADDRES S (B2).

36. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.

37.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.

38.During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.

39. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

40.CE0 = BE0 – BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be

completed (labelled as no operation). One clock cycle is required to thre e-state the I/O for the Write operation on the next ri sing edge of CLK.

Switching Waveforms (continued)

A0A1A2A3A4A5

tSA tHA

tSC tHC

tSA tHA

tSC tHC

tSC tHC tCKHZ

tDC

tCD2

tCKLZ

tCD2 tCD2 tCKHZ

tCKLZ

tCD2 tCKHZ

tCKLZ

tCD2

tCH2 tCL2

tCYC2

CLK

ADDRESS(B1)

CE(B1)

DATAOUT(B2)

DATAOUT(B1)

ADDRESS(B2)

CE(B2)

tCYC2tCL2

tCH2

tHC

tSC

CLK

R/W

ADDRESS

DATAIN

DATAOUT

tHW

tSW

tHA

tSA

tHW

tSW

tCD2 tDC

tSD tHD

WRITE

AnAn+1 An+2 An+2 An+2 An+3

tCKHZ

NO OPERATION

READ

Dn+2

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 17 of 26

Read-to-Write-to-Read (OE Controlled)[34, 37, 39, 40]

Read with Address Counter Ad vance[39]

Switching Waveforms (continued)

tCYC2tCL2

tCH2

tHC

tSC

tHW

tSW

tHA

tSA

AnAn+1 An+2 An+3 An+4 An+5

tHW

tSW

tSD tHD

Dn+2

tCD2

tOHZ

READ READWRITE

Dn+3

CLK

R/W

ADDRESS

DATAIN

DATAOUT

Qn+4

tCD2

tSA tHA

tCH2 tCL2

tCYC2

CLK

ADDRESS An

COUNTER HOLD

READ WITH COUNTER

tSAD tHAD

tSCN tHCN

tSAD tHAD

tSCN tHCN

Qx–1 QxQnQn+1 Qn+2 Qn+3

tDC

tCD2

READ WITH COUNTER

READ

EXTERNAL

ADDRESS

ADS

CNTEN

DATAOUT

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 18 of 26

Write with Address Counter Advance [40]

Switching Waveforms (continued)

tCH2 tCL2

tCYC2

AnAn+1 An+2 An+3 An+4

Dn+1 Dn+1 Dn+2 Dn+3 Dn+4

tSAD tHAD

tSCN tHCN

tSD tHD

WRITE EXTERNAL WRITE WITH COUNTER

ADDRESS WRITE WITH

COUNTER WRITE COUNTER

HOLD

CLK

ADDRESS

INTERNAL

DATAIN

ADDRESS

tSA tHA

CNTEN

ADS

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 19 of 26

Counter Reset[41, 42]

Notes:

41.CE0 = BE0 – BE1 = LOW; CE1 = MRST = CNT/MSK = HIGH.

42.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental wi th the counter reset.

43.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.

Switching Waveforms (continued)

CLK

ADDRESS

INTERNAL

CNTEN

ADS

DATAIN

ADDRESS

CNTRST

R/W

DATAOUT

AnAmAp

Ax01AnAmAp

Q1Qn

tCH2 tCL2

tCYC2

tSA tHA

tSW tHW

tSRST tHRST

tSD tHD

tCD2 tCD2

tCKLZ

[43]

RESET ADDRESS 0

COUNTER WRITE READ

ADDRESS 0 ADDRESS 1

READ READ

ADDRESS AnADDRESS Am

READ

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 20 of 26

Readback State of Address Counter or Mask Register[44, 45, 46, 47]

Notes:

44.CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

45.Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.

46.Address in input mode. Host can drive address bus after tCKHZ.

47.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.

Switching Waveforms (continued)

CNTEN

CLK

tCH2 tCL2

tCYC2

ADDRESS

ADS

Qx-2 Qx-1 Qn

tSA tHA

tSAD tHAD

tSCN tHCN

LOAD

ADDRESS

EXTERNAL

tCD2

INTERNAL

ADDRESS An+1 An+2

tCKHZ

DATAOUT

n+3

Qn+1 Qn+2

An+3 An+4

tCKLZ

tCA2 or tCM2

READBACK

INTERNAL

COUNTER

ADDRESS

INCREMENT

EXTERNAL

A0–A16

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 21 of 26

Left_Port (L_Port) Write to Right_Port (R_Port) Read[48, 49 , 50]

Notes:

48.CE0 = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.

49.This timing is valid when one port is writ ing, and other port i s reading the same location at t he same time. If tCCS is violated, indeterminat e data will be Read out.

50.If tCCS < minimum specified value, then R_P ort will Read the most recen t data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Po rt's clock. If

tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) af ter the rising edge of R_Port's clock.

Switching Waveforms (continued)

tSA tHA

tSW tHW

tCH2 tCL2

tCYC2

CLKL

R/WL

tCKHZ tHD

tSA

tHA

tDC

tCCS

tSD tCKLZ

tCH2

tCL2

tCYC2

tCD2

L_PORT

ADDRESS

L_PORT

DATAIN

CLKR

R/WR

R_PORT

ADDRESS

R_PORT

DATAOUT

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 22 of 26

Counter Interrupt and Retransmit[16, 43, 51, 52, 53, 54]

Notes:

51.CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

52.CNTINT is always driven.

53.CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.

54.The mask register assumed to have the value of 3FFFFh.

Switching Waveforms (continued)

tCH2 tCL2

tCYC2

CLK

3FFFD 3FFFF

INTERNAL

ADDRESS Last_Loaded Last_Loaded +1

HCM

COUNTER

3FFFE

CNTINT

tSCINT tRCINT

3FFFC

CNTEN

ADS

CNT/MSK

SCM

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 23 of 26

MailBox Interrupt Ti ming[55, 56, 57, 58, 59]

Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 60, 61, 62]

Inputs Outputs

OperationOE CLK CE0CE1R/W DQ0 – DQ17

X H X X High-Z Deselected

X X L X High-Z Deselected

X L H L DIN Write

L L H H DOUT Read

H X L H X High-Z Ou tputs Disabled

Notes:

55.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.

56.Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.

57.L_Port is configured for Write operation, and R_Port is configured for Read operation.

58.At least one byte enable (BE0 – BE1) is required to be active during interrupt oper ations.

59.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the risin g edge of the Read clock.

60.OE is an asynchronous input signal.

61.When CE changes state, deselection and Read happen after one cycle of latency.

62.CE0 = OE = LOW; CE1 = R/W = HIGH.

Switching Waveforms (continued)

CH2

CL2

CYC2

CLK

tCH2 tCL2

tCYC2

CLKR

7FFFF

tSA tHA

An+3

AnAn+1 An+2

L_PORT

ADDRESS

AmAm+4

Am+1 7FFFF Am+3

R_PORT

ADDRESS

INTR

tSA tHA

tSINT tRINT

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 24 of 26

Ordering Information

512K

18 (9Mb) 3.3V Synchronous CYD09S18V Dual-Port SRAM

Speed

(MHz) Ordering Code Package

Name Package Type Operating

Range

133 CYD09S18V-133BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

100 CYD09S18V-100BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

CYD09S18V-100BBI BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Industrial

256K

18 (4Mb) 3.3V Synchronous CYD04S36V Dual-Port SRAM

Speed

(MHz) Ordering Code Package

Name Package Type Operating

Range

167 CYD04S18V-167BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

133 CYD04S18V-133BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

CYD04S18V-133BBI BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Industrial

128K

18 (2Mb) 3.3V Synchronous CYD02S18V Dual-Port SRAM

Speed

(MHz) Ordering Code Package

Name Package Type Operating

Range

167 CYD02S18V-167BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

133 CYD02S18V-133BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

CYD02S18V-133BBI BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Industrial

64K

18 (1Mb) 3.3V Synchronous CYD01S1 8V Dual-Port SRAM

Speed

(MHz) Ordering Code Package

Name Package Type Operating

Range

167 CYD01S18V-167BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

133 CYD01S18V-133BBC BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Commercial

CYD01S18V-133BBI BB256

256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA)

Industrial

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 25 of 26

© Cypress Semi con duct or Cor po rati on , 20 05 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Diagram

FLEx18 and FLEx18-E are trademarks of Cypress Semicon ductor Corp oration. All produ cts and company names mentioned in

this document may be the trademarks of their respective holders.

BOTTOM VIEW

TOP VIEW

10987654321

PIN 1 CORNER

0.20(4X)

Ø0.25MCAB

Ø0.05 M C

Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K)

0.25 C

0.70±0.05

SEATING PLANE

0.15 C

16 15 14 13 12 11

161513 141210 11928765431

Ø0.50 (256X)-ALL OTHER DEVICES

+0.10

-0.05

A1 0.36 0.56

A 1.40 MAX. 1.70 MAX.

REFERENCE JEDEC MO-192

15.00

1.00

0.35

17.00±0.10

7.50

15.00

17.00±0.10

1.00

-0.05

+0.10

256-Ball FBGA (17 x 17 mm) BB256

51-85108-*F

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

Document #: 38-06077 Rev. *C Page 26 of 26

Document History Page

Document Title: CYD01S18V/CYD02S18V/CYD04S18V/CYD09S18V FLEx18™ 3.3V 64K/128K/256K /512K x 18

Synchronous Dual-Port RAM

Document Number: 38-06077

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 259671 See ECN WWZ New data sheet

*A 289711 See ECN YDT Change Pinout D10 from NC to VSS

Changed tRSCNTINT to tRSINT

Added tRSINT to the master reset timing diagram

Added ISB5 and changed IIX2

*B 3 27354 See ECN AEQ Change Pinout C10 from REVR[2,4] to NC[2,5]

Change Pinout G5 from VDDIOL to REVL[2,3]

*C 365320 See ECN YDT Added note for VCORE

Removed preliminary status