ADC141S626
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SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter
Check for Samples: ADC141S626
1FEATURES DESCRIPTION
2• True Differential Inputs The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS
• Guaranteed Performance from 50 kSPS to 250 sampling Analog-to-Digital (A/D) converter. The
kSPS converter is based on a successive-approximation
• External Reference register (SAR) architecture where the differential
nature of the analog inputs is maintained from the
• Zero-Power Track Mode internal sample-and-hold circuits throughout the A/D
• Wide Input Common-Mode Voltage Range converter to provide excellent common-mode signal
• Operating Temperature Range of −40°C to rejection. The ADC141S626 features an external
+85°C reference that can be varied from 1.0V to VA. It also
features a zero-power track mode where the ADC is
• SPI™/QSPI™/MICROWIRE/DSP Compatible consuming the minimum amount of supply current
Serial Interface while the internal sampling capacitor is tracking the
applied analog input voltage.
APPLICATIONS The serial data output is binary 2's complement and
• Automotive Navigation is compatible with several standards, such as SPI™,
• Portable Systems QSPI™, MICROWIRE, and many common DSP
serial interfaces. The conversion result is clocked out
• Medical Instruments by the serial clock input and is the result of the
• Instrumentation and Control Systems conversion currently in progress; thus, ADC141S626
• Motor Control has no latency.
• Direct Sensor Interface The ADC141S626 may be operated with independent
analog (VA) and digital input/output (VIO) supplies. VA
KEY SPECIFICATIONS and VIO can range from 2.7V to 5.5V and can be set
independent of each other. This allows a user to
• Conversion Rate: 50 kSPS to 250 kSPS maximize performance and minimize power
• INL: ± 0.95 LSB (Max) consumption by operating the analog portion of the
• DNL: ± 0.95 LSB (Max) ADC at a VAof 5V while communicating with a 3V
• SNR: 82 dBc (Max) controller on the digital side. With a 3V source, the
power consumption when operating at 200 kSPS is
• THD: -90 dBc (Typ) 2.0 mW. With a 5V source, the power consumption
• ENOB: 13.3 Bits(Min) when operating at 250 kSPS is 4.8 mW. The power
• Power Consumption: consumption drops down to 4 µW and 13 µW
respectively when the ADC141S626 enters
– 200 kSPS, 3V: 2.0 mW (Typ) acquisition (power-down) mode. The differential input,
– 250 kSPS, 5V: 4.8 mW (Typ) low power consumption, and small size make the
– Power-Down, 3V: 4 µW (Typ) ADC141S626 ideal for direct connection to bridge
sensors and transducers in battery operated systems
– Power-Down, 5V: 13 µW (Typ) or remote data acquisition applications.
Operation is guaranteed over the temperature range
of −40°C to +85°C and clock rates of 0.9 MHz to 4.5
MHz. The ADC141S626 is available in a 10-lead
VSSOP package.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SAR CONTROL
SERIAL
INTERFACE
COMPARATOR
S/H CDAC
+IN
-IN
VREF
1
2
3
4
56
7
8
9
10
SCLK
DOUT
GND
- IN
+IN ADC141S626
CS
VREF VA
VIO
GND
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
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Connection Diagram
Block Diagram
PIN DESCRIPTIONS
Pin No. Symbol Description
Voltage Reference Input. A voltage reference between 1V and VAmust be applied to this
input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
1 VREF A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µFcapacitor is
recommended for enhanced performance.
Non-Inverting Input. +IN is the positive analog input for the differential signal applied to the
2 +IN ADC141S626.
Inverting Input. −IN is the negative analog input for the differential signal applied to the
3−IN ADC141S626.
4 GND Ground. GND is the ground reference point for all signals applied to the ADC141S626.
5 GND Ground. GND is the ground reference point for all signals applied to the ADC141S626.
Chip Select Bar. CS must be active LOW during an SPI conversion, which begins on the
6 CS falling edge of CS. The ADC141S626 is in acquisition mode when CS is HIGH.
Serial Data Output. The conversion result is provided on DOUT. The serial data output word
7 DOUT is comprised of 2 null bits followed by 14 data bits (MSB first). During a conversion, the
data is output on the falling edges of SCLK and is valid on the subsequent rising edges.
8 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.
Digital Input/Output Power Supply Input. A voltage source between 2.7V and 5.5V must be
9 VIO applied to this input. VIO must be decoupled to GND with a ceramic capacitor value of 0.1
µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF.
Analog Power Supply Input. A voltage source between 2.7V and 5.5V must be applied to
10 VAthis input. VAmust be decoupled to GND with a ceramic capacitor value of 0.1 µF in
parallel with a bulk capacitor value of 1.0 µF to 10 µF.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)(3)
Analog Supply Voltage VA−0.3V to 6.5V
Digital I/O Supply Voltage VIO −0.3V to 6.5V
Voltage on Any Analog Input Pin to GND −0.3V to (VA+ 0.3V)
Voltage on Any Digital Input Pin to GND −0.3V to (VIO + 0.3V)
Input Current at Any Pin(4) ±10 mA
Package Input Current(4) ±50 mA
Power Consumption at TA= 25°C See(5)
Human Body Model 4000V
ESD Susceptibility(6) Machine Model 300V
Charge Device Model 1250V
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited
to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to five.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC141S626 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply
polarity is reversed). Such conditions should always be avoided.
(6) Human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is a 220 pF capacitor discharged
through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an
automated assembler) then rapidly being discharged.
Operating Ratings(1)(2)
Operating Temperature Range −40°C ≤TA≤+85°C
Supply Voltage, VA+2.7V to +5.5V
Supply Voltage, VIO +2.7V to +5.5V
Reference Voltage, VREF 1.0V to VA
Analog Input Pins Voltage Range 0 to VA
Differential Analog Input Voltage −VREF to +VREF
Input Common-Mode Voltage, VCM See Figure 41
Digital Input Pins Voltage Range 0 to VIO
Clock Frequency 0.9 MHz to 4.5 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance(1)(2)
Package θJA
10-lead VSSOP 240°C / W
(1) Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.
(2) Reflow temperature profiles are different for lead-free packages.
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ADC141S626
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ADC141S626 Converter Electrical Characteristics(1)
The following specifications apply for VA= VIO = VREF = +2.7V to 5.5V and fSCLK = 0.9 to 3.6 MHz or VA= VIO = VREF = +4.5V
to 5.5V and fSCLK = 3.6 to 4.5 MHz; fIN = 20 kHz and CL= 25 pF, unless otherwise noted. Boldface limits apply for TA= TMIN
to TMAX; all other limits are at TA= 25°C.
Symbol Parameter Conditions Typical Limits Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 14 Bits
INL Integral Non-Linearity ±0.5 ±0.95 LSB (max)
DNL Differential Non-Linearity ±0.5 ±0.95 LSB (max)
OE Offset Error −1±5 LSB (max)
Positive Full-Scale Error −3±7 LSB (max)
FSE Negative Full-Scale Error 0.5 ±4 LSB (max)
Positive Gain Error −1.5 ±6 LSB (max)
GE Negative Gain Error 1.5 ±6 LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
VA= VIO = VREF = +3V, −0.1 dBFS 81.9 80.1 dBc (min)
SINAD Signal-to-Noise Plus Distortion Ratio VA= VIO = VREF = +5V, −0.1 dBFS 84.2 82 dBc (min)
VA= VIO = VREF = +3V, −0.1 dBFS 82 80.2 dBc (min)
SNR Signal-to-Noise Ratio VA= VIO = VREF = +5V, −0.1 dBFS 84.3 82 dBc (min)
VA= VIO = VREF = +3V, −0.1 dBFS −102 dBc
THD Total Harmonic Distortion VA= VIO = VREF = +5V, −0.1 dBFS −102 dBc
VA= VIO = VREF = +3V, −0.1 dBFS 97 dBc
SFDR Spurious-Free Dynamic Range VA= VIO = VREF = +5V, −0.1 dBFS 101 dBc
VA= VIO = VREF = +3V, −0.1 dBFS 13.3 13.0 bits (min)
ENOB Effective Number of Bits VA= VIO = VREF = +5V, −0.1 dBFS 13.7 13.3 bits (min)
Differential Input 26 MHz
Output at 70.7%FS
FPBW −3 dB Full Power Bandwidth Single-Ended
with FS Input 22 MHz
Input
ANALOG INPUT CHARACTERISTICS
−VREF V (min)
VIN Differential Input Range +VREF V (max)
IDCL DC Leakage Current VIN = VREF or VIN = -VREF ±1 µA (max)
In Acquisition Mode 30 pF
CINA Input Capacitance In Conversion Mode 3 pF
See the Specification Definitions for the
CMRR Common Mode Rejection Ratio 76 dB
test condition
DIGITAL INPUT CHARACTERISTICS
VIH Input High Voltage VIO = +2.7V to 5.5V 1.9 2.3 V (min)
VIL Input Low Voltage VIO = +2.7V to 5.5V 1.0 0.7 V (max)
IIN Input Current VIN = 0V or VA±1 µA (max)
CIND Input Capacitance 2 4pF (max)
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA VA−0.05 VA−0.2 V (min)
VOH Output High Voltage ISOURCE = 1 mA VA−0.16 V
ISINK = 200 µA 0.01 0.4 V (max)
VOL Output Low Voltage ISINK = 1 mA 0.05 V
IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA±1 µA (max)
COUT TRI-STATE Output Capacitance Force 0V or VA24pF (max)
Output Coding Binary 2'S Complement
(1) Typical values are at TJ= 25°C and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average Outgoing
Quality Level).
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ADC141S626 Converter Electrical Characteristics(1) (continued)
The following specifications apply for VA= VIO = VREF = +2.7V to 5.5V and fSCLK = 0.9 to 3.6 MHz or VA= VIO = VREF = +4.5V
to 5.5V and fSCLK = 3.6 to 4.5 MHz; fIN = 20 kHz and CL= 25 pF, unless otherwise noted. Boldface limits apply for TA= TMIN
to TMAX; all other limits are at TA= 25°C.
Symbol Parameter Conditions Typical Limits Units
POWER SUPPLY CHARACTERISTICS
2.7 V (min)
VAAnalog Supply Voltage Range 5.5 V (max)
2.7 V (min)
VIO Digital Input/Output Supply Voltage Range See(2) 5.5 V (max)
1.0 V (min)
VREF Reference Voltage Range VAV (max)
fSCLK = 3.6 MHz, VA= 3V, fS= 200 540 760 µA (max)
kSPS, fIN = 20 kHz
IVA Analog Supply Current, Conversion Mode
(Conv) fSCLK = 4.5 MHz, VA= 5V, fS= 250 740 970 µA (max)
kSPS, fIN = 20 kHz
fSCLK = 3.6 MHz, VA= 3V, fS= 200 90 190 µA (max)
kSPS, fIN = 20 kHz
IVIO Digital I/O Supply Current, Conversion
(Conv) Mode fSCLK = 4.5 MHz, VA= 5V, fS= 250 170 260 µA (max)
kSPS, fIN = 20 kHz
fSCLK = 3.6 MHz, VA= 3V, fS= 200 25 60 µA (max)
kSPS, fIN = 20 kHz
IVREF Reference Current, Conversion Mode
(Conv) fSCLK = 4.5 MHz, VA= 5V, fS= 250 45 80 µA (max)
kSPS, fIN = 20 kHz
fSCLK = 4.5 MHz, VA= 5V 8 µA
Analog Supply Current, Power Down
IVA (PD) Mode (CS high) fSCLK = 0(3) 23µA (max)
fSCLK = 4.5 MHz, VA= 5V 3 µA
Digital I/O Supply Current, Power Down
IVIO (PD) Mode (CS high) fSCLK = 0(3) 0.1 0.3 µA (max)
fSCLK = 4.5 MHz, VA= 5V 0.1 µA
IVREF Reference Current, Power Down Mode
(PD) (CS high) fSCLK = 0(3) 0.1 0.2 µA (max)
fSCLK = 3.6 MHz, fS= 200 kSPS, fIN = 20 2.0 3.0 mW
kHz, VA= VIO = VREF = 3.0V
PWR Power Consumption, Conversion Mode
(Conv) fSCLK = 4.5 MHz, fS= 250 kSPS, fIN = 20 4.8 6.5 mW
kHz, VA= VIO = VREF = 5.0V
fSCLK = 0, VA= VIO = VREF = 3.0V(3) 34µW (max)
PWR Power Consumption, Power Down Mode
(PD) (CS high) fSCLK = 0, VA= VIO = VREF = 5.0V(3) 13 17 µW (max)
See the Specification Definitions for the
PSRR Power Supply Rejection Ratio −85 dB
test condition.
AC ELECTRICAL CHARACTERISTICS
fSCLK Maximum Clock Frequency VA= VIO = VREF = +2.7V to 5.5V 4.8 4.5 MHz (min)
fSCLK Minimum Clock Frequency 0.9 MHz (max)
fSMaximum Sample Rate(4) 250 kSPS (min)
tACQ Acquisition/Track Time 667 ns (min)
tCONV Conversion/Hold Time 15 SCLK cycles
tAD Aperture Delay See the Specification Definitions. 6 ns
(2) The value of VIO is independent of the value of VA. For example, VIO could be operating at 5V while VAis operating at 3V or VIO could
be operating at 3V while VAis operating at 5V.
(3) This parameter is guaranteed by design and/or characterization and is not tested in production.
(4) While the maximum sample rate is fSCLK/18, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/18.
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1.6V
TO OUTPUT
PIN CL
25 pF
IOH
IOL
2 mA
2 mA
SCLK
CS
tCSS
1 2
4 5 11 12 13 14 15 16
tACQ (Power-Down)
tCONV (Power-Up)
DB13 DB12 DB5 DB4 DB3 DB2
1
D`
SCLK
CS
2 3 17 18
0
00
1
DB1 DB0
2
tEN tDIS
tCL
tCH
0
tCS
ADC141S626
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ADC141S626 Timing Specifications(1)
The following specifications apply for VA= VIO = VREF= +2.7V to 5.5V and fSCLK = 0.9 to 4.5 MHz, CL= 25 pF, Boldface limits
apply for TA= TMIN to TMAX: all other limits TA= 25°C.
Symbol Parameter Conditions Typical Limits Units
36ns (min)
tCSS CS Setup Time prior to an SCLK rising edge 1/fSCLK - 3 1/fSCLK - 6 ns (max)
tDH DOUT Hold Time after an SCLK falling edge 10 6ns (min)
tDA DOUT Access Time after an SCLK falling edge 28 40 ns (max)
tDIS DOUT Disable Time after the rising edge of CS(2) 10 20 ns (max)
tCS Minimum CS Pulse Width 5 20 ns (min)
tEN DOUT Enable Time after the falling edge of CS 32 51 ns (max)
tCH SCLK High Time 67 89 ns (min)
tCL SCLK Low Time 67 89 ns (min)
trDOUT Rise Time 7 ns
tfDOUT Fall Time 7 ns
(1) Typical values are at TJ= 25°C and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average Outgoing
Quality Level).
(2) tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit.
Timing Diagrams
Figure 1. ADC141S626 Single Conversion Timing Diagram
Figure 2. Timing Test Circuit Figure 3. Valid CS Assertion Times
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VIL
2.3V
0.7V
DOUT
SCLK
tDH
tDA
DOUT
CS VIH
tDIS
90%
10%
90%
10%
DOUT
90%
10%
DOUT
tf
tr
0.9 x VIO
0.1 x VIO
ADC141S626
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Figure 4. DOUT Rise and Fall Times Figure 5. Voltage Waveform for tDIS
Figure 6. DOUT Hold and Access Times
Specification Definitions
APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is
sampled for conversion.
COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input
pins are rejected.
To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed
from 2V to 3V.
CMRR = 20 LOG ( ΔCommon Input / ΔOutput Offset) (1)
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is equivalent to
a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive
Full-Scale Error and Negative Full-Scale Error and can be calculated as:
Gain Error = Positive Full-Scale Error −Negative Full-Scale Error (2)
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
½ LSB below the first code transition through ½ LSB above the last code transition. The deviation of any given
code from this straight line is measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC141S626 is
guaranteed not to have any missing codes.
NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions from negative full scale to the next code and −VREF + 1 LSB
NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error.
OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from
code 0000h to 0001h and 1 LSB.
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POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions to positive full scale and VREF minus 1 LSB.
POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage
is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage,
expressed in dB. For the ADC141S626, VAis changed from 4.5V to 5.5V.
PSRR = 20 LOG (ΔOutput Offset / ΔVA) (3)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below one-half the sampling frequency,
including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component below one-half the sampling frequency,
where a spurious spectral component is any signal present in the output spectrum that is not present at the input
and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the
output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as
(4)
where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the
first 5 harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversion.
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Typical Performance Characteristics
VA= VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA= +25°C, and fIN = 20 kHz unless otherwise stated.
DNL - 250 kSPS INL - 250 kSPS
Figure 7. Figure 8.
DNL vs. VAINL vs. VA
Figure 9. Figure 10.
DNL vs. VREF INL vs. VREF
Figure 11. Figure 12.
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Typical Performance Characteristics (continued)
VA= VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA= +25°C, and fIN = 20 kHz unless otherwise stated.
DNL vs. SCLK FREQUENCY INL vs. SCLK FREQUENCY
Figure 13. Figure 14.
DNL vs. TEMPERATURE INL vs. TEMPERATURE
Figure 15. Figure 16.
SINAD vs. VATHD vs. VA
Figure 17. Figure 18.
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Typical Performance Characteristics (continued)
VA= VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA= +25°C, and fIN = 20 kHz unless otherwise stated.
SINAD vs. VREF THD vs. VREF
Figure 19. Figure 20.
SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY
Figure 21. Figure 22.
SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY
Figure 23. Figure 24.
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Typical Performance Characteristics (continued)
VA= VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA= +25°C, and fIN = 20 kHz unless otherwise stated.
SINAD vs. TEMPERATURE THD vs. TEMPERATURE
Figure 25. Figure 26.
VACURRENT vs. VAVACURRENT vs. SCLK FREQUENCY
Figure 27. Figure 28.
VACURRENT vs. TEMPERATURE VREF CURRENT vs. VREF
Figure 29. Figure 30.
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Typical Performance Characteristics (continued)
VA= VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA= +25°C, and fIN = 20 kHz unless otherwise stated.
VREF CURRENT vs. SCLK FREQUENCY VREF CURRENT vs. TEMPERATURE
Figure 31. Figure 32.
VIO CURRENT vs. VIO VIO CURRENT vs. SCLK FREQUENCY
Figure 33. Figure 34.
VIO CURRENT vs. TEMPERATURE SPECTRAL RESPONSE - 250 kSPS
Figure 35. Figure 36.
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FUNCTIONAL DESCRIPTION
The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter
uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an
inherent sample-and-hold function. The differential nature of the analog inputs is maintained from the internal
sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection.
The ADC141S626 operates from independent analog and digital supplies. The analog supply (VA) can range
from 2.7V to 5.5V and the digital input/output supply (VIO) can range from 2.7V to 5.5V. The ADC141S626
utilizes an external reference (VREF), which can be any voltage between 1V and VA. The value of VREF
determines the range of the analog input, while the reference input current (IREF) depends upon the conversion
rate.
The analog input is presented to two input pins: +IN and –IN. Upon initiation of a conversion, the differential input
at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry
while a conversion is in progress. The ADC141S626 features a zero-power track mode where the ADC is
consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied
analog input voltage. Zero-power track mode is exercised by bringing chip select bar (CS) high or low after the
conversion is complete (after the 16th falling edge of the serial clock).
The ADC141S626 communicates with other devices via Serial Peripheral Interface (SPI™) , a synchronous serial
interface that operates using three pins: chip select bar (CS), serial clock (SCLK), and serial data out (DOUT). The
external SCLK controls data transfer and serves as the conversion clock. The duty cycle of SCLK is essentially
unimportant, provided the minimum clock high and low times are met. The minimum SCLK frequency is set by
internal capacitor leakage. Each conversion requires 18 SCLK cycles to complete. If less than 14 bits of
conversion data are required, CS can be brought high at any point during the conversion. This procedure of
terminating a conversion prior to completion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit (MSB)
first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in
progress and thus there is no pipe line delay.
REFERENCE INPUT (VREF)
The externally supplied reference voltage (VREF) sets the analog input range. The ADC141S626 will operate with
VREF in the range of 1V to VA.
Operation with VREF below 1V is also possible with slightly diminished performance. As VREF is reduced, the
range of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage (VCM), the
differential peak-to-peak input range is limited to (2 x VREF). See Input Common Mode Voltage for more details.
Reducing VREF also reduces the size of the least significant bit (LSB). The size of one LSB is equal to [(2 x VREF)
/ 2n], which is 16,384 where n is 14 bits. When the LSB size goes below the noise floor of the ADC141S626, the
noise will span an increasing number of codes and overall performance will suffer. For example, dynamic signals
will have their SNR degrade, while D.C. measurements will have their code uncertainty increase. Since the noise
is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of
consecutive conversions.
Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D
converter will increase in terms of LSB size as VREF is reduced.
VREF and analog inputs (+IN and -IN) are connected to the capacitor array through a switch matrix when the input
is sampled. Hence, IREF, I+IN, and I-IN are a series of transient spikes that occur at a frequency dependent on the
operating sample rate of the ADC141S626.
IREF changes only slightly with temperature. See Figure 31 and Figure 32 in Typical Performance Characteristics
for additional details.
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC141S626
|
|
|
01 1111 1111 1111b
|
|
|
10 0000 0000 0000b
00 0000 0000 0000b
ADC Output Code
Analog Input
-1 LSB
+1 LSB
+VREF±1LSB
-VREF+1LSB
ADC141S626
www.ti.com
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
ANALOG SIGNAL INPUTS
The ADC141S626 has a differential input where the effective input voltage that is digitized is (+IN) −(−IN). By
using this differential input, small signals common to both inputs are rejected. As shown in Figure 37, noise is
immune at low frequencies where the common-mode rejection ratio (CMRR) is 90 dB. As the frequency
increases to 1 MHz, the CMRR rolls off to 40 dB . In general, operation with a fully differential input signal or
voltage will provide better performance than with a single-ended input. However, if desired, the ADC141S626
can be presented with a single-ended input.
Figure 37. Analog Input CMRR vs. Frequency
The current required to recharge the input sampling capacitor will cause voltage spikes at +IN and −IN. Do not
try to filter out these noise spikes. Rather, ensure that the transient settles out during the acquisition period.
Differential Input Operation
As shown in Figure 38 for a fully differential input signal, a positive full scale output code (01 1111 1111 1111b or
1FFFh or 8191d) will be obtained when (+IN) −(−IN) is greater than or equal to (VREF −1 LSB). A negative full
scale code (10 0000 0000 0000b or 2000h or -8192d) will be obtained when (+IN) −(−IN) is less than or equal to
(−VREF + 1 LSB). This ignores gain, offset and linearity errors, which will affect the exact differential input voltage
that will determine any given output code. Both inputs should be biased at a common mode voltage (VCM), which
will be thoroughly discussed in Input Common Mode Voltage .Figure 39 shows the ADC141S626 being driven
by a full-scale differential source.
Figure 38. ADC Output vs. Input for a Differential Input Operation
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: ADC141S626
Differential Input
1.25
0.0 1.0 2.0 3.0 4.0 5.0
3.75
VA = 5.0V
VREF (V)
COMMON-MODE VOLTAGE (V)
2.5
0
5
-1
6
2.5
Single-Ended Input
1.25
0.0 0.75 1.75 2.5
3.75
VA = 5.0V
VREF (V)
COMMON-MODE VOLTAGE (V)
2.5
0
5
-1
6
1.25
+
-
ADC141S626
CS
SRC
VREF
RS
VCM
VCM
VCM + VREF
VCM - VREF
+
-
ADC141S626
CS
SRC
VREF RS
RS
VCM
VCM -VREF
2
VCM + VREF
2
VCM
VCM -VREF
2
VCM + VREF
2
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
www.ti.com
Figure 39. Differential Input
Single-Ended Input Operation
For single-ended operation, the non-inverting input (+IN) of the ADC141S626 can be driven with a signal that has
a peak-to-peak range that is equal to or less than (2 x VREF). The inverting input (−IN) should be biased at a
stable VCM that is halfway between these maximum and minimum values. In order to utilize the entire dynamic
range of the ADC141S626, VREF is limited to VA/ 2. This allows +IN a maximum swing range of ground to VA.
Figure 40 shows the ADC141S626 being driven by a full-scale single-ended source.
Figure 40. Single-Ended Input
Since the design of the ADC141S626 is optimized for a differential input, the performance degrades slightly when
driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and
dynamic characteristics such as SINAD typically degrade by 2 dB. Note that single-ended operation should only
be used if the performance degradation (compared with differential operation) is acceptable.
Input Common Mode Voltage
The allowable input common mode voltage (VCM) range depends upon VAand VREF used for the ADC141S626.
The ranges of VCM are depicted in Figure 41 and Figure 42. Note that these figures only apply to a VAof 5V.
Equations for calculating the minimum and maximum VCM for differential and single-ended operations are shown
in Table 1.
Figure 41. VCM range for Differential Input Figure 42. VCM range for single-ended operation
operation
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Product Folder Links: ADC141S626
ADC141S626
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SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
Table 1. Allowable VCM Range
Input Signal Minimum VCM Maximum VCM
Differential VREF / 2 VA−VREF / 2
Single-Ended VREF VA−VREF
SERIAL DIGITAL INTERFACE
The ADC141S626 communicates via a synchronous 3-wire serial interface as shown in Figure 1 or re-shown in
Figure 43 for convenience. CS, chip select bar, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC141S626's DOUT
pin is in a high impedance state when CS is high and is active when CS is low; thus. CS acts as an output
enable.
The ADC141S626 samples the differential input upon the assertion of CS. Assertion is defined as bringing the
CS pin to a logic low state. For the first 15 periods of the SCLK following the assertion of CS, the ADC141S626
is converting the analog input voltage. On the 16th falling edge of SCLK, the ADC141S626 enters acquisition
(tACQ) mode. For the next three periods of SCLK, the ADC141S626 is operating in acquisition mode where the
ADC input is tracking the analog input signal applied across +IN and -IN. During acquisition mode, the
ADC141S626 is consuming a minimal amount of power.
The ADC141S626 can enter conversion mode (tCONV) under three different conditions. The first condition
involves CS going low (asserted) with SCLK high. In this case, the ADC141S626 enters conversion mode on the
first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this
condition, the ADC141S626 automatically enters conversion mode and the falling edge of CS is seen as the first
falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC141S626 enters
conversion mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, there is a
minimum and maximum setup time requirements for the falling edge of CS with respect to the rising edge of
SCLK. See Figure 3 in the Timing Diagrams section for more information.
CS Input
The CS (chip select bar) input is active low and is TTL and CMOS compatible. The ADC141S626 enters
conversion mode when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the
ADC141S626 is always in acquisition mode and thus consuming the minimum amount of power. Since CS must
be asserted to begin a conversion, the sample rate of the ADC141S626 is equal to the assertion rate of CS.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time
(the 3rd falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in
the Timing Specifications.
SCLK Input
The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is TTL and
CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor
leakage limits the minimum clock frequency. The ADC141S626 offers guaranteed performance with the clock
rates indicated in the Electrical Characteristics.
The ADC141S626 enters acquisition mode on the 16th falling edge of SCLK during a conversion frame.
Assuming that the LSB is clocked into a controller on the 16th rising edge of SCLK, there is a minimum
acquisition time period that must be met before a new conversion frame can begin. Other than the 16th rising
edge of SCLK that was used to latch the LSB into a controller, there is no requirement for the SCLK to transition
during acquisition mode. Therefore, it is acceptable to idle SCLK after the LSB has been latched into the
controller.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADC141S626
4 5 11 12 13 14 15 16
tACQ (Power-Down)
tCONV (Power-Up)
DB13 DB12 DB5 DB4 DB3 DB2
1
D`
SCLK
CS
2 3 17 18
0
00
1
DB1 DB0
2
tEN tDIS
tCL
tCH
0
tCS
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
www.ti.com
Data Output
The data output format of the ADC141S626 is two’s complement as shown in Figure 38. This figure indicates the
ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or
noise. Each data output bit is output on the falling edges of SCLK. The 1st and 2nd SCLK falling edges clock out
leading zeros while the 3rd to 16th SCLK falling edges clock out the conversion result, MSB first.
While most receiving systems will capture the digital output bits on the rising edges of SCLK, the falling edges of
SCLK may be used to capture the conversion result if the minimum hold time for DOUT is acceptable. See
Figure 6 for DOUT hold (tDH) and access (tDA) times.
DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th
falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new
conversion will begin when CS is driven LOW.
Figure 43. ADC141S626 Single Conversion Timing Diagram
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC141S626:
−40°C ≤TA≤+85°C
+2.7V ≤VA≤+5.5V
+2.7V ≤VIO ≤+5.5V
1V ≤VREF ≤VA
0.9 MHz ≤fSCLK ≤4.5 MHz
VCM: See Input Common Mode Voltage
POWER CONSUMPTION
The architecture, design, and fabrication process allow the ADC141S626 to operate at conversion rates up to
250 kSPS while consuming very little power. The ADC141S626 consumes the least amount of power while
operating in acquisition (power-down) mode. For applications where power consumption is critical, the
ADC141S626 should be operated in acquisition mode as often as the application will tolerate. To further reduce
power consumption, stop the SCLK while CS is high.
Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 14-bit resolution, or where
an analog signal is being monitored until some condition occurs. In some circumstances, the conversion could be
terminated after the first few bits. This will lower power consumption in the converter since the ADC141S626
spends more time in acquisition mode and less time in conversion mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC141S626
output. This is possible because the ADC141S626 places the latest converted data bit on DOUT as it is
generated. If only 10-bits of the conversion result are needed, for example, the conversion can be terminated by
pulling CS high after the 10th bit has been clocked out.
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Product Folder Links: ADC141S626
ADC141S626
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SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
Burst Mode Operation
Normal operation of the ADC141S626 requires the SCLK frequency to be 18 times the sample rate and the CS
rate to be the same as the sample rate. However, in order to minimize power consumption in applications
requiring sample rates below 250 kSPS, the ADC141S626 should be run with an SCLK frequency of 4.5 MHz
and a CS rate as slow as the system requires. When this is accomplished, the ADC141S626 is operating in burst
mode. The ADC141S626 enters into acquisition mode at the end of each conversion, minimizing power
consumption. This causes the converter to spend the longest possible time in acquisition mode. Since power
consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the system.
PCB LAYOUT AND CIRCUIT CONSIDERATIONS
For best performance, care should be taken with the physical layout of the printed circuit board. This is especially
true with a low VREF or when the conversion rate is high. At high clock rates there is less time for settling, so it is
important that any noise settles out before the conversion begins.
Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may
originate from switching power supplies, digital logic, high power devices, and other sources. Power to the
ADC141S626 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF
capacitor should be used to bypass the ADC141S626 supply, with the 0.1 µF capacitor placed as close to the
ADC141S626 package as possible.
Since the ADC141S626 has both the VAand VIO pins, the user has three options on how to connect these pins.
The first option is to tie VAand VIO together and power them with the same power supply. This is the most cost
effective way of powering the ADC141S626 but is also the least ideal. As stated previously, noise from VIO can
couple into VAand adversely affect performance. The other two options involve the user powering VAand VIO
with separate supply voltages. These supply voltages can have the same amplitude or they can be different.
They may be set independent of each other to any value between 2.7V and 5.5V.
Best performance will typically be achieved with VAoperating at 5V and VIO at 3V. Operating VAat 5V offers the
best linearity and dynamic performance when VREF is also set to 5V; while operating VIO at 3V reduces the power
consumption of the digital logic. Operating the digital interface at 3V also has the added benefit of decreasing the
noise created by charging and discharging the capacitance of the digital interface pins.
Voltage Reference
The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor
value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the
ADC141S626 draws very little current from the reference on average, there are higher instantaneous current
spikes at the reference.
VREF of the ADC141S626, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if
VREF is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external
reference circuitry will appear in the digital results. The use of an active reference source is recommended. The
LM4040 and LM4050 shunt reference families and the LM4132 and LM4140 series reference families are
excellent choices for a reference source.
PCB Layout
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible. Digital circuits create substantial supply and ground current transients. The logic noise
generated could have significant impact upon system noise performance. To avoid performance degradation of
the ADC141S626 due to supply noise, avoid using the same supply for the VAand VREF of the ADC141S626 that
is used for digital circuitry on the board.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: ADC141S626
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
www.ti.com
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated. The analog input should be
isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. The power planes should be
located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog power plane. All digital circuitry should be placed over the digital power plane.
Furthermore, the GND pins on the ADC141S626 and all the components in the reference circuitry and input
signal chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid
connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal
processor, or other high power digital device.
20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC141S626
+
-
+
-
ADC141S626
REF
DAC081S101
Micro-
Controller
LMP7702
100 k:
Bridge
Sensor
AV = 100 V/V
CSB
SCLK
DOUT
SYNCB
SCLK
DIN
100 k:
2 k:
180:
180:
VAVIO
470 pF +5V +5V
+5V
+5V
LM4132-4.1
4.7 PF
++
4.7 PF
0.1 PF
100:
+
ADC141S626
VREF
+IN
- IN
GND
VA
SCLK
DOUT
CSB
0.1 PF
10 PF0.1 PF
+10 PF
+5V
Controller
LM4040-4.1 VIO
ADC141S626
www.ti.com
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
APPLICATION CIRCUITS
The following figures are examples of the ADC141S626 in typical application circuits. These circuits are basic
and will generally require modification for specific circumstances.
Data Acquisition
Figure 44 shows a typical connection diagram for the ADC141S626 operating at VAof +5V. VREF is connected to
a 4.1V shunt reference, the LM4040-4.1, to define the analog input range of the ADC141S626 independent of
supply variation on the +5V supply line. The VREF pin should be de-coupled to the ground plane by a 0.1 µF
ceramic capacitor and a tantalum capacitor of 10 µF. It is important that the 0.1 µF capacitor be placed as close
as possible to the VREF pin while the placement of the tantalum capacitor is less critical. It is also recommended
that the VAand VIO pins of the ADC141S626 be de-coupled to ground by a 0.1 µF ceramic capacitor in parallel
with a 10 µF tantalum capacitor.
Figure 44. Low cost, low power Data Acquisition System
Bridge Sensor Application
Figure 45 shows an example of interfacing a bridge sensor to the ADC141S626. The application assumes that
the bridge sensor requires buffering and amplification to fully utilize the dynamic range of the ADC and thus
optimize the performance of the entire signal path. The amplification stage consists of the LMP7702, a dual
precision amplifier, and some gain setting passive components. The amplification stage offers the benefit of high
input impedance and high amplification capability. On the other hand, it offers no common-mode rejection of
common-mode noise or DC-voltage coming from the bridge sensor.
The DAC081S101, a digital-to-analog converter (DAC), is used to bias the bridge sensor. The DAC provides a
mean for dynamically adjusting the gain of the bridge sensor relative to actual maximum and minimum output
conditions. Another option for biasing the bridge sensor would be powering it from the same +5V power supply
voltage as the VApin on the ADC141S626. This option has the benefit of providing the ideal common-mode input
voltage for the ADC141S626 while keeping design complexity and cost to a minimum. However, any fluctuation
in the +5V supply will still be visible in the converted result. The LM4132-4.1, a 4.1V series reference, is used as
the reference voltage in the application. The ADC141S626, DAC081S101, and the LM4132-4.1 are all powered
from the same +5V voltage source.
Figure 45. Interfacing the ADC141S626 to a Bridge Sensor
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: ADC141S626
+ADC141S626
VREF
+IN
-IN
GND
VA
SCLK
DOUT
0.1 PF
10 PF0.1 PF
+10 PF
+5V
VIO
CSB
VCM
OUT
+5V
GND
IIN
IOUT 2.5V
2.5V + 2.0V
IIN
IOUT
LTSR-1513¶V
LM4132-2.0
ADC Serial
Interface
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
www.ti.com
Current Sensing Application
Figure 46 shows an example of interfacing a current transducer to the ADC141S626. The current transducer
converts an input current into a voltage that is converted by the ADC. Since the output voltage of the current
transducer is single-ended and centered around a common-mode voltage (VCM) of 2.5V, the ADC141S626 is
configured with the output of the transducer driving the non-inverting input and VCM of the transducer driving the
inverting input. The output of the transducer has an output range of ±2V around VCM of 2.5V. As a result, a series
reference voltage of 2.0V is connected to the ADC141S626. This will allow all of the codes of the ADC141S626
to be available for the application. This configuration of the ADC141S626 is referred to as a single-ended
application of a differential ADC. All of the elements in the application are conveniently powered by the same
+5V power supply, keeping circuit complexity and cost to a minimum.
Figure 46. Interfacing the ADC141S626 to a Current Transducer
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ADC141S626
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SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 22
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Product Folder Links: ADC141S626
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC141S626CIMM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 X94C
ADC141S626CIMMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 X94C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC141S626CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADC141S626CIMMX/NOP
BVSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC141S626CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0
ADC141S626CIMMX/NOP
BVSSOP DGS 10 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Mar-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
5.05
4.75
1.1 MAX
8X 0.5
10X 0.27
0.17
2X
2
0.15
0.05
TYP
0.23
0.13
0 - 8
0.25
GAGE PLANE
0.7
0.4
A
NOTE 3
3.1
2.9
B
NOTE 4
3.1
2.9
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
110
0.1 C A B
6
5
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.200
www.ti.com
EXAMPLE BOARD LAYOUT
(4.4)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
10X (1.45)
10X (0.3)
8X (0.5)
(R )
TYP
0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
56
10
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(4.4)
8X (0.5)
10X (0.3)
10X (1.45)
(R ) TYP0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
56
10
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
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