LM1771SMM/NOPB - NATIONAL SEMICONDUCTOR

LM1771

LM1771 Low-Voltage Synchronous Buck Controller with Precision Enable and

No External Compensation

Literature Number: SNVS446B

LM1771

Low-Voltage Synchronous Buck Controller with

Precision Enable and No External Compensation

General Description

The LM1771 is an efficient synchronous buck switching con-

troller with a precision enable requiring no external compen-

sation. The constant on-time control scheme provides a

simple design free of compensation components, allowing

minimal component count and board space. The precision

enable pin allows flexibility in sequencing multiple rails and

setting UVLO. The LM1771 also incorporates a unique input

feed-forward to maintain a constant frequency independent

of the input voltage. The LM1771 is optimized for a low

voltage input range of 2.8V to 5.5V and can provide an

adjustable output as low as 0.8V. Driving an external high

side PFET and low side NFET it can provide efficiencies as

high as 95%.

Three versions of the LM1771 are available depending on

the switching frequency desired for the application. Nominal

switching frequencies are in the range of 100kHz to

1000kHz.

Features

nInput voltage range of 2.8V to 5.5V

n0.8V reference voltage

nPrecision enable

nNo compensation required

nConstant frequency across input range

nLow quiescent current of 400 µA

nInternal soft-start

nShort circuit protection

nTiny LLP-6 package and MSOP-8 package

Applications

nSimple To Design, High Efficiency Step Down Switching

Regulators

nFPGAs, DSPs, and ASIC Power Supplies

nSet-Top Boxes

nCable Modems

nPrinters

nDigital Video Recorders

nServers

nGraphic Cards

Typical Application Circuit

20189001

October 2006

LM1771 Low-Voltage Synchronous Buck Controller with Precision Enable and No External

Compensation

Connection Diagrams

Top View Top View

20189002

6-Lead LLP (3mm x 3mm)

NS Package Number SDE06A

20189040

MSOP-8

NS Package Number MUA08A

Ordering Information

For 6-Lead LLP Package

Order Number Timing Option Package Type

NSC Package

Drawing Top Mark Supplied As

LM1771SSD 500ns

6-Lead LLP SDE06A

1771S 1000 units Tape and Reel

LM1771SSDX 1771S 4500 units Tape and Reel

LM1771TSD 1000ns 1771T 1000 units Tape and Reel

LM1771TSDX 1771T 4500 units Tape and Reel

LM1771USD 2000ns 1771U 1000 units Tape and Reel

LM1771USDX 1771U 4500 units Tape and Reel

For 8-Lead MSOP Package

Order Number Timing Option Package Type

NSC Package

Drawing Top Mark Supplied As

LM1771SMM 500ns

MSOP-8 MUA08A

SNRB 1000 units Tape and Reel

LM1771SMMX SNRB 3500 units Tape and Reel

LM1771TMM 1000ns SNSB 1000 units Tape and Reel

LM1771TMMX SNSB 3500 units Tape and Reel

LM1771UMM 2000ns SNTB 1000 units Tape and Reel

LM1771UMMX SNTB 3500 units Tape and Reel

Pin Descriptions

Pin #

Name FunctionLLP-6 MSOP-8

1 1 FB Feedback Pin

2 2, 3 GND Ground

3 4 HG PFET Gate Drive

4 5 LG NFET Gate Drive

5 6, 7 VIN Input Supply

6 8 EN Enable Pin

DAP - Die Attach Pad is internally connected to GND, but it cannot

be used as the primary GND connection

LM1771

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

-0.3V to 6V

EN, FB, HG, LG -0.3V to V

Storage Temperature Range −65˚C to 150˚C

Junction Temperature 150˚C

Lead Temperature (soldering, 10sec) 260˚C

ESD Rating 2kV

Operating Ratings

to GND 2.8V to 5.5V

Junction Temperature Range (T

) −40˚C to +125˚C

Electrical Characteristics Specifications with standard typeface are for T

= 25˚C, and those in bold face

type apply over the full Junction Temperature Range (−40˚C to +125˚C). Minimum and Maximum limits are guaranteed

through test, design or statistical correlation. Typical values represent the most likely parametric norm at T

= 25˚C and are

provided for reference purposes only. Unless otherwise specified V

= 3.3V.

Symbol Parameter Conditions Min Typ Max Unit

Feedback pin voltage 0.782 0.8 0.818 V

Quiescent current V

= 0.9V 400 700 µA

Switch On-Time

LM1771S - (500ns) 0.4 0.5 0.6

µsLM1771T - (1000ns) 0.8 1.0 1.2

LM1771U - (2000ns) 1.6 2.0 2.4

OFF_MIN

Minimum Off-Time

LM1771S - (500ns) 150 250

nsLM1771T - (1000ns) 135 225

LM1771U - (2000ns) 120 220

Gate Drive Dead-Time 70 ns

IH_EN

EN Pin Rising Threshold 1.15 1.2 1.25 V

EN_HYS

EN Pin Hysteresis 50 200 mV

Feedback pin bias current V

= 0.9V 50 nA

UVLO

Under-voltage lock out V

Rising Edge 2.65 2.8 V

UVLO_HYS

Under-voltage lock out hysteresis 50 mV

SC_TH

Feedback pin Short Circuit Latch

Threshold

0.42 0.55 0.65 V

DS(ON) 1

HG FET driver pull-up On resistance I

=20mA 4 Ω

DS(ON) 2

HG FET driver pull-down On resistance I

=20mA 6 Ω

DS(ON) 3

LG FET driver pull-up On resistance I

=20mA 4 Ω

DS(ON) 4

LG FET driver pull-down On resistance I

=20mA 6 Ω

Note 1: Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for which the device is

intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics.

LM1771

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Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical ap-

plication circuit shown in Application Information section of this datasheet. T

= 25˚C, unless otherwise specified.

vs V

(LM1771S) T

vs V

(LM1771T)

20189007 20189009

vs V

(LM1771U) T

vs Temperature (LM1771S)

20189011 20189008

vs Temperature (LM1771T) T

vs Temperature (LM1771U)

20189010 20189012

LM1771

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Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical

application circuit shown in Application Information section of this datasheet. T

= 25˚C, unless otherwise

specified. (Continued)

OFF

vs Temperature (LM1771S) T

OFF

vs Temperature (LM1771T)

20189013 20189041

OFF

vs Temperature (LM1771U) Feedback Voltage vs Temperature

20189042 20189017

Threshold vs Temperature Short Circuit Threshold vs Temperature

20189014 20189018

LM1771

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Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical

application circuit shown in Application Information section of this datasheet. T

= 25˚C, unless otherwise

specified. (Continued)

Quiescent Current vs Temperature Deadtime vs Temperature

20189016 20189015

Efficiency vs I

OUT

(LM1771T)

= 5V, V

OUT

= 1.8V, F

= 545kHz)

Efficiency vs I

OUT

(LM1771U)

= 5V, V

OUT

= 2.5V, F

= 379kHz)

20189004 20189003

Efficiency vs I

OUT

(LM1771U)

= 5V, V

OUT

= 3.3V, F

= 500kHz)

Efficiency vs I

OUT

(LM1771S)

= 5V, V

OUT

= 1.2V, F

= 727kHz)

20189005 20189006

LM1771

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Block Diagram

20189019

LM1771

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Application Information

THEORY OF APPLICATION

The LM1771 synchronous buck controller has a control

scheme that is referred to as adaptive on-time control. This

topology relies on a fixed switch on-time to regulate the

output voltage. This on-time is internally set by EEPROM

and is available with three different set-points to allow for

different frequency options. The LM1771 automatically ad-

justs the on-time during operation inversely with the input

voltage (VIN) to maintain a constant frequency. Therefore

the switching frequency during continuous conduction mode

is independent of the inductor and capacitor size unlike

hysteretic switchers.

At the beginning of the cycle the LM1771 turns on the high

side PFET for a fixed duration. This on-time is predetermined

(internally set by EEPROM and adjusted by V

) and the

switch will not turn off until the timer has completed its

period. The PFET will then turn off for a minimum pre-

determined time period. This minimum T

OFF

of 150ns is

internally set and cannot be adjusted. This is to prevent false

triggering from occurring on the comparator due to noise

from the SW node transition. After the minimum T

OFF

period

has expired, the PFET will remain off until the comparator

trip-point has been reached. Upon passing this trip-point (set

at 0.8V at the feedback pin), the PFET will turn back on and

the process will repeat, thus regulating the output.

The NFET control is complementary to the PFET control with

the exception of a short dead-time to prevent shoot through

from occurring.

DEVICE OPERATION

Timing Opinion

Three versions of the LM1771 are available each with a

predetermined T

set internally by EEPROM. This T

setting will determine the switching frequency for the appli-

cation. Derivation and calculation of the switching frequen-

cy’s dependence on V

and T

can be seen in the follow-

ing section.

In a PWM buck switcher the following equations can be

manipulated to obtain the switching frequency. The first

equation shows the standard duty-cycle equation given by

the volts-seconds balance on the inductor with the following

equations defining standard relationships:

=DxT

Using these equations and solving for duty-cycle:

D=f

Frequency can now be expressed as:

Or simply written as:

where,

α=V

To maintain a set frequency in an application, αis always

held constant by varying T

inversely with V

. The three

versions of the LM1771 are identified by the on times at a

of 3.3V for consistency. For clarification see the table

below:

Product ID T

@3.3V α(V µs)

LM1771S 0.5µs 1.65

LM1771T 1.0µs 3.3

LM1771U 2.0µs 6.6

The variation of T

versus V

can also be expressed

graphically. These graphs can be found in the typical curves

section of the datasheet.

With αbeing a constant regardless of the version of the

LM1771 used, equation [6] shows that the only dependent

variable remaining is V

OUT

. Since V

OUT

will be a constant in

any application, the frequency will also remain constant. The

switching frequency at which the application runs depends

upon the V

OUT

desired and the LM1771 version chosen. For

any V

OUT

, three frequency options (LM1771 versions) can

be selected. This can be seen in the table below. The rec-

ommended frequency range of operation is 100kHz to

1000kHz.

VOUT

Timing Options

500ns 1000ns 2000ns

0.8 485 242 121

1 606 303 152

1.2 727 364 182

1.5 909 455 227

1.8 1091 545 273

2.5 1515 758 379

3.3 2000 1000 500

Switching Frequency (kHz) of LM1771 based on output voltage and timing

option.

SHORT-CIRCUIT PROTECTION

The LM1771 has an internal short circuit comparator that

constantly monitors the feedback node (except during soft-

start). If the feedback voltage drops below 0.55V (equivalent

to the output voltage dropping below 68% of nominal), the

comparator will trip causing the part to latch off. The LM1771

will not resume switching until the input voltage is taken

below the UVLO threshold and then brought back into its

normal operating range, or the part is disabled then re-

enabled through the enable pin. The purpose of this function

is to prevent a severe short circuit from causing damage to

the application. Due to the fast transient response of the

LM1771 a severe short on the output causing the feedback

to drop would only occur if the load applied had an effective

resistance that approaches the PMOS R

DS(ON)

PRECISION ENABLE

The LM1771 features a precision enable circuit. If the volt-

age on the EN pin is 1.2V or greater, the part is enabled and

switching will occur. If the enable voltage falls below 1.2V,

LM1771

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Application Information (Continued)

the part will be placed into a shutdown state and the drivers

will be tri-stated. This allows the LM1771 to be easily se-

quenced using a resistive divider from the output of another

regulator, or the working input voltage range of the LM1771

to be set using a resistive divider on V

. There is no internal

pull-up connected to the EN pin, so an external signal is

required to initiate switching. It should be noted that when

power is first applied to the LM1771, there is a slight delay

before the enable comparator is functional. During this delay,

typically on the order of 400 µs, the part will be disabled

regardless of the voltage on the EN pin. The falling enable

threshold features 50 mV of hysteresis

SOFT-START

To limit in-rush current and allow for a controlled startup the

LM1771 incorporates an internal soft-start scheme. Every

time the enable voltage rises rises above 1.2V while V

greater than the UVLO threshold, the LM1771 goes through

an adaptive soft-start that limits the on-time and expands the

minimum off-time. In addition the part will only activate the

PMOS allowing a discontinuous mode of operation enabling

a pre-biased startup. The time spent in soft-start will depend

on the load applied to the output, but is usually close to a set

time that is dependent on the timing option. The approximate

soft-start time can be seen below for each timing option.

Product ID Timing T

LM1771S 0.5 µs 1 ms

LM1771T 1.0 µs 1.2 ms

LM1771U 2.0 µs 1.8 ms

It should be noted that as soon as soft-start terminates the

short-circuit protection is enabled. This means that if the

output voltage does not reach at least 68% of its final value

the part will latch off. Therefore, if the input supply is ex-

tremely slow rising such that at the end of soft-start the input

voltage is still near the UVLO threshold, a timing option

should be chosen to ensure that maximum duty-cycle per-

mits the output to meet the minimum condition. As a general

recommendation it is advisable to use the 2000 ns option

(LM1771U) in conditions where the output voltage is 2.5V or

greater to avoid false latch offs when there is concern re-

garding the input supply slew rate.

In some situations, the internal soft-start routine can create a

slight overshoot on the output voltage. If this must be

avoided, the use of a feed-forward capacitor as detailed in

the feed-forward capacitor section of this datasheet is rec-

ommended.

JITTER

The LM1771 utilizes an adaptive on-time control scheme

that relies on the output voltage ripple to provide a consistent

switching frequency. Under certain conditions, excessive

noise can couple onto the feedback pin causing the switch

node to appear to have a slight amount of jitter. This is not

indicative of an unstable design. The output voltage will still

regulate to the exact same value. Careful component selec-

tion and layout should minimize any external influence.

In addition to any external noise that can add to the jitter

seen on the switch node, the LM1771 will always have a

slight amount of switch jitter. This is because the LM1771

makes a small alteration in the reference voltage every 128

cycles to improve its accuracy and long term performance.

This has the effect of causing a change in the switching

frequency at that instant. When viewed on an oscilloscope

this can be seen as a jitter in the switch node. The change in

feedback voltage or output voltage, however, is almost indis-

tinguishable.

Design Guide

The following section walks the designer through the steps

necessary to select the external components to build a fully

functional power supply. As with any DC-DC converter nu-

merous trade-offs are possible to optimize the design for

efficiency, size or performance. These will be taken into

account and highlighted throughout this discussion.

The first equation to calculate for any buck converter is

duty-cycle. Ignoring conduction losses associated with the

FETs and parasitic resistances it can be approximated by:

A more accurate calculation for duty-cycle can be used that

takes into account the voltage drops across the FETs. This

equation can be used to determine the slight load depen-

dency on switch frequency if needed. Otherwise the simpli-

fied equation works well for component calculation.

FREQUENCY SELECTION

The LM1771 is available with three preset timing options that

select the on-time and hence determine the switching fre-

quency of the application. Increasing the switching fre-

quency has the effect of reducing the inductor size needed

for the application while requiring a slight trade-off in effi-

ciency. The table below shows the same frequency table as

shown earlier, with the exception that the recommended

timing option for each V

OUT

is highlighted. It is not recom-

mended to use a high switching frequency with V

OUT

equal

to or greater than 2.5V due to the maximum duty-cycle

limitations of the device coupled with the internal startup.

OUT

Timing Options

500 ns 1000 ns 2000 ns

0.8 485 242 -

1 606 303 -

1.2 727 364 -

1.5 909 455 227

1.8 - 545 273

2.5 - - 379

3.3 - - 500

Recommended switching frequency (kHz) based on output voltage and

timing option.

INDUCTOR SELECTION

The inductor selection is an iterative process likely requiring

several passes before settling on a final value. The reason

for this is because it influences the amount of ripple seen at

the output, a critical component to ensure general stability of

an adaptive on-time circuit. For the first pass at inductor

selection the value can be obtained by targeting a maximum

LM1771

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Design Guide (Continued)

peak-to-peak ripple current equal to 30% of the maximum

load current. The inductor current ripple (∆I

) can be calcu-

lated by:

Therefore, L can be initially set to the following by applying

the 30% rule:

The other features of the inductor that can be selected

besides inductance value are saturation current and core

material. Because the LM1771 does not have a current limit,

it is recommended to have a saturation current higher than

the maximum output current to handle any ripple or momen-

tary over-current events. The core material also influences

the saturation characteristics as ferrite materials have a hard

saturation curve and care should be taken such that they

never saturate during normal use. A shielded inductor or low

profile unshielded inductor is recommended to reduce EMI.

This also helps prevent any spurious noise from picking up

on the feedback node resulting in unexpected tripping of the

feedback comparator.

OUTPUT CAPACITOR

One of the most important components to select with the

LM1771 is the output capacitor. This is because its size and

ESR have a direct effect on the stability of the loop. A

constant on-time control scheme works by sensing the out-

put voltage ripple and switching the FETs appropriately. The

output voltage ripple on a buck converter can be approxi-

mated by stating that the AC inductor ripple flows entirely

into the output capacitor and is created by the ESR of the

capacitor. This can be expressed in the following equation:

∆V

OUT

=∆I

ESR

To ensure stability, two constraints need to be met. The first

is that there is sufficient ESR to create enough voltage ripple

at the feedback pin. The recommendation is to have at least

10mV of ripple seen at the feedback pin. This can be calcu-

lated by multiplying the output voltage ripple by the gain

seen through the feedback resistors. This gain, H, can be

calculated below:

If the output voltage is fairly high, causing significant attenu-

ation through the feedback resistors, a feed-forward capaci-

tor can be used. This is actually recommended for most

circuits as it improves performance. See the feed-forward

capacitor section for more details.

The second criteria is to ensure that there is sufficient ripple

at the output that is in-phase with the switch. The problem

exists that there is actually ripple caused by the capacitor

charging and discharging, not only the ESR ripple. Since

these are effectively out of phase, problems can exist. To

avoid this issue it is recommended that the ratio of the two

ripples (β) is always greater than 5. To calculate the mini-

mum ESR value needed, the following equation can be

used.

In general the best capacitors to use are chemistries that

have a known and consistent ESR across the entire operat-

ing temperature range. Tantalum capacitors or similar chem-

istries such as Niobium Oxide perform well along with certain

families of Aluminum Electrolytics. Small value POSCAPs

and SP CAPs also work as they have sufficient ESR. When

used in conjunction with a low value inductor it is possible to

have an extremely stable design. The only capacitors that

require modification to the circuit are ceramic capacitors.

Ceramic capacitors cause problems meeting both criteria

because they have low ESR and low capacitance. There-

fore, if they are to be used, an external ESR resistor (R

SNS

)

should be added. This can be seen below in the following

circuit.

LM1771

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Design Guide (Continued)

20189029

This circuit uses an additional resistor in series with the

inductor to add ripple at the output. It is placed in this location

and used in combination with the feed-forward capacitor

) to provide ripple to the feedback pin, without adding

ripple or a DC offset to the output. The benefit of using a

ceramic capacitor is still obtained with this technique. Be-

cause the addition of the resistor results in power loss, this

circuit implementation is only recommended for low currents

(2A and below). The power loss and rating of the resistor

should be taken into account when selecting this compo-

nent.

This circuit implementation utilizing the feed-forward capaci-

tor begins to experience limitations when the output voltage

is small. Previously the circuit relied on the C

for all the

ripple at the feedback node by assuming that the resistor

divider was negligible. As V

OUT

decreases this can not be

assumed. The resistor divider contributes a larger amount of

ripple which is problematic as it is also out of phase. There-

fore the resistor location should be changed to be in series

with the output capacitor. This can be viewed as adding an

effective ESR to the output capacitor.

20189030

FEED-FORWARD CAPACITOR

The feed-forward capacitor is used across the top feedback

resistor to provide a lower impedance path for the high

frequency ripple without degrading the DC accuracy. Typi-

cally the value for this capacitor should be small enough to

prevent load transient errors because of the discharging

time, but large enough to prevent attenuation of the ripple

voltage. In general a small ceramic capacitor in the range of

1nF to 10nF is sufficient.

If C

is used then it can be assumed that the ripple voltage

seen at the feedback pin is the same as the ripple voltage at

the output. The attenuation factor H no longer needs to be

used. However, in these conditions, it is recommended to

have a minimum of 20mV ripple at the feedback pin. The use

LM1771

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Design Guide (Continued)

ofaC

capacitor is recommended as it improves the regu-

lation and stability of the design. However, its benefit is

diminished as V

OUT

starts approaching V

REF

, therefore it is

not needed in this situation.

INPUT CAPACITOR

The dominating factor that usually sets an input capacitors’

size is the current handling ability. This is usually determined

by the package size and ESR of the capacitor. If these two

criteria are met then there usually should be enough capaci-

tance to prevent impedance interactions with the source. In

general it is recommended to use a ceramic capacitor for the

input as they provide a low impedance and small footprint.

One important note is to use a good dielectric for the ceramic

capacitor such as X5R or X7R. These provide better over

temperature performance and also minimize the DC voltage

derating that occurs on Y5V capacitors. To calculate the

input capacitor RMS current, the equation below can be

used:

which can be approximated by,

MOSFET Selection

The two FETs used in the LM1771 requires attention to

selection of parameters to ensure optimal performance of

the power supply. The high side FET should be a PFET and

the low side an NFET. These can be integrated in one

package or as two separate packages. The criteria that

matter in selection are listed below:

VDS VOLTAGE RATING

The first selection criteria is to select FETs that have suffi-

cient V

voltage ratings to handle the maximum voltage

seen at the input plus any transient spikes that can occur

from parasitic ringing. In general most FETs available for this

application will have ratings from 8V to 20V. If a larger

voltage rating is used then the performance will most likely

be degraded because of higher gate capacitance.

RDSON

The R

DS(ON)

specification is important as it determines sev-

eral attributes of the FET and the overall power supply. The

first is that it sets the maximum current of the FET for a given

package. A lower R

DS(ON)

will permit a higher allowable

current and reduce conduction losses, however, it will in-

crease the gate capacitance and the switching losses.

GATE DRIVE

The next step is to ensure that the FETs are capable of

switching at the low Vin supplies used by the LM1771. The

FET should have the Rdson specified at either 1.8V or 2.5V

to ensure that it can switch effectively as soon as the

LM1771 starts up.

GATE CHARGE

Because the LM1771 utilizes a fixed dead-time scheme to

prevent cross conduction, the FET transitions must occur in

this time. The rise and fall time of the FETs gate can be

influenced by several factors including the gate capacitance.

Therefore the total gate charge of both FETs should be

limited to less than 20nC at 4.5V V

. The lower the number

the faster the FETs should switch and the better the effi-

ciency.

RISE / FALL TIMES

A better indication of the actual switching times of the FETs

can be found in their electrical characteristics table. The rise

and fall time should be specified and selected to be at a

minimum. This helps improve efficiency and ensuring that

shoot through does not occur.

GATE CHARGE RATIO

Another consideration in selecting the FETs is to pay atten-

tion to the Qgd / Qgs ratio. The reason for this is that proper

selection can prevent spurious turn on. If we look at the

NFET for example, when the FET is turning off, the gate

signal will pull to ground. Conversely the PFET will be turn-

ing on, causing the SW node to rise towards V

. The gate to

drain capacitance of the NFET couples the SW node to the

gate and will cause it to rise. If this voltage is excessive, then

it could weakly turn on the low side FET causing an effi-

ciency loss. However, this coupling is mitigated by having a

large gate to source capacitance of the FET, which helps to

hold the gate voltage down. Ideally, a very low Qgd / Qgs

would be ideal, but in practice it is common to find the

number around 1. As a general rule, the lower the ratio, the

better.

If the above selection criteria have been met it is useful to

generate a figure of merit to allow comparison between the

FETs. One such method is to multiply the R

DS(ON)

of the FET

by the total gate charge. This allows an easy comparison of

the different FETs available. Once again, the lower the prod-

uct, the better.

FEEDBACK RESISTORS

The feedback resistors are used to scale the output voltage

to the internal reference value such that the loop can be

regulated. The feedback resistors should not be made arbi-

trarily large as this creates a high impedance node at the

feedback pin that is more susceptible to noise. A combined

value of 50kΩfor the two resistors is adequate. To calculate

the resistor values use the equation below. Typically the low

side resistor is initially set to a pre-determined value such as

10 kΩ.

is the internal reference voltage that can be found in the

electrical characteristics table or approximated by 0.8V.

The output voltage value can be set in a precise manner by

taking into account the fact that the reference voltage is

regulating the bottom of the output ripple as opposed to the

average value. This relationship is shown in the figure below.

LM1771

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MOSFET Selection (Continued)

20189034

It can be seen that the average output voltage (V

OUT_AC-

TUAL

) is higher than the output voltage (V

OUT_SET

) that was

calculated by the earlier equation by exactly half the output

voltage ripple. The output voltage that is targeted for regu-

lation may then be appended according to the voltage ripple.

This can be seen below:

OUT_ACTUAL

OUT_SET

⁄

∆V

OUT

OUT_SET

⁄

∆I

ESR

Efficiency Calculations

One of the most important parameters to calculate during the

design stage is the expected efficiency of the system. This

can help determine optimal FET selection and can be used

to calculate expected temperature rise of the individual com-

ponents. The individual losses of each component are bro-

ken down and the equations are listed below:

QUIESCENT CURRENT

The quiescent current consumed by the LM1771 is one of

the major sources of loss within the controller. However, from

a system standpoint this is usually less than 0.5% of the

overall efficiency. Therefore, it could easily be omitted but is

shown for completeness:

CONDUCTION LOSS

There are three losses associated with the external FETs.

From the DC standpoint there is the I-squared R loss,

caused by the on resistance of the FET. This can be mod-

eled for the PMOS by:

P_COND

=DxR

DSON_PMOS

OUT2

and the NMOS by:

N_COND

=(1-D)xR

DSON_NMOS

OUT2

SWITCHING LOSS

The next loss is the switching loss that is caused by the need

to charge and discharge the gate capacitance of the FETs

every cycle. This can be approximated by:

P_SWITCH

g_PMOS

for the PMOS, and the same approach can be adapted for

the NMOS:

N_SWITCH

g_NMOS

TRANSITIONAL LOSS

The last FET power loss is the transitional loss. This is

caused by switching the PMOS while it is conducting current.

This approach only models the PMOS transition, the NMOS

loss is considered negligible because it has minimal drain to

source voltage when it switches due to the conduction of the

body diode. Therefore the transitional loss of the PMOS can

be modeled by:

P_TRANSITIONAL

=0.5xV

OUT

x(t

)

and t

are the rise and fall times of the FET and can be

found in their corresponding datasheet. Typically these num-

bers are simulated using a 6Ωdrive, which corresponds well

to the LM1771. Given this, no adjustment is needed.

DCR LOSS

The last source of power loss in the system that needs to be

calculated is the loss associated with the inductor resistance

(DCR) which can be calculated by:

DCR

OUT2

EFFICIENCY

The efficiency, η, can then be calculated by summing all the

power losses and then using the equation below:

Thermals

By breaking down the individual power loss in each compo-

nent it makes it easy to determine the temperature rise of

each component. Generally the expected temperature rise

of the LM1771 is extremely low as it is not in the power path.

Therefore the only two items of concern are the PMOS and

the NMOS. The power loss in the PMOS is the sum of the

conduction loss and transitional loss, while the NMOS only

has conduction loss. It is assumed that any loss associated

with the body diode conduction during the dead-time is

negligible.

For completeness of design it is important to watch out for

the temperature rise of the inductor. Assuming the inductor is

kept out of saturation the predominant loss will be the DC

copper resistance. At higher frequencies, depending on the

core material, the core loss could approach or exceed the

DCR losses. Consult with the inductor manufacturer for ap-

propriate temp curves based on current.

LM1771

www.national.com13

Layout

The LM1771, like all switching regulators, requires careful

attention to layout to ensure optimal performance. The fol-

lowing steps should be taken to aid in the layout. For more

information refer to Application Note AN-1299.

1. Ensure that the ground connections of the input capaci-

tor, output capacitor and NMOS are as close as pos-

sible. Ideally these should all be grounded together in

close proximity on the component side of the board.

2. Keep the switch node small to minimize EMI without

degrading thermal cooling of the FETs.

3. Locate the feedback resistors close to the IC and keep

the feedback trace as short as possible. Do not run any

feedback traces near the switch node.

4. Keep the gate traces short and keep them away from the

switch node as much as possible.

5. If a small bypass capacitor is used on V

(0.1µF) place

it as close to the pin, with the ground connection as

close to the chip ground as possible.

LM1771

www.national.com 14

Typical Application Circuit

20189043

Example Circuit Schematic

Bill of Materials (5V to 1.8V Conversion, f

= 1090kHz, I

OUT

= 2A)

Designator Description Part Number Quantity Vendor

LM1771, 500ns LM1771S 1 National Semiconductor

PMOS Si3867DV 1 Siliconix

NMOS Si3460DV 1 Siliconix

22µF Capacitor, 0805 GRM21BR60J226ME39 1 Murata

OUT

100µF Capacitor, 6.3V, 100mΩTPSY107M006R0100 1 AVX

FB1

12.4kΩResistor, 0603 CRCW06031242F 1 Vishay

FB2

10kΩResistor, 0603 CRCW06031002F 1 Vishay

1nF Capacitor, 0603 VJ0603102KXXA 1 Vishay

L 3.3µH Inductor MSS7341-332NLB 1 Coilcraft

Bill of Materials (5V to 3.3V Conversion, f

= 500kHz, I

OUT

= 5A)

Designator Description Part Number Quantity Vendor

LM1771, 200ns LM1771U 1 National Semiconductor

PMOS Si9433BDY 1 Siliconix

NMOS Si4894DY 1 Siliconix

100µF Capacitor, 1812 GRM43SR60J107ME20B 1 Murata

OUT

150µF Capacitor, 6.3V, 70mΩNOSD157M006R0070 1 AVX

FB1

29.4kΩResistor, 0805 CRCW08052942F 1 Vishay

FB2

10kΩResistor, 0805 CRCW08051002F 1 Vishay

1nF Capacitor, 0805 VJ0805102KXXA 1 Vishay

L 2.2µH Inductor DO3316P-222 1 Coilcraft

LM1771

www.national.com15

Physical Dimensions inches (millimeters) unless otherwise noted

LLP-6 Package

NS Package Number SDE06A

MSOP-8 Package

NS Package Number MUA08A

LM1771

www.national.com 16

Notes

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances

and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:

www.national.com/quality/green.

Lead free products are RoHS compliant.

National Semiconductor

Americas Customer

Support Center

Email: new.feedback@nsc.com

Tel: 1-800-272-9959

National Semiconductor

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Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

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Fax: 81-3-5639-7507

Email: jpn.feedback@nsc.com

Tel: 81-3-5639-7560

www.national.com

LM1771 Low-Voltage Synchronous Buck Controller with Precision Enable and No External

Compensation

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