CY8CLEDAC02T - Cypress Semiconductor

CY8CLEDAC02

AC-DC Controller for Dimmable

LED Lighting

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-54879 Rev. *B Revised March 29, 2010

Features

■AC offline input range from 80 to 277 VAC

■Up to 25W output power range

■Intelligent wall dimmer detection:

❐Leading edge (R, RL) dimmers

❐Trailing edge (RC, RLC) dimmers

❐No dimmer

■Wide dimming range from 2 to 100%

■Resonant control to achieve high efficiency

(85% without dimmer)

■Meets harmonic requirement with high power factor

(0.7 without dimmer)

■Primary-side sens i ng el i mi na t es op to -i so l at ors

■Tight LED current regulation (typically < + 2.5%)

■Low startup current (typically 10A)

■Low startup time (typically 0.5s with active startup)

■Multiple p r ot ection features:

❐Output overvoltage protection (OOVP)

❐Output short circuit protection (OSCP)

❐Overtemperature protection (OTP)

❐Current-sense resistor short protection (CSSP)

❐Peak current limit protection (PCLP)

❐Single-poi n t fa ul t protection

■Applications:

❐Dimmable offline LED driver

❐Dimmable LED replacement lamps

❐Dimmable LED luminaires

Description

The CY8CLEDAC02 is a high performance offline LED driver,

designed to interface directly with most conventiona l phase cut

based wall dimmers. The device uses proprietary digital control

technology to provide automatic detection of dimmer type

(leading or trailing edge). It automatically generates dimming

signals for LED loads and h as the ability to dim down to 2%. It

modulates LED brightness using a linear dimming scheme and

switches to a PWM based dimming scheme for output current

levels lower than 20% of the full load current. In PWM mode

optimized dimming frequencies in the range of 900 Hz re sult in

zero visible flicker.

At the heart of a CY8CLEDAC02 based system is the chopping

circuit which provides the load necessary to en able correct wall

dimmer operation. It also improves PF when there is no dimmer

on the line.

The devices’ proprietary primary side sensing enables tight LED

current regulation and eliminates the need for secondary

feedback circuitry. No opto-couplers are necessary to meet UL

isolation requirements; enabling flyback conversion with

automatic is ol a ti on.

The CY8CLEDAC02 operates in quasi-resonant mode to

achieve high efficiency. This mode of operation helps minimize

external component count and simplifies EMI design, lowering

the total bill of material cost.

The device’s cycle-by-cycle adaptive digital regulation uses

critical discontinuous conduction mode (CDCM) when driving

LED loads. The control algorithm for cycle-by-cycle regulation

has internal compensation for guaranteed system phase and

gain margins; requiring no external components for loop

compensation.

The CY8CLEDAC02 has full featured circuit protection not

normally available with other primary-side control solutions. The

built-in protection includes output overvoltage protection

(OOVP), output short circuit protection (OSCP), overtemper-

ature protection (OTP), current-sense resistor short protection

(CSSP), and peak current limit protection (PCLP). It also enables

automatic LED brightness adjustment to compensate for temper-

ature drift by simply connecting a NTC resistor to the VT pin.

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 2 of 19

Logic Block Diagram

Figure 1. Simplified Applic ation Diagram

ADC

DAC

ADC-

MUX

VOVP

VVMS

VFB_C

1.7V

0.128V

1.538V

ISHORT_C

IPEAK

DISENSE VPEAK

0~1.8V

1.9V

0.16V

Output

Boost_Out

65K

POR Startup

Reg

16 MHz

POR

VIN_A 0 ~1.8V

2.5K

ISD

(100µA)

adc_mux_sel

VIN_D

Digital Logic

Dimmer Detection

and Dimmer Phase

Measurement

Constant Current

Control

VIN

VSENSE

VCC

BOOST

OUTPUT

ISENSE

GND

ZVin

VOCP

LDO

(3.3V)

AC Input from

Dimmer

NTC

LED

BOOST

VSENSE

VIN

VCC

OUTPUT

ISENSE

GND

CHOPPING CIRCUIT ISOLATED FLYBACK CONVERSION

CONTROLLER

INPUT FILTERING AND RECTIFICATION

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 3 of 19

Contents

Features ............................................................................. 1

Description........................................................................ 1

Logic Block Diagram........................................................ 2

Contents............................................................................ 3

Pin Information................................................................. 4

Functional Description............................ ... .............. ... ..... 5

Overview ..................................................................... 5

Device Startup............................................................. 5

Dimmer Detection........................................................ 6

Dimmer Tracking and Phase Measurement................ 7

Protection Features............................ ... ... .............. ... .. 9

Understanding Primary Feedback............................. 10

Valley Mode Switching.............................................. 11

Electrical Specifications................................................ 12

Absolute Maximum Ratings.............. .. .............. ......... 12

Electrical Characteristics............ .. ... .............................. 13

Typical Application Diagram......................................... 14

Typical Performance Characteristics........................... 15

Performance Information............................................... 16

Ordering Code Definitions............................................. 17

Packaging Information................ .. ............... .. .............. .. 18

Physical Package Dimensions.................................. 18

Document History Page......................... .............. ... ....... 19

Sales, Solutions, and Legal Information...................... 19

Worldwide Sales and Design Support....................... 19

Products.................................................................... 19

PSoC Solutions..... ... .. .............. ... ... .............. ... ... ....... 19

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 4 of 19

Pin Information

Pin No. Name Type Pin Description

1BOOST Output Gate driver for driving the MOSFET switch in the chopping circuit

2 VSENSE Ana log Input Auxiliary voltage sense (used for primary regulation and zero voltage switching)

3 VIN Analog Input Rectified AC line voltage sense, also used for device startup

4 VTAnalog Input Used for temperature compensation and overtemperature protection, also used

as an external shut down pin

5 GND Ground Ground

6 ISENSE Analog Input Primary current sense. Used for cycle-by- cycle peak-current control and limiting

7OUTPUT Output Gate driver for main MOSFET switch

8 VCC Power Input Power supply for control logic and voltage sense for power-on reset circuitry

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 5 of 19

Functional Description

Overview

The digital logic block is the main control block. All the other

blocks are either inputs or outputs for the digital logic block.

The digital logic block receives signals to determine the input

voltage (VIN), output voltage (VSENSE), temperature (VT), and

output current (ISENSE). It has three output controls; DISENSE

(current control), Output (flyback MOSFET gate drive control),

and Boost_Out (chopper MOSFET gate drive control).

The bias winding of the transformer provides voltage feedback

to the controller for regulation and safety features. The external

voltage sense resistors (not shown) determine the feedback

signal to the VSENSE pin of the controller. The VSENSE pin

connects to circuitry composed of three comparators: VOVP

(output overvoltage protection), VVMS (voltage valley mode

switch), and VFB_C (voltage feedback from coil). When the

VSENSE voltage exceeds VSENSE(MAX) (1.7V) the control block

detects an overvoltage condition, it will enter a shutdown mode

and wait for POR to re-initialize the system. VVMS is monitored

by the control block to determine when the power in the flyback

MOSFET is at a minimum or in a 'valley'. When the VSENSE

voltage goes below the 0.128V threshold the control block starts

monitoring valleys and will start the next cycle at th e 'valley' for

maximum efficiency and minimum switching EMI. For normal

operation, the VSENSE voltage should be set below VSENSE(NOM)

(1.538V). When the VSENSE voltage exceeds VSENSE(NOM) the

controller senses an outp ut overvoltage and tries to maintain a

constant output voltage. This is an intermediate mode where the

controller starts reacting to a problem with the output voltage.

However, an OVP fault will only trigger if VSENSE voltage

exceeds VSENSE(MAX).

The ISENSE pin connects to circuitry composed of three compar-

ators: IPEAK, VOCP, and ISHORT_C. These three blocks work

together for soft start control and peak current detection,

overcurrent protection, and sense resistor short protection

respectively. The DAC VPEAK controls soft start; minimizing

stress associated with system startup. The IPEAK comparator

monitors the voltage at the ISENSE pin. The voltage is generated

by current flowing through a small external resistor (RISENSE -

not shown). When the ISENSE voltage reaches VREG-TH (1.8V),

the IPEAK comparator asserts a high to the control block. The

control block will shut off the output and wait for VVMS detection;

then start the next cycle. The VOCP comparator provides primary

side overcurrent protection. When the voltage on ISENSE reaches

VPEAK (1.9V), the VOCP signal gets asserted. When overcurrent

is detected, the control block will enter a shutdown mode and

reset the system. When the ISENSE voltage reaches VRSNS

(0.16V), a sense resistor short circuit fault is detected and the

control block will enter a shutdown mode and reset all the digital

logic.

The Output signal connects to the gate driver block for the

OUTPUT pin that, in turn, connects to the flyback MOSFET gate

pin (not shown). The OUTPUT pin is a digital control pin that

switches between high level (approximatel y VCC) and low level

(approximately ground). The duration for high (tON) and low

(tOFF) of the Gate Driver is a function of the control block

operating upon its inputs: VINtON, VFB, VVMS, VT, IPEAK, VOCP,

and VCC.

The Boost_Out signal connects to the gate driver block for the

BOOST pin that, in turn, connects to the chopper MOSFET gate

pin (not shown). The BOOST pin is again a digital control pin that

switches between h igh level (appro ximately VCC) and low level

(approximately ground). The BOOST pin timing is internally

controlled and depends on the mode of operation for the IC (that

is, no dimmer, trailing edge dimmer, or leading edge dimmer

mode).

The VT pin connects to a current source (ISD), generated by an

internal LDO, and an analog to digital converter . This pin can be

used for OTP along with au tomatic LED brightness adjustment

to compensate for temperature drift. This can be achieved by

simply connecting the VT pin to an external NTC component (not

shown). The current source causes a voltage to develop at the

VT pin which is sampled once every AC half cycle by the ADC. If

the voltage is between 0.5 to 2V , the controller operates normally.

For a voltage range 0.5V to 0.3V, the LED intensity is linearly

dimmed. At 0.3V the LEDs are dimmed to 10%. From 0.3V to

0.1V, the LED intensity stays at 10% and below 0.1V (VSH-TH),

the controller will trigger a fault, enter shutdown mode, and reset

all the digital logic.

Device Startup

Before startup, VIN charges up the VCC capacitor through the

internal diode between VIN and VCC (see “Logic Block Diagram”

on page 2). When the voltage at VCC rises above the startup

threshold VCCST, the control logic is enabled.

In the first four AC half cycles after startup, the BOOST pin is held

high (see Figure 2 on page 6). During these half cycles the

dimmer type is detected and the AC line period is measured.

Following this, the controller enters an intermediate state and

waits for the output voltage to ramp up. When the output voltage

is higher than the forward voltage for the LED string, the

controller enters constant current mode.

An adaptive soft start control algorithm is applied at startup,

during which the initial output pulses are small and gradually get

larger until the full pulse width is achieved. The peak curren t is

limited cycle-by-cycle by IPEAK comparator.

If at any time the V CC voltage drops below the VCCUVL threshold,

all the digital logic is reset. At this time the internal VIN switch

turns off allowing the VCC capacitor to charge for a fresh startup.

If a faster startup is required, then an external active startup

scheme can be used. Components R10, R1 1, Q3, and D5 enable

active startup as i llustrated in the “Typical Application Diagram”

on page 14. Q3 , a depleti on type MOSFET, is initially on before

startup. The VCC capacitor C8 charges a lot quicker as the

resistors R10 and R11 can be made much smaller than R3 and

R4 lowering the overall charging resistance. When VCC rises

above VCCST, the interna l control logic gets enabled pulling the

VIN node low. The gate to source voltage across Q3 becomes

negative, thus turning Q3 off. This technique substantially

reduces startup time.

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 6 of 19

Figure 2. Device Startup Sequencing

Dimmer Detection

Intelligent Wall Dimmer detection includes automatically

detecting presence or absence of a dimmer and, if present,

detecting the dimmer type (leading or trailing edge ).

Dimmer detection or discovery takes place during the first four

AC half cycles after startup. During this phase the BOOST pin

remains high, placing a purely resistive load across the dimmer .

As wall dimmers are designed to work with resi stive loads such

as an incandescent lamp, loading the dimmer with a purely

resistive load enables accurate dimmer detection.

The operation is broken into two stages. In the first stage, the

controller simply determines whether a dimmer is present. If a

dimmer is not detected, the dimmer type is set to 'no dimmer'. If

a dimmer is detected, then in the next stage the dimmer type

(leading or trailing edge) is determined.

The presence or absence of a dimmer is determined by

monitoring how long the VIN voltage stays below a zero-cross

detect (ZCD) threshold. This threshold is determined by the

controller using the peak of line and half line period measure-

ments. An internal digital signal, VCROSS, is generated which

tracks the VIN signal and determines the duration (tPERIOD –

tCROSS) for which VIN is below the ZCD threshold (see Fig ure 4

on page 7). This detection scheme is based on the fact that VIN

will remain below the ZCD threshold for a much lo nger d uration

in a single AC half cycle when a dimmer is present. In most cases

VIN is below the ZCD threshold for longer due to phase cut on

the line. In cases when the dimmer does not exhibit any phase

cut (at maximum setting) the duration is longer due to delays

associated with dimmer operation .

If a dimmer is detected, then the VIN pin voltage is filtered and

differentiated to identify the largest positive and negative slopes

in the AC half cycle. If the positive (rising) slope is greater than

1.5 times the negative (falling) slope, then a leading edge

dimmer must be present. If not, a trailin g edge dimmer must be

present.

Figure 3. AC Line Waveforms with Leading Edge (left) and Trailing Edge (right) Dimmers

AC line before Wall-

dimmer

Dimmed AC line after

Wall-dimmer

Dimmed AC line after

Wall-dimmer

AC line before Wall-

dimmer

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 7 of 19

Figure 4. Dimmer Detection

Dimmer Tracking and Phase Measurement

Dimmer detection and tracking algorithms depend on accurate

measurement of the V IN period. The period is measured during

the second cycle of the dimmer discovery process and is then

latched for use. Using the measured VIN period in subsequent

calculations rather tha n a constant value enables automatic 50

or 60 Hz operation.

The phase measurement algorithm uses an internal counter that

starts counting when the rising threshold on VIN is exceeded and

counts input voltage samples until the voltage is above the

threshold. The counter is synchronized with the measured VIN

period and is restarted on every rising threshold (as shown in

Figure 5).

The dimmer phase is calculated as:

Equation 1

The calculated DPHASE is then used to generate a signal DRATIO.

When DPHASE is less than 0.2, DRATIO is set to 0.02 and w hen

DPHASE is greater than 0.8, DRATIO is set to 1.0. For all other

cases DRATIO is set using the following equation:

Equation 2

where K1 and K2 are constants with values 1.63 and 0.3 respec-

tively.

The output power to the LED load is modulated by DRATIO. When

DRATIO is 1, 100% power is provided to the LED load, and when

DRATIO of 0.1, 10% power is provided to the LED load.

The voltage at the ISENSE pin VISENSE, which modulates the

output LED current can be set at a nominal value and modulated

using the following equation:

Equation 3

This equation provides a mapping from the measured dimmer

phase to actual light output.

Figure 5. Dimmer Tracking and Phase Measurement

BOOST

VCROSS

VIN

tCROSS

tPERIOD

LED_EN

VLED

ZCD Threshold

PERIOD

CROSS

PHASE tt

D

21 KKDD PHASERATIO





RATIO

NOMSENSE

IISENSE DVV





)(

VCROSS tCROSS

tPERIOD

VINA

ZCD Threshold

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 8 of 19

Chopping Operation

The chopping circuit provides four key functions:

■At startup, it provides a low impedance load on the wall dimmer

enabling the type of dimmer (none, leading edge, or trailing

edge) to be determined.

■Each cycle intelligently provides a low impedance load to:

❐Enable accurate determination of mains zero crossing points.

❐Meet triac trigger current and latch current requirements for

triac based (leading edge) dimmers.

■Improves Power Factor

■Minimizes mains cycle peak current for triac based (leading

edge) dimmers by boosting energy into the bulk capacitor.

The chopping circuit is shown in Figure 7. When Q3 is driven with

short on pulses, the circuit operates as a boost converter. When

Q3 turns on, the chopping inductor L3 stores energy. When Q3

turns off, this energy is released t o capacitor C3 through diode

D3. Source resistor R6 is used to limit the current in the chopper

path to optimize the efficiency of the circuit. A dithering algorithm

is used to co ntrol the period for Q3 to mini mize EMI generated

by the mainly discontinuous operation of the boost circuit. The

voltage on ZVIN i s the scaled rectified mains voltage, a voltage

only available internal to the device.

During the chopping period, the average current in L3 is in phase

with and proportional to the input mains voltage inherently gener-

ating high power factor.

If the circuit determines it i s connected to a dimmer, Q3 is held

on while the mains voltage in is low . This provides a load on the

dimmer enabling the internal circuitry of the dimmer to reset

correctly for each half cycle. For leading edge dimmers, Q3 is

held on for a significant time after the triac in the dimmer fires

each half cycle. During this period L3 will saturate and R6

provides the current necessary for the triac latch current to be

reached. For trailing edge dimmers, Q3 is held high after the

trailing edge. This load forces the line to quickly fall to zero when

the dimmer turns off, enabling accurate detection of the dimmer

on time.

D8 and D9 ensure C3 is charged to peak voltage output from the

dimmer. This maximizes the voltage on C3 each half cycle,

minimizing the in rush current when the triac fires on the next half

cycle.

The chopper operates in th ree different modes as follows:

■No dimmer: Chopper operates when the internal voltage at ZVIN

is above a pre-defined chopping threshold. The chopper

remains off otherwise.(see Figure 6)

■Leading edge dimmer mode: The chopping period is defined

as the percentage of the dimming period (TCROSS). The

chopper FET remains hard on during the zero crossing section

on VIN.(see Figure 8)

■T railing edge dimmer mode: Chopping circuit is active across

the entire dimming period (TCROSS). The chopper FET remains

hard on otherwise (see Figure 9).

Figure 6. Chopping Operation (No Dimmer Mode)

Figure 7. Chopper Circuit

R3 + R4

D1 L3

ZVIN

WALL

DIMMER

C1 AC

BOOST (pin)

VIN (pin)

(Internal)

BR1

VCBULK

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 9 of 19

Figure 8. Chopper Operation (Leading Edge Dimmer Mode)

Figure 9. Chopper Operation (Trailing Edge Dimmer Mode)

Protection Features

The CY8CLEDAC02 has full featured circuit protection not

normally available with other primary-side control solutions.

The built-in protection features include output overvoltage

protection (O OVP), o utput short circu it prot ection (OSC P), peak

current limit protection (PCLP), current-sense resistor short

protection (CSSP), and ove rtemperature protection (OTP).

In an event a protection is tr iggered (except PCLP and OOVP),

VCC discharges below VCCUVL and causes the digital logic to

reset. The controller now initiates a new soft start cycle and

continues to attempt start-up. It is unable to start-up until the fault

condition is removed. PCLP does not trigger a shutdown. In case

of OOVP the IC stays latched and cannot perform a reset unless

the VCC voltage drops approximately 1-2V below VCCUVL

threshold.

Output Overvoltage Protection (OOVP)

The CY8CLEDAC02 includes a function that protects against an

output overvoltage. The output voltage is monitored by the

VSENSE pin. The protection is t riggered if the voltage at th is pin

exceeds the overvoltage threshold VSENSE(MAX).

Output Short Circuit Protection (OSCP)

The CY8CLEDAC02 includes a function that protects against an

output short circuit. The output voltage is monitored by the

VSENSE pin. The protection is tr iggered if the voltage at th is pin

is below 0.22V.

Overtemperature Protection (OTP)

The VT pin along with an external NTC provides overtemperature

protection. Having an internal current source to the pin allows for

sensing the voltage across the NTC. The voltage across the pin

is sampled once every AC half cycle and the protection mode is

triggered if it reaches the VT shutdown threshold (VSDTH).

Current Sense Resistor Short Protection (CSSP)

If the ISENSE sense resistor is shorted, there is a potential danger

of an overcurrent condition not being detected. The

CY8CLEDAC02 has a separate circuit to detect this fault. This

protection mode is triggered if the ISENSE voltage is below ISENSE

short protection re ference (VRSNS).

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 10 of 19

Peak Current Limit protection (P CL P)

The ISENSE pin of the CY8CLEDAC02 monitors the primary peak

current. This enables cycle-by-cycle peak current control and

limiting. When the ISENSE voltage is greater than the overcurrent

limit threshold VOCP, an overcurrent condition is detected and the

IC immediately turns off the MOSFET driver. During the next

switching cycle, the driver sends out a regular switching pulse

and turns off again if the OCP t hreshold is still reach ed. Normal

switching resumes if the fault is removed and the OCP threshold

is not reached.

Single Point Fault Protection

The CY8CLEDAC02 can detect a short on an y of the following

pins VIN, ISENSE, VSENSE, VCC, OUTPUT, and VT. Therefore any

single point fault is p rot ec te d ag a i nst .

Understanding Prima ry Feedback

Figure 10 illustrates a simplified flyback converter. When the

switch Q1 conducts during tON(t), the current ig(t) is directly

drawn from rectified sinu soid vg(t). Th e energy Eg(t) is stored in

the magnetizing inductance LP. The rectifying diode D1 is

reverse biased and the load current IO is supplied by the

secondary capacitor CO. When Q1 turns off, D1 conducts and

the stored energy Eg(t) is delivered to the output.

Figure 10. Simplified Flyback Converter

To tightly regulate output current, information about the load

current needs to be accurately sensed. To achieve CC

regulation, this i nformation ca n be derived indi rectly by sens ing

the primary current.

To detect faults with output voltage, information about the output

voltage and load current need s to be accurately sensed. In t he

DCM flyback converter , this information can be read through the

auxiliary winding.

During the Q1 on time, the load current is supplied from the

output filter capacitor CO. The voltage across LP is vg(t),

assuming the voltage dropped across Q1 is zero. The current in

Q1 ramps up linearly at a rate of:

Equation 4

At the end of on time, the current has ramped up to:

Equation 5

This current represents a stored energy of:

Equation 6

When Q1 turns off, ig(t) in LP forces a reversal of polarities on all

windings. Ignoring the commutation time caused by the leakage

inductance LKP at the instant of turn-off, the primary current

transfers to the secondary at a peak amplitude of:

Equation 7

Assuming the secondary winding is master and the auxiliary

winding is slave, the auxiliary voltage is given by:

Equation 8

and reflects the output voltage as shown in Figure 11.

vin(t) AC

iin(t)

vg(t)

ig(t) id(t)

Ts(t) Q1

LAUX

NAUX

gg L

tdi )()( 

ONg

peakg L

ttv



)(

)(

_)(

Epeakg

g

)()( _ti

ti peakg

d

)V(  O

AUX

AUX V

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 11 of 19

Figure 11. Auxiliary Voltage Wave forms

The voltage at the lo ad differs from the secondary voltage by a

diode drop and IR losses. The diode drop is a function of current,

as are IR losses. Thus, if the secondary voltage is always read

at a constant secondary current, the difference between the

output voltage and the secondary voltage is a fixed V. Further ,

if the voltage can be read when the secon dary current is small;

for example, at the knee of the auxiliary waveform (see

Figure 11), then V is also small. With the CY8CLEDAC02, V

can be ignored.

The real time waveform analyzer in the CY8CLEDAC02 reads

the auxiliary waveform information cycle by cycle. The part then

generates a feedback voltage VFB_C. The VFB_C signal precisely

represents the output voltage and is used to sense the output

voltage.

Valley Mode Switching

To reduce EMI and switching losses in the MOSFET, the

CY8CLEDAC02 employs valle y mode switchi ng by swi tchi ng at

the lowest MOSFET VDS (see Figure 12). It detects valleys in the

MOSFET drain voltage indirectly through the VSENSE pin. This

voltage is provided by the auxi liary wi ndin g of t he fl yback tra ns-

former and represents a copy of the secondary side character-

istics (see Figure 11).

Figure 12. Valley Mode Switching

T urning on at the lowest VDS generates lowest dV/dt; thus valley

mode switching can also reduce EMI. To limit the switching

frequency range, the CY8CLEDAC02 can skip valleys (as shown

in the first cycle in Figure 12) when the switching frequency

becomes too high.

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 12 of 19

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8CLEDAC02. For the most up to date electrical specifications,

confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/powerpsoc. Specifications are valid

for -40°C  TA  85°C and TJ  125°C, except where noted. Table 1 lists the units of measure that are used in this section.

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. Not all user guidelines are production tested

Table 1. Unit s of Measure

Symbol Unit of Measure Symbol Unit of Measure Symbol Unit of Measure

°C degrees Celsius Kbit 1024 bits mA milliampere

dB decibels KHz kilohertz ms millisecond

Hz Hertz Kkilohms mV millivolts

pp peak-to-peak MHz megahertz mA milliwatts

sigma:one standard deviation Mmegaohms nA nanoamperes

Vvolts Amicroamperes ns nanoseconds

ohms Fmicrofarads nV nanovolts

KB 1024 bytes Hmicrohenrys pA picoamperes

ppm parts per million smicroseconds pF picofarads

sps samples per second Vmicrovolts ps picoseconds

Wwatts Vrms microvolts root-mean-square fF femtofarads

Aamperes Wmicrowatts

Symbol Description Min Typ Max Units Notes

VCC DC Supply Voltage Range -0.3 -18 VPin 8, ICC = 20 mA max

ICC DC Supply Current at VCC Pin - - 20 mA Pin 8

VOUT OUTPUT Pin Voltage -0.3 -18 VPin 7

VBOOST BOOST Pin Voltage -0.3 -18 VPin 1

VVSENSE VSENSE Pin Voltage -0.7 - 4 V Pin 2, IVSENSE < 10mA

VVIN VIN Pin Voltage -0.3 -18 VPin 3

VISENSE ISENSE Pin Voltage -0.3 - 4 V Pin 6

VVT VT Pin Voltage -0.3 - 4 V Pin 4

PDPower Dissipation - - 526 mW TA < 25°C

TJ MAX Maximum Junction Temperature - - 125 °C

TSTG Storage Temperature -65 -150 °C

TLEAD Lead Temperature - - 260 °C During IR reflow for < 15

seconds

JB[1] Thermal Resistance Junction-to-PCB

board surface - - 70 °C/W

VESD ESD Voltage Rating - - 2000 VAccording to JEDEC

JESD22-A114

ILU Latch Up Current -100 -100 mA According to JEDEC JESD78

Note

1. JB provides an estimation of the die temperature relative to the Printed circuit board (PCB) surface temperature. This data is measured at the ground pin (pin 5)

without using any thermal adhesives.

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 13 of 19

Electrical Characteristics

Notes

2. Adjust VCC above start-up threshold before setting at 12V.

3. These parameters are not 100% tested, guaranteed by design and characterization.

4. Operating frequency varies based on line and load conditions.

VCC=12V; -40°C  TA  85°C unless otherwise specified[2]

Symbol Description Min Typ Max Units Notes

VIN Section (pin 3)

VIN Input V oltage Range 0 - 1.8 V During normal operation (after startup)

IINST Startup Current - 10 15 AV

IN = 10V, CVCC = 10F

ZVIN Input Impedance - 2.5 - kDuring normal operation (after startup)

VSENSE Section (pin 2)

IBVS Input Leakage Current - - 1 AV

SENSE = 2V

VSENSENOM Nominal Voltage Threshold 1.523 1.538 1.553 V TA = 25°C, Negative edge

VSENSEMAX Output OVP Threshold 1.683 1.700 1.717 V TA = 25°C, Negative edge

OUTPUT Section (pin 7)

RDS(ON)LO Output Low Level ON-Resistance - 30 - ISINK = 5 mA

RDS(ON)HI Output High Level ON-Resistance - 60 - ISOURCE = 5 mA

tR[3] Rise Time (10% to 90%) - 50 - ns TA = 25 °C , CL = 330pF

tF[3] Fall Time (90% to 10%) - 30 - ns TA = 25°C, CL = 330pF

fSWMAX[4] Maximum Switching Frequency - 200 - kHz

VCC Section (pin 8)

VCCMAX Maximum Operating Volt age - - 16 V

VCCST Startup Threshold 11 12 13 V VCC Rising

VCCUVL Undervoltage Lockout Threshold 7.0 7.5 8.0 V VCC Falling

ICC Operating Current - 3.9 4.5 mA CL = 330pF, VSENSE = 1.5V

VCC-CLAMP Zener Diode Clamp Voltage - 19 - V Test current of 10 mA

ISENSE Section (pin 6)

VOCP Overcurrent Threshold Limit - 1.9 - V

VRSNS ISENSE Short Protection Reference - 0.16 - V

VREGTH CC Regulation Threshold Limit - 1.8 - V

VT Section (pin 4)

VSDTH Shutdown Threshold - 0.09 - V

IBVSD Input Leakage Current - - 1.0 AV

SD = 1.0V

ISD Pull up Current Source 95 100 105 A

BOOST Section (pin 1)

RDS(ON)LO-TR Output Low Level ON-Resistance - 100 - ISINK = 5 mA

RDS(ON)HI-TR Output High Level ON-Resistance - 200 - ISOURCE = 5 mA

tR-BST[3] Rise Time - 60 - ns

tF-BST[3] Fall Time - 60 - ns

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 14 of 19

Typical Application Diagram

D1 L3

C4 R11

R12

R15

C10 R22

AC Input

R27NTC

LED

R10

R13

R14

R20

R21

R19

Z1 VSEN

CY1

VSEN

C15

R28

D10 R23

Q4 R24

C13

R25

BST

BR1

R29

BOOST

VSENSE

VIN

VCC

OUTPUT

ISENSE

GND

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 15 of 19

Typical Performance Characteristics

Figure 13. VCC vs. VCC supply start-up current

Figure 14. VCC startup threshold vs. temperature

Figure 15. % Deviation of switching frequency to ideal

switching frequenc y with temperature

Figure 16. Internal re ference voltage vs. temperature

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 16 of 19

Performance Information

Figure 17. Inrush and AC Peak Current (Trailing Edge)

Figure 18. Inrush and AC Peak Current (Trailing Edge)

Figure 19. Inrush and AC Pe ak Current (Leading Edge)

Figure 20. Inrush and AC Peak Curre nt (Leading Edge)

Figure 21. Inrush and AC Peak Current (No Dimmer)

Figure 22. Dimming Curve

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 17 of 19

Ordering Information

Ordering Code Definitions

Ordering Code No. of Pins Package Temperature Range

CY8CLEDAC02 8 SOIC -40°C to 85°C

CY 8 C LED AC 02

02 = Dimmable

AC = Offline

Family Code: LED = LED Applicat ion s

Technology Code: C = CMOS

Marketing Code: 8 = PowerPSoC® Family

Company ID: CY = Cypress

CY8CLEDAC02

Document Number: 001-54879 Rev. *B Page 18 of 19

Packaging Information

Physical Package Dimensions Figure 14. 8-Pin Small Outline (SOIC) Package

001-54263 *A

SEATING PLANE

0.228[5.792]

0.244[6.197]

0.157[3.987]

0.150[3.810]

0.189[4.800]

0.197[5.004]

0.050[1.270]

BSC

0.051[1.295]

0.067[1.702]

0.002[0.050]

0.006[0.152]

0.014[0.356]

0.019[0.483]

0.016[0.406]

0.050[1.270]

0.007[0.178]

0.010[0.254]

1. DIMENSIONS IN INCHES[MM]

0°~8°

0.004[0.102]

2. REFERENCE JEDEC MS-012F

0.094[2.388]

0.086[2.184]

0.126[3.200]

0.118[2.997]

TOP VIEW BOTTOM VIEW

exposed

pad

3. PACKAGE WEIGHT 0.07 gm

Document Number: 001-54879 Rev. *B Revised March 29, 2010 Page 19 of 19

PSoC® and PowerPSoC® are registered trademarks and PSoC Designer™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are

property of the respective corp orations.

CY8CLEDAC02

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress produ cts in life-supp ort systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conjuncti on with a Cypress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

the express written perm ission of Cypres s.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cyp ress does not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Sales, Solutions, and Legal Information

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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

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PSoC 1 | PSoC 3 | PSoC 5

Document Title: CY8CLEDAC02 AC-DC Controller for Dimmable LED Lighting

Document Number: 001-54879

Revision ECN Orig. of

Change Submission

Date Description of Change

** 2746461 KJV 07/30/09 Preliminary data sheet

*A 2882776 KJV/AESA 02/22/2010 Updated Features, Description, and Functional Description sections.

Updated Electrical Specifications.

Updated package diagram.

Added Contents.

Updated links in Sales, Solutions, and Legal Information.

*B 2901104 KJV/VED 03/29/2010 Release to web