FEDR26V01G53L-002-01
Issue Date: Oct. 01, 2008
MR26V01G53L
64M–Word × 16–Bit or 12 8M–Word × 8–Bit Pag e Mode P2ROM
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FEATURES PIN CONFIGURATION (TOP VIEW)
· 64M-word × 16-bit / 128M-word × 8-bit electrically
switchable configuration
· Page size of 8-word x 16-Bit or 16-word x 8-Bit A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A23
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
BYTE#
A0
D0
D8
D1
D9
Vcc
D2
D10
D3
D11
GND
CE#
A12
A13
A14
A15
Vcc
A16
A17
A18
A19
A20
A21
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
A22
A24
OE#2
OE#1
D15/A-1
D7
D14
D6
D13
D5
D12
D4
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
· 3.0 V to 3.6 V power supply
· Random Access time 105 ns MAX
· Page Access time 35 ns MAX
· Operating current 100 mA MAX
· Standby current 10 mA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR26V01G53L-xxxMB
70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC) 70SSOP
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added ben efits over
the other non-volatile technologies, which include the
following;
· Short l ead time , since the P2ROM is programmed at the fi nal
stage of the production process, a large P2ROM inventory
"bank system" of un-programmed packaged products are
maintained to provide an aggressive lead-time and minimize
liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and OTP
that require additional programming and handling costs, the
P2ROM already has the code loaded at the factory with
minimal effect on the production throughput. The cost is
included in the unit price.
· Custom Marki ng i s available at no additional charge
FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
BLOCK DIAGRAM
A
0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
CE# BYTE#
OE#1
CE OE1
× 8 / × 16 Switch
D0 D2 D4 D6 D8 D10 D12 D14
D1 D3 D5 D7 D9 D11 D13 D15
Memory Cell Matr ix
64M × 16-Bit or 128M × 8-Bit
Multiplexer
Output Buffer
Row Decoder
Column Decoder
Address Buffer
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
A–1
OE#2
OE2
PIN DESCRIPTIONS
Pin name Functions
D15 / A–1 Data output / Address input
A0 to A24 Address inputs
D0 to D14 Data outputs
CE# Chip enable input
OE#1 OE#2 Output enable input
BYTE# Word / Byte select input
VCC Power supply voltage
VSS Ground
NC No connect
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
FUNCTION TABLE (Vcc=3.0V~3.6V)
Mode Address CE# OE#1 OE#2 BYTE# D0 to D7 D8 to D14 D15/A–1
0000000-1FFFFFF L H DOUT(MSB=0)
Read (16-Bit) 2000000-3FFFFFF L H L H DOUT(MSB=1)
0000000-3FFFFFF L H
Read (8-Bit) 4000000-7FFFFFF L H L L DOUT Hi–Z L/H
H
Output disable ∗ L H H L
Hi–Z ∗
H
Standby ∗ H ∗ ∗ L
Hi–Z ∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Value Unit
Operating temperature under bias Ta 0 to 70 °C
Storage temperature T stg — –55 to 125 °C
Input voltage VI –0.5 to VCC+0.5 V
Output voltage VO –0.5 to VCC+0.5 V
Power supply voltage VCC Relative to VSS –0.5 to 5 V
Power dissipation per package PD Ta = 25°C 1.0 W
Output short circuit current IOS — 10 mA
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter Symbol Condition Min. Typ. Max. Unit
VCC power supply voltage VCC 3.0 — 3.6 V
Input “H” level VIH 2.2 — VCC+0.5∗ V
Input “L” level VIL VCC = 3.0 to 3.6 V –0.5∗∗ — 0.6 V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
(VCC = 3.3 V, Ta = 25°C, f = 1 MHz)
Parameter Symbol Condition Min. Typ. Max. Unit
Input CIN1 — — 15
BYTE# CIN2 VI = 0 V — — 400
Output COUT V
O = 0 V — — 15 pF
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
Parameter Symbol Condition Min. Typ. Max. Unit
Input leakage current ILI V
I = 0 to VCC — — 10 μA
Output leakage current ILO V
O = 0 to VCC — — 10 μA
ICCSC CE# = VCC — — 10 mA VCC power supply current
(Standby) ICCST CE# = VIH — — 10 mA
VCC power supply current
(Read) ICCA1 CE# = VIL, OE# = VIH
f=5MHz — — 100 mA
Input “H” level VIH — 2.2 —
VCC+0.5
∗ V
Input “L” level VIL — –0.5∗∗ — 0.6 V
Output “H” level VOH I
OH = –1 mA 2.4 — — V
Output “L” level VOL I
OL = 2 mA — — 0.4 V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
Parameter Symbol Condition Min. Max. Unit
Address cycle tim e tC — 105 — ns
Address access time tACC CE# = VIL
OE1# or OE2#= VIL — 105 ns
Page cycle time tPC — 35 — ns
Page access time tPAC CE# = VIL
OE1# or OE2#= VIL — 35 ns
CE# access time tCE OE1# or OE2#= VIL — 105 ns
OE# access time tOE CE# = VIL — 30 ns
OE# delay time tOES — 0 — ns
tCHZ OE1# or OE2#= VIL 0 20 ns
Output disable time tOHZ CE# = VIL 0 20 ns
Output hold time tOH CE# = VIL
OE1# or OE2#= VIL 0 — ns
Measurement conditions
Input signal level ---------------------------------- 0 V/3 V
Input timing r eference level --------------------- 1/2Vcc
Output load----------------------------------------- 50 pF
Output timing reference level ------------------- 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
Address
CE#
OE#1or OE#2
Dout
tC
tCE
tOE
tOH
tCHZ
Valid Data
Hi-Z Hi-Z
tOH
t
A
CC
Valid Data
t
A
CC
tC
Page Access Mode Read Cycle
A3 to A24
tC
tCE
tOE
t
A
CC
tOH
tCHZ
tOHZ
Hi-Z Hi-Z
Dout Valid Data
TOES tPAC
Valid Data
A-1 to A2 (Byte mode)
Valid Data
tPC tPC
tPAC
A0 to A2 (Word mode)
CE#
OE#1 or OE#2
OE#2or OE#1 TOES tOHZ
OE#2 or OE#1
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting , contact ROHM’s respon s ibl e sale s pers on for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
REVISION HISTORY
Page
Document
No. Date Previous
Edition Current
Edition
Description
FEDR26V01G53 L-02-0 1 Jul. 29, 200 5 – – Final edition 1
FEDR26V01G53L-002-01 Oct. 1, 2008 – – Changed company logo and name
to OKI SEMICONDUCTOR
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FEDR26V01G53L-002-01
MR26V01G53L/ P2ROM
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