2015 Microchip Technology Inc. DS20005418B-page 1
HV5122 / HV5222
Features
Processed with High Voltage CMOS technology
Output voltages to 225V using a ramped supply
voltage
SINK current minimum 100mA
Shift register speed 8.0MHz
Strobe and enable inputs
CMOS compatible inputs
Forward and reverse shifting options
Description
HV5122 / HV5222 are low-voltage serial to high-volt-
age parallel converters with open-drain outputs. These
devices are primarily designed for use as a driver for
AC electroluminescent displays. HV5122 / HV5222 can
also be used in any application requiring multiple high-
voltage, current-sinking output capabilities such as
driving inkjet and electrostatic print heads, plasma pan-
els, vacuum fluorescent, or large matrix LCD displays.
These devices consist of a 32-bit shift register and con-
trol logic to perform the Output Enable and all-on func-
tions. Data is shifted through the shift register on the
high-to-low transition of the clock. HV5122 shifts in the
counter-clockwise direction when viewed from the top
of the package and HV5222 shifts in the clockwise
direction.
For cascading devices, HV5122 / HV5222 provides a
data output buffer that reflects he current status of the
last bit of the shift register. Operation of the shift regis-
ter is not affected by the OE (Output Enable) or the
STR (Strobe) inputs.
HV5122 / HV5222 are designed to be used in systems
which either switch off the high voltage supply before
changing the state of the high voltage outputs or which
limit the current through each output.
32-Channel, Serial-to-Parallel Converter
with Open-Drain Outputs
HV5122 / HV5222
DS20005418B-page 2 2015 Microchip Technology Inc.
Package Type
Functional Block Diagram
44-Lead PLCC
See Table 2-1 for pin information
44-Lead PQFP
1
44
144
640
HV
OUT
2
28 Additional
Outputs
HV
OUT
31
OE
DATA
INPUT
CLK
Data Out
STR
HV
OUT
1
HV
OUT
32
32 bit
Static Shift
Register
2015 Microchip Technology Inc. DS20005418B-page 3
HV5122 / HV5222
1.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD ...................................................................................................................................-0.5V to +15V
Supply voltage, VPP .................................................................................................................................-0.5V to +250V
Logic input levels ............................................................................................................................... -0.5V to VDD+0.5V
Ground current1....................................................................................................................................................... 1.5A
Continuous total power dissipation2.................................................................................................................. 1200mW
Operating temperature range.................................................................................................................. -40°C to +85°C
Storage temperature range ................................................................................................................... -65°C to +150°C
1: Duty cycle is limited by the total power dissipated in the package.
2: For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C.
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 1-1: ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over recommended conditions unless otherwise specified
Symbol Parameter Min Max Units Conditions
DC Characteristics
IDD VDD supply current - 15 mA fCLK= 8.0MHz, fDATA= 4.0MHz
IDDQ
Quiescent VDD supply current - 100 µA DIN= 0V, all input logic pins = 0V,
all outputs off
IO(OFF) Off-state output current - 10 µA All outputs high, all switches parallel
IIH High level logic input current - 1.0 µA VIN= VDD
IIL Low level logic input current - -1.0 µA VIL= 0
VOH
High level output data out VDD -
1.0V -V
IDOUT= -100µA
VOL Low level output voltage HVOUT -15
VIHVOUT= +100mA
Data out - 1.0 IDOUT= +100µA
VOC HVOUT clamp voltage - -1.5 V IOL= -100mA
AC Characteristics (VDD = 12V, TA=25°C)
fCLK Clock frequency - 8.0 MHz
tWClock width, high or low 62 - ns
tSU Data setup time before CLK falls 25 - ns
tHData hold time after CLK falls 10 - ns
tON Turn-on time, HVOUT from strobe - 500 ns RL= 2.0k to 200V
tDHL Data output delay after H to L CLK - 100 ns CL= 15pF
tDLH Data output delay after L to H CLK - 100 ns CL= 15pF
TABLE 1-2: TYPICAL THERMAL RESISTANCE
Package θja
44-Lead PQFP 51°C/W
44-Lead PLCC 37°C/W
HV5122 / HV5222
DS20005418B-page 4 2015 Microchip Technology Inc.
2.0 PIN DESCRIPTION
The locations of the pins are listed in Package Type.
TABLE 2-1: PIN DESCRIPTION PQFP
Pin # HV5122 HV5222 Description
1HV
OUT11 HVOUT22
High voltage outputs.
2HV
OUT12 HVOUT21
3HV
OUT13 HVOUT20
4HV
OUT14 HVOUT19
5HV
OUT15 HVOUT18
6HV
OUT16 HVOUT17
7HV
OUT17 HVOUT16
8HV
OUT18 HVOUT15
9HV
OUT19 HVOUT14
10 HVOUT20 HVOUT13
11 HVOUT21 HVOUT12
12 HVOUT22 HVOUT11
13 HVOUT23 HVOUT10
14 HVOUT24 HVOUT9
15 HVOUT25 HVOUT8
16 HVOUT26 HVOUT7
17 HVOUT27 HVOUT6
18 HVOUT28 HVOUT5
19 HVOUT29 HVOUT4
20 HVOUT30 HVOUT3
21 HVOUT31 HVOUT2
22 HVOUT32 HVOUT1
23 DATA OUT DATA OUT Data output for cascading to the data input of the next device.
24
N/C N/C No connect.
25
26
27
28 OE OE
Output enable input.
When OE is LOW, all HV outputs are forced into a LOW state,
regardless of data in each channel. When OE is HIGH, all HV
outputs reflect data latched.
29 CLK CLK Data shift register clock. Input are shifted into the shift register on
the positive edge of the clock.
30 GND GND Logic and high voltage ground.
31 VDD VDD Low voltage logic power rail.
32 STR STR Strobe.
33 DATA IN DATA IN Serial data input. Data needs to be present before each rising
edge of the clock.
34 N/C N/C No connect.
2015 Microchip Technology Inc. DS20005418B-page 5
HV5122 / HV5222
35 HVOUT1HV
OUT32
High voltage outputs.
36 HVOUT2HV
OUT31
37 HVOUT3HV
OUT30
38 HVOUT4HV
OUT29
39 HVOUT5HV
OUT28
40 HVOUT6HV
OUT27
41 HVOUT7HV
OUT26
42 HVOUT8HV
OUT25
43 HVOUT9HV
OUT24
44 HVOUT10 HVOUT23
TABLE 2-1: PIN DESCRIPTION PQFP (CONTINUED)
Pin # HV5122 HV5222 Description
TABLE 2-2: PIN DESCRIPTION PLCC
Pin # HV5122 HV5222 Description
1HV
OUT16 HVOUT17
High voltage outputs
2HV
OUT17 HVOUT16
3HV
OUT18 HVOUT15
4HV
OUT19 HVOUT14
5HV
OUT20 HVOUT13
6HV
OUT21 HVOUT12
7HV
OUT22 HVOUT11
8HV
OUT23 HVOUT10
9HV
OUT24 HVOUT9
10 HVOUT25 HVOUT8
11 HVOUT26 HVOUT7
12 HVOUT27 HVOUT6
13 HVOUT28 HVOUT5
14 HVOUT29 HVOUT4
15 HVOUT30 HVOUT3
16 HVOUT31 HVOUT2
17 HVOUT32 HVOUT1
18 DATA OUT DATA OUT Data output for cascading to the data input of the next device.
19
N/C N/C No connect.
20
21
22
23 OE OE
Output enable input.
When OE is LOW, all HV outputs are forced into a LOW state,
regardless of data in each channel. When OE is HIGH, all HV
outputs reflect data latched.
24 CLK CLK Data shift register clock. Input are shifted into the shift register on
the positive edge of the clock.
25 GND GND Logic and high voltage ground.
26 VDD VDD Low voltage logic power rail.
27 STR STR Strobe.
HV5122 / HV5222
DS20005418B-page 6 2015 Microchip Technology Inc.
28 DATA IN DATA IN Serial data input. Data needs to be present before each rising
edge of the clock.
29 N/C N/C No connect.
30 HVOUT1HV
OUT32
High voltage outputs.
31 HVOUT2HV
OUT31
32 HVOUT3HV
OUT30
33 HVOUT4HV
OUT29
34 HVOUT5HV
OUT28
35 HVOUT6HV
OUT27
36 HVOUT7HV
OUT26
37 HVOUT8HV
OUT25
38 HVOUT9HV
OUT24
39 HVOUT10 HVOUT23
40 HVOUT11 HVOUT22
41 HVOUT12 HVOUT21
42 HVOUT13 HVOUT20
43 HVOUT14 HVOUT19
44 HVOUT15 HVOUT18
TABLE 2-2: PIN DESCRIPTION PLCC (CONTINUED)
Pin # HV5122 HV5222 Description
2015 Microchip Technology Inc. DS20005418B-page 7
HV5122 / HV5222
3.0 FUNCTIONAL DESCRIPTION
Table 3-1 provides functional information about
HV5122 / HV5222.
Note 1: H = high level, L = low level, X = irrelevant, = high-to-low transition
2: = dependent on previous stage’s state before the last CLK high-to-low transition
3.1 Power-Up and Recommended
Operating Conditions
To power-up HV5122 / HV5222, perform the following
power-up sequence:
1. Connect ground
2. Apply VDD
3. Set all inputs to a known state
To power-down the device, reverse the steps above.
FIGURE 3-1: Input and Output Equivalent Circuits
TABLE 3-1: FUNCTIONAL TABLE
Function
Inputs Outputs
Data In CLK OE STR Shift Reg HV Outputs Data Out
1 2...32 1 2...32
All on X X X L ●●...ON ON...ON
All off X X L H ●●...OFF OFF...OFF
Load S/R H/L L H H/L Q1...Q31 OFF OFF...OFF Q32
Output Enable X H/L H H H/L ...ON/OFF ...●●
TABLE 3-2: RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Units
VDD Logic voltage supply 10.8 12 13.2 V
HVOUT High voltage output -0.3 - 225 V
VIH High-level input voltage VDD-2.0 - VDD V
VIL Low-level input voltage 0 - 2.0 V
fCLK Clock frequency - - 8.0 MHz
TAOperating free-air temperature -40 - +85 °C
VDD
INPUT
GND
HV
OUT
Logic Inputs
GND
DATA
OUT
Logic Data Output High Voltage Outputs
VDD
HV
IN
GND
HV5122 / HV5222
DS20005418B-page 8 2015 Microchip Technology Inc.
FIGURE 3-2: Switching Waveforms
DATA
IN Data Valid 1
CLK
DATA
OUT
DATA
OUT
STR
t
DLH
t
SU
t
H
t
WL
t
WH
t
DHL
HV
OUT
50% 50% 50%
50%
50%
15V
t
ON
12V
0V
12V
0V
2015 Microchip Technology Inc. DS20005418B-page 9
HV5122 / HV5222
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
44-lead PLCC Example
XXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
e3
HV5122PJ
1526343
e3
44-lead PQFP Example
XXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
e3
HV5122PG
1526343
e3
HV5122 / HV5222
DS20005418B-page 10 2015 Microchip Technology Inc.
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 ș
Dimension
(mm)
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*
0.80
BSC
0.73
1.95
REF
0.25
BSC
0
O
NOM - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5
O
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7
O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings not to scale.
SD # DSPD 44PQFPPG V i C041309
1
44
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
D
D1
E
E1
be
Side View
A2
A
A1
Note 1
(Index Area
D1/4 x E1/4)
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2015 Microchip Technology Inc. DS20005418B-page 11
HV5122 / HV5222
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
Symbol A A1 A2 b b1 D D1 E E1 e R
Dimension
(inches)
MIN .165 .090 .062 .013 .026 .685 .650 .685 .650
.050
BSC
.025
NOM .172 .105 - - - .690 .653 .690 .653 .035
MAX .180 .120 .083 .021 .036.695 .656 .695 .656 .045
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
.150 MAX
.048/.042 x 45O
1
.075 MAX
640
D
D1
E1 E
Top View
Horizontal Side View
View B
AA2
A1
Seating
Plane
e
b
Note 1
(Index Area)
.056/.042 x 45O
.020max
(3 Places)
.020 MIN
Vertical Side View
View B
Note 2
44
b1
Base
Plane
R
Notes:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
2. $FWXDOVKDSHRIWKLVIHDWXUHPD\YDU\
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
HV5122 / HV5222
DS20005418B-page 12 2015 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision A (August 2015)
Update file to new format
Revision B (October 2015)
Updated Continuous total power dissipation in
Absolute Maximum Ratings on page 3
Corrected a typo on page 13
2015 Microchip Technology Inc. DS20005418B-page 13
HV5122 / HV5222
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: HV5122 = 32-Channel Serial to Parallel Converter,
data shifts in counter-clockwise direction
HV5222 = 32-Channel Serial to Parallel Converter,
data shifts in clockwise direction
Package: PG = 44-Lead PQFP
PJ = 44-Lead PLCC
Environmental G = Lead (Pb)-free/ROHS-compliant package
Media Type: (blank) = 96/Tray for PG package
= 27/Tube for PJ package
Examples:
a) HV5122PG-G Data shifts in counter-
clockwise direction, 44-
Lead PQFP package,
96/Tray
b) HV5222PJ-G Data shifts in clockwise
direction, 44-Lead PLCC
package, 27/Tube
PART NO. X
Device
X
Environmental
XX
Package
Options
Media
--
Type
DS20005418B-page 14 2015 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
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The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-882-6
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Microchip received ISO/TS-16949:2009 certification for its worldwide
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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QUALITYMANAGEMENTS
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005418B-page 15 2015 Microchip Technology Inc.
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Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
07/14/15