STA680 HD RadioTM baseband receiver Features IBOC (in-band on-channel) digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes Dual-channel HD 1.5 for background scanning and data services HD codec (HDC) audio decompression Metadata support for HD Radio reception MPS (main program service) and PAD (program associated data) data decoder Advanced HD Radio feature support: - Conditional access (CA) - Apple ID3 tag - Multicasting - Electronic program guide (EPG) - Real-time traffic - Audio time shifting Variable input base-band data-rate I2S-like interface supporting 650, 675, 744.1875, 882, 912 kS/s data rates Secondary RF base-band interface for dual tuner applications Glueless interface to Synchronous SDRAM addressing up to 512 Mbit of SDRAM in x16 configuration Optional Serial Flash memory SPI interface for application code storage IIS serial audio interface with programmable sample rate converter Table 1. LQFP144 (20x20x1.4 mm) LFBGA 168 balls (12x12x1.4 mm) Primary and secondary serial interfaces for based on industry standard IIC and SPI Several General purpose IOs One Internal clock oscillator and two internal PLLs External clock input 1.2 V core supply; 3.3 V I/O supply Automotive qualified in accordance with AEC-Q100 Description The STA680 is an HD-radio base-band processor for car-radio applications. The STA680 functionality includes audio decompression and data processing, while multiple interfaces ensure flexible integration into the system. The STA680 takes full advantage of HD 1.5 Radio benefits including CD-like audio quality from HD Radio FM broadcasts and FM-like audio quality using HD Radio AM, while program associated data or traffic information is received from the second channel. Device summary Order code Package(1) Packing STA680 LFBGA 168 balls (12x12x1.4 mm) Tray STA680Q LQFP144 (20x20mm) Tray 1. ECOPACK(R) compliant. November 2010 Doc ID 14860 Rev 4 1/43 www.st.com 1 Contents STA680 Contents 1 2 3 4 5 2/43 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.1 LQFP description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.2 LFBGA description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.3 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.4 I/Os supply groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 Receiver system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 HD Radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 Dual channel HD 1.5 Radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 Overview of main functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.1 Adjacent channel filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 HiFi2 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.3 Vectra core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.5 Hardware accelerator (VITERBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operation and general remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 Clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power supply ramp-up phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Oscillator setting time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 Normal operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital I/O and memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Interfaces: LQFP vs. LFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Base-band I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 Base-band I2S interface frequency diversity . . . . . . . . . . . . . . . . . . . . . . 27 5.4 Audio interface (AIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 14860 Rev 4 STA680 Contents 5.5 5.6 5.4.1 Output serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4.2 Audio sample rate converter (ASRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Serial peripheral interfaces (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5.1 Host micro serial peripheral interface (SPI1) . . . . . . . . . . . . . . . . . . . . . 31 5.5.2 Flash serial peripheral interface (SPI2) . . . . . . . . . . . . . . . . . . . . . . . . . 31 2 I C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6.1 5.7 6 Host micro I2C interface (I2C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 14860 Rev 4 3/43 List of tables STA680 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. 4/43 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power on timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interface list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Baseband interfaces pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 BBI timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AIF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial audio interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SPI interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Host micro SPI pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flash SPI pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Host and auxiliary I2C interface pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C1 interface device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SDRAM Interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SDRAM interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 14860 Rev 4 STA680 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 LQFP pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LFBGA ball-out (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional block diagram for HD Radio demodulating and decoding . . . . . . . . . . . . . . . . . 18 Clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Crystal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BBI waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial audio interface waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SPI interface timings diagrams and waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timing diagrams and waveform for the two I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 32 Timing diagrams and waveform for the SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . 34 LQFP144 (20x20mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 40 LFBGA 168 balls (12x12x1.4 mm) mechanical data and package dimensions . . . . . . . . . 41 Doc ID 14860 Rev 4 5/43 Block diagram and pin description STA680 1 Block diagram and pin description 1.1 Block diagram Figure 1. Functional block diagram 8MB SDRAM STA680 RF Tuner (i.e. TDA7706) SDRAM Interface Core System Vectra LX Tensilica DSP HiFi Tensilica Core OTP BBI 2 BaseBand Interface AHB Bus BBI 1 RF Tuner (i.e. TDA7706) Turner & Audio Interface I2S Clock Gen. Unit Peripheral PLL System PLL Audio Interface Viterbi AHB/APB Bridge DMA Boundary Scan JTAG Peripheral Bus LDO Crystal Oscillator Xtal 28224 6/43 I/O & Control Interface SPI Flash 1MB SERIAL FLASH (bootable) Doc ID 14860 Rev 4 SPI SD/MMC SPI/I2C Micr i/f MAIN MICRO GPIO STA680 Block diagram and pin description 1.2 Pin description The STA680 is available in two different packages targeting different application cost and complexity. It comes both in a 20x20mm LQFP package with 144 pins, and in a 12x12mm LFBGA with 169 balls with 0.8mm pitch. 1.2.1 LQFP description Figure 2 presents the pinout of the STA680 for the LQFP package option. Different colors have been used for I/O signals from different interfaces according to Table 2 reported in Section 1.2.3. VDD GND SDR_A3 SDR_A2 SDR_A1 SDR_A0 SDR_A10 GND_RAM_IO VDD_RAM_IO SDR_BA1 SDR_BA0 SDR_CS_N GND VDD SDR_RAS SDR_CAS SDR_WE_N SDR_A4 GND_RAM_IO VDD_RAM_IO SDR_A5 SDR_A6 SDR_A7 GND VDD SDR_A8 SDR_A9 SDR_A11 SDR_A12 GND_RAM_IO VDD_RAM_IO SDR_CKE SDR_DQM1 SDR_DQM0 GND VDD 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 LQFP pinout (top view) 144 Figure 2. TESTMODE 1 108 SDR_D7 TRST_N 2 107 SDR_D6 TCK 3 106 SDR_D5 TMS 4 105 VDD_RAM_IO TDI 5 104 GND_RAM_IO TDO 6 103 SDR_D4 RTS_GPIO0 7 102 SDR_D3 VDD 8 101 SDR_D2 9 100 VDD CTS_GPIO1 10 99 GND GND_GEN_IO 11 98 SDR_D1 VDD_GEN_IO 12 97 SDR_D0 TXD_GPIO2 13 96 SDR_D8 RXD_GPIO3 14 95 SDR_D9 RESET_N 15 94 VDD_RAM_IO SPI1_SS0_N 16 93 GND_RAM_IO SPI1_SCK 17 92 SDR_D10 SPI1_MOSI 18 91 SDR_D11 VDD 19 90 SDR_D12 GND 20 89 VDD SPI1_MISO 21 88 GND GND_GEN_IO 22 87 SDR_D13 VDD_GEN_IO 23 86 SDR_D14 IIC1_SCL 24 85 SDR_D15 IIC1_SDA 25 84 SDR_FEED_CLK BB2_Q 26 83 SDR_CLK_RAM3V3 GND 27 Base band input interface 82 VDD_RAM_IO_1V8 VDD 28 Audio input interface 81 GND_RAM_IO_1V8 GND_GEN_IO 29 80 GND 79 VDD 78 SPI2_MISO GND Color legend: JTAG interface UART GPIO interface Host microprocessor interface Flash interface Audio output interface VDD_GEN_IO 30 BB2_I 31 BB2_WS 32 77 SPI2_SS1_N BB2_BCK 33 76 SPI2_SCK BLEND 34 75 SPI2_SS0_N BB1_Q 35 74 SPI2_MOSI VDD 36 73 VDD_FSH_IO 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 GND GND_GEN_IO VDD_GEN_IO BB1_I BB1_WS BB1_BCK SPDIF AUDIO_IN_ABCK AUDIO_IN_AWS VDD GND GND_GEN_IO VDD_GEN_IO AUDIO_IN_ADAT DAC256X ADAT3 ADAT2 ADAT AWS ABCK CLK_IN GND VDD GND_PLL_DIG VDD_PLL_DIG GND_PLL0_ANA VDD_PLL0_ANA GND_OSC VDD_OSC OSC_IN OSC_OUT VDD_REG3V3 VDD_REG1V8 GND VDD GND_FSH_IO SDRAM interface Doc ID 14860 Rev 4 AC00504 7/43 Block diagram and pin description 1.2.2 STA680 LFBGA description Figure 3 presents the ball-out of the STA680 for the LFBGA package option. Different colors have been used for I/O signals from different interfaces according to Table 2 reported in Section 1.2.3. Figure 3. 1 A LFBGA ball-out (top view) 2 3 4 5 6 7 8 9 10 11 GPIO6 BB2_BCK BB2_I GND_GEN_IO IIC1_SDA SPI1_MISO SPI1_SCK RESET_N TXD_GPIO2 RTS_GPIO0 VDD_GEN_IO TESTMODE CTS_GPIO1 VDD_GEN_IO B GPIO5 BB1_Q BLEND BB2_WS GND_GEN_IO BB2_Q IIC1_SCL SPI1_MOSI SPI1_SS0_N RXD_GPIO3 C BB1_WS BB1_I ADAT2 IIC2_SDA GPIO7 IIC2_SCL IIC1_DA SPI3_MOSI SPI3_MISO SPI3_SCK TDI BB1_BCK IIC2_DA VDD VDD SPI3_SS_N GPIO4 VDD_GEN_IO VDD_GEN_IO D E AUDIO_IN_ ABCK SPDIF ADAT3 VDD_PLL_DIG F AUDIO_IN_ ADAT AUDIO_IN_ AWS GND_PLL_ DIG GND_PLL_ DIG G AWS ADAT GND_GEN_IO GND_GEN_IO H 12 13 14 SDR_A3 TRST_N TCK SDR_A1 SDR_A2 TDO TMS SDR_A10 SDR_A0 VDD MODEOP_FSH SDR_BA0 SDR_BA1 VDD MODEOP_GEN SDR_RAS_N GND GND GND GND DAC256X GND GND GND GND SDR_CAS_N ABCK GND GND GND GND SDR_A4 SDR_A5 GND_RAM_IO GND GND GND GND VDD VDD SDR_A7 SDR_A6 VDD VDD SDR_A9 SDR_A8 SDR_A12 SDR_A11 GND_PLL1_ GND_PLL0_ ANA ANA J VDD_OSC GND_OSC K OSC_OUT CLK_IN VDD VDD_REG3V3 L OSC_IN GND_OSC VDD VDD_REG3V3 VDD_FSH_IO GND_FSH_IO M VDD_PLL1_ ANA VDD_PLL0_ ANA SPI2_SS1_N SPI2_SS2_N VDD_RAM_IO GND_RAM_IO GND_RAM_IO GND_RAM_IO _1V8 _1V8 SPI2_SS3_N RFU SDR_D13 SDR_D10 SDR_WE_N VDD_RAM_IO VDD_RAM_IO VDD_RAM_IO GND_RAM_IO GND_RAM_IO SDR_DQM1 N VDD_REG1V8 VDD_REG1V8 SPI2_MOSI SPI2_SCK SDR_CLK_ RAM3V3 SDR_D15 SDR_D12 SDR_D9 SDR_D0 SDR_D2 SDR_D4 SDR_D6 P SPI2_SS0_N SPI2_MISO SDR_FEED_ CLK SDR_D14 SDR_D11 SDR_D8 SDR_D1 SDR_D3 SDR_D5 SDR_D7 SDR_CS_N SDR_CKE SDR_DQM0 AC00707 Color legend: Ball unused 8/43 Ball not present JTAG interface UART GPIO Memory card Host microinterface interface processor interface Flash interface Doc ID 14860 Rev 4 Base band input interface Audio Input interface Audio Output interface SDRAM interface STA680 1.2.3 Block diagram and pin description Pin list The Table 2 describes the primary function and behavior of the STA680 pins. Table 2. Pin # Pins description Ball # Signal name Type Pull-up /down(1) Electrical Supply group A13 TESTMODE I Pull-down 1.8 V or 3.3 V Generic IO supply Factory test mode enable Description Test 1 Standard 1149.1 JTAG interface 2 B14 TRST_N I Pull-up 1.8 V or 3.3 V Generic IO supply JTAG active-low test reset 3 C12 TCK I Pull-down 1.8 V or 3.3 V Generic IO supply JTAG test clock 4 D12 TMS I Pull-up 1.8 V or 3.3 V Generic IO supply JTAG test mode state 5 C11 TDI I Pull-up 1.8 V or 3.3 V Generic IO supply JTAG test data in 6 D11 TDO O - 1.8 V or 3.3 V Generic IO supply JTAG test data out GPIO & UART interfaces 7 A11 RTS_GPIO0 I/O Pull-up 1.8 V or 3.3 V Generic IO supply UART ready to send / GPIO bit 0 10 B11 CTS_GPIO1 I/O Pull-up 1.8 V or 3.3 V Generic IO supply UART clear to send / GPIO bit 1 13 A10 TXD_GPIO2 I/O Pull-up 1.8 V or 3.3 V Generic IO supply UART transmit data / GPIO bit 2 14 B10 RXD_GPIO3 I/O Pull-up 1.8 V or 3.3 V Generic IO supply UART receive data / GPIO bit 3 Not bonded D10 GPIO4 I/O Pull-up 1.8 V or 3.3 V Generic IO supply GPIO bit 4 Not bonded B1 GPIO5 I/O Pull-up 1.8 V or 3.3 V Generic IO supply GPIO bit 5 Not bonded A2 GPIO6 I/O Pull-up 1.8 V or 3.3 V Generic IO supply GPIO bit 6 Not bonded C5 GPIO7 I/O Pull-up 1.8 V or 3.3 V Generic IO supply GPIO bit 7 A9 RESET_N I Pull-up 1.8 V or 3.3 V Generic IO supply Device active-low reset Reset 15 Doc ID 14860 Rev 4 9/43 Block diagram and pin description Table 2. Pin # STA680 Pins description (continued) Ball # Signal name Type Pull-up /down(1) Electrical Supply group Description Host processor interfaces 16 B9 SPI1_SS0_N I Pull-up 1.8 V or 3.3 V Generic IO supply SPI interface 1 active-low slave select 17 A8 SPI1_SCK I Pull-up 1.8 V or 3.3 V Generic IO supply SPI interface 1 serial clock 18 B8 SPI1_MOSI I Pull-up 1.8 V or 3.3 V Generic IO supply SPI interface 1 serial data master out/slave in 21 A7 SPI1_MISO O Pull-up 1.8 V or 3.3 V Generic IO supply SPI interface 1 serial data master in/slave out 24 B7 IIC1_SCL I/O Pull-up 1.8 V or 3.3 V Generic IO supply IIC interface 1 serial clock line 25 A6 IIC1_SDA I/O Pull-up 1.8 V or 3.3 V Generic IO supply IIC interface 1 serial data line Not bonded C7 IIC1_DA I/O Pull-up 1.8 V or 3.3 V Generic IO supply IIC interface 1 data acknowledged Not bonded C6 IIC2_SCL I/O Pull-up 1.8 V or 3.3 V Generic IO supply Reserved Not bonded C4 IIC2_SDA I/O Pull-up 1.8 V or 3.3 V Generic IO supply Reserved Not bonded D4 IIC2_DA I/O Pull-up 1.8 V or 3.3 V Generic IO supply Reserved IIS tuner interfaces 40 C2 BB1_I I Pull-down 1.8 V or 3.3 V Generic IO supply Primary baseband interface serial I data 35 B2 BB1_Q I Pull-down 1.8 V or 3.3 V Generic IO supply Primary baseband interface serial Q data 41 C1 BB1_WS I Pull-down 1.8 V or 3.3 V Generic IO supply Primary baseband interface word strobe 42 D3 BB1_BCK I Pull-down 1.8 V or 3.3 V Generic IO supply Primary baseband interface bit clock 31 A4 BB2_I I Pull-down 1.8 V or 3.3 V Generic IO supply Secondary baseband interface serial I data 26 B6 BB2_Q I Pull-down 1.8 V or 3.3 V Generic IO supply Secondary baseband interface serial Q data 32 B4 BB2_WS I Pull-down 1.8 V or 3.3 V Generic IO supply Secondary baseband interface word strobe 33 A3 BB2_BCK I Pull-down 1.8 V or 3.3 V Generic IO supply Secondary baseband interface bit clock 10/43 Doc ID 14860 Rev 4 STA680 Table 2. Pin # Block diagram and pin description Pins description (continued) Ball # Signal name Type Pull-up /down(1) Electrical Supply group Description IIS audio input interface 45 F2 AUDIO_IN_AWS I Pull-up 1.8 V or 3.3 V Generic IO supply Reserved 44 E1 AUDIO_IN_ABCK I Pull-up 1.8 V or 3.3 V Generic IO supply Reserved 50 F1 AUDIO_IN_ADAT I Pull-down 1.8 V or 3.3 V Generic IO supply Reserved Audio output interfaces 55 G1 AWS I/O Pull-up 1.8 V or 3.3 V Generic IO supply Digital audio output word strobe 56 H3 ABCK I/O Pull-up 1.8 V or 3.3 V Generic IO supply Digital audio output clock 54 G2 ADAT O - 1.8 V or 3.3 V Generic IO supply Digital audio output serial data 53 C3 ADAT2 O - 1.8 V or 3.3 V Generic IO supply Reserved 52 E3 ADAT3 O - 1.8 V or 3.3 V Generic IO supply Reserved 43 E2 SPDIF O - 1.8 V or 3.3 V Generic IO supply Reserved 34 B3 BLEND O - 1.8 V or 3.3 V Generic IO supply Digital audio output blend output 51 G3 DAC256X O - 1.8 V or 3.3 V Generic IO supply Digital audio output oversampling clock Reference digital clock Clock & oscillator 57 K2 CLK_IN I - 1.8 V or 3.3 V Generic IO supply 66 L1 OSC_IN ana - 1.8 V Osc supply 28,224MHz crystal in or digital clock input 67 K1 OSC_OUT ana - 1.8 V Osc supply Crystal output SPI Flash interface 78 P4 SPI2_MISO I Pull-up 1.8 V or 3.3 V Flash IO supply SPI interface 2 serial data master in/slave out 74 N3 SPI2_MOSI O Pull-up 1.8 V or 3.3 V Flash IO supply SPI interface 2 serial data master out/slave in 75 P3 SPI2_SS0_N O Pull-up 1.8 V or 3.3 V Flash IO supply SPI interface 2 active-low slave select 0 77 M3 SPI2_SS1_N O Pull-up 1.8 V or 3.3 V Flash IO supply Reserved Not bonded M4 SPI2_SS2_N O Pull-up 1.8 V or 3.3 V Flash IO supply Reserved Doc ID 14860 Rev 4 11/43 Block diagram and pin description Table 2. STA680 Pins description (continued) Pin # Ball # Signal name Type Pull-up /down(1) Electrical Supply group Not bonded M5 SPI2_SS3_N O Pull-up 1.8 V or 3.3 V Flash IO supply Reserved 76 N4 SPI2_SCK O Pull-up 1.8 V or 3.3 V Flash IO supply SPI interface 2 serial clock Description SPI SD/MMC interface Not bonded C9 SPI3_MISO I Pull-up 1.8 V or 3.3 V Generic IO supply Reserved Not bonded C8 SPI3_MOSI O Pull-up 1.8 V or 3.3 V Generic IO supply Reserved Not bonded D9 SPI3_SS_N O Pull-up 1.8 V or 3.3 V Generic IO supply Reserved Not bonded C10 SPI3_SCK O Pull-up 1.8 V or 3.3 V Generic IO supply Reserved I - 3.3 V SDRAM IO supply Feedback clock from SDRAM interface SDRAM interface 84 P5 83 N5 SDR_CLK_RAM 3V3 O - 3.3 V SDRAM IO supply Clock to SDRAM for 3.3 V interface 97 N9 SDR_D0 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 0 98 P9 SDR_D1 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 1 101 N10 SDR_D2 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 2 102 P10 SDR_D3 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 3 103 N11 SDR_D4 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 4 106 P11 SDR_D5 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 5 107 N12 SDR_D6 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 6 108 P12 SDR_D7 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 7 96 P8 SDR_D8 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 8 95 N8 SDR_D9 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 9 92 M8 SDR_D10 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 10 91 P7 SDR_D11 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 11 12/43 SDR_FEED_CLK Doc ID 14860 Rev 4 STA680 Table 2. Block diagram and pin description Pins description (continued) Pin # Ball # Signal name Type Pull-up /down(1) Electrical Supply group 90 N7 SDR_D12 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 12 87 M7 SDR_D13 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 13 86 P6 SDR_D14 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 14 85 N6 SDR_D15 I/O - 3.3 V SDRAM IO supply SDRAM bidirectional data bit 15 111 N13 SDR_DQM0 O - 3.3 V SDRAM IO supply Low-byte data input/output mask 112 M13 SDR_DQM1 O - 3.3 V SDRAM IO supply High-byte data input/output mask 128 G13 SDR_WE_N O - 3.3 V SDRAM IO supply Active-low write enable 129 G12 SDR_CAS_N O - 3.3 V SDRAM IO supply Active-low column address strobe 130 F13 SDR_RAS_N O - 3.3 V SDRAM IO supply Active-low row address strobe 113 M14 SDR_CKE O - 3.3 V SDRAM IO supply Clock enable 133 F14 SDR_CS_N O - 3.3 V SDRAM IO supply Active-low chip select 134 E13 SDR_BA0 O - 3.3 V SDRAM IO supply Bank select address 0 135 E14 SDR_BA1 O - 3.3 V SDRAM IO supply Bank select address 1 139 D14 SDR_A0 O - 3.3 V SDRAM IO supply Address bit 0 to SDRAM 140 C13 SDR_A1 O - 3.3 V SDRAM IO supply Address bit 1 to SDRAM 141 C14 SDR_A2 O - 3.3 V SDRAM IO supply Address bit 2 to SDRAM 142 B13 SDR_A3 O - 3.3 V SDRAM IO supply Address bit 3 to SDRAM 127 H12 SDR_A4 O - 3.3 V SDRAM IO supply Address bit 4 to SDRAM 124 H13 SDR_A5 O - 3.3 V SDRAM IO supply Address bit 5 to SDRAM 123 J14 SDR_A6 O - 3.3 V SDRAM IO supply Address bit 6 to SDRAM 122 J13 SDR_A7 O - 3.3 V SDRAM IO supply Address bit 7 to SDRAM Doc ID 14860 Rev 4 Description 13/43 Block diagram and pin description Table 2. STA680 Pins description (continued) Pin # Ball # Signal name Type Pull-up /down(1) Electrical Supply group 119 K14 SDR_A8 O - 3.3 V SDRAM IO supply Address bit 8 to SDRAM 118 K13 SDR_A9 O - 3.3 V SDRAM IO supply Address bit 10 to SDRAM 138 D13 SDR_A10 O - 3.3 V SDRAM IO supply Address bit 10 to SDRAM 117 L14 SDR_A11 O - 3.3 V SDRAM IO supply Address bit 11 to SDRAM 116 L13 SDR_A12 O - 3.3 V SDRAM IO supply Address bit 12 to SDRAM SDRAM IO supply Define the opereting voltage of the "Generic I/O" supply group. If tied low the I/Os work at 1.8V else they work at 3.3V. Default value is 3.3V. Define the opereting voltage of the "Flash I/O" supply group. If tied low the I/Os work at 1.8V else they work at 3.3V. Default value is 3.3V. Description Supplies Not bonded F12 MODEOP_GEN I Pull-up 3.3 V Not bonded E12 MODEOP_FSH I Pull-up 3.3 V SDRAM IO supply 8, 19, 28, 36, 46, 59, 71, 79, 89, 100, 109, 120, 131, 144 D5, D6, E11, F11, J11, J12, K3, K11, K12, L3 VDD n/a - 1.2 V Core supply Power supply for core logic 9, 20, 27, 37, 47, 58, 70, 80, 88, 99, 110, 121, 132, 143 F6, F7, F8, F9, G6, G7, G8, G9, H6, H7, H8, H9, J6, J7, J8, J9 GND n/a - - Core supply Ground for core logic 14/43 Doc ID 14860 Rev 4 STA680 Table 2. Block diagram and pin description Pins description (continued) Pin # Ball # Signal name Type Pull-up /down(1) Electrical Supply group 11, 22, 29, 38, 48 A5, B5, H1, H2 GND_GEN_IO n/a - - Generic IO supply Generic I/Os ground 12, 23, 30, 39, 49 A12, B12, D1, D2 VDD_GEN_IO n/a - 1.8 V or 3.3 V Generic IO supply Generic I/Os power supply 72 L6 GND_FSH_IO n/a - - Flash IO supply 73 L5 VDD_FSH_IO n/a - 1.8 V or 3.3 V Flash IO supply 93, 104, 115, 126, 137 H14, L11, L12, M11, M12 GND_RAM_IO n/a - - SDRAM IO supply Ground for SDRAM Interface I/Os 94, 105, 114, 125, 136 G14, M9, M10 VDD_RAM_IO n/a - 3.3 V SDRAM IO supply Power supply for SDRAM 60 F3, F4 GND_PLL_DIG n/a - - 61 E4 VDD_PLL_DIG n/a - 1.2 V 62 J4 GND_PLL0_ANA n/a - - PLL analog supply Ground for PLL0 analog part 62 J3 GND_PLL1_ANA n/a - - PLL analog supply Ground for PLL1 analog part (2) 63 M2 n/a - 1.8 V PLL analog supply 63 M1 n/a - 1.8 V PLL analog supply 64 J2, L2 GND_OSC n/a - - Osc supply Ground for oscillator core 65 J1 VDD_OSC n/a - 1.8 V Osc supply Power supply for oscillator core 68 K4, L4 VDD_REG3V3 n/a - 3.3 V LDO supply Voltage regulator input power supply@3.3 Volt 69 N1, N2 VDD_REG1V8 n/a - 1.8 V LDO supply Voltage regulator output power supply@1.8 Volt VDD_PLL0_ANA VDD_PLL1_ANA Doc ID 14860 Rev 4 Description Ground for Flash Interface I/Os Power supply for Flash Inteface I/Os Interface I/Os PLL digital Ground for PLL digital part supply PLL digital Power supply for PLL digital part supply (2) Power supply for PLL0 analog part(3) Power supply for PLL1 analog part (3) 15/43 Block diagram and pin description Table 2. STA680 Pins description (continued) Pin # Ball # Signal name Type Pull-up /down(1) Electrical Supply group 82 L9 VDD_RAM_IO _1V8 n/a - 1.8 V n/a Reserved - connect to 1.8 V supplyt 81 L10 GND_RAM_IO _1V8 n/a - - n/a Reserved - Connect to ground M6 RFU n/a - n/a n/a Reserved for future use - do not connect Description Others Not bonded 1. Each input pin has a pull-up/down resistor to its default value. Unless otherwise specified, unused pins can be left unconnected after verifying that the impedance value of the pull-up/down resistor (see Table 20) is sufficient to guarantee noise immunity in user application environment. 2. In the LQFP package GND_PLL0_ANA and GND_PLL1_ANA are bonded together. 3. In the LQFP package VDD_PLL0_ANA and VDD_PLL1_ANA are bonded together. 1.2.4 I/Os supply groups The STA680 I/O signals can be grouped into three different supply domains, as shown in (see Table 2): Generic IO supply Flash IO supply SDRAM IO supply group In the LQFP package option all three groups must be supplied with 3.3 V. In the LFBGA package the three supply groups can independently operate at 3.3 V or 1.8 V. 16/43 The SDRAM_IO supply group must always be supplied with 3.3 V. The MODEOP_GEN pin selects the operating voltage of the Generic_IO supply group. If it is shorted to ground then all the I/O signals belonging to the Generic_IO supply group will work at 1.8 V; if the MODEOP_GEN pin is left floating or is tied to 3.3 V all the group I/Os will operate at 3.3 V. The MODEOP_FSH pin selects the operating voltage of the Flash_IO supply group. If it is shorted to ground then all the I/O signals belonging to the Flash_IO supply group will work at 1.8 V; if the MODEOP_FSH pin is left floating or is tied to 3.3 V the Flash Interface I/Os will operate at 3.3 V. Doc ID 14860 Rev 4 STA680 2 General description General description The STA680 is a system-on-chip designed for demodulating and decoding HD Radio signals. The STA680 is the base-band signal processor needed by an HD Radio receiver: it includes the OFDM demodulator and error correction and the audio and data decoding of the digital channel. Figure 4. System block diagram TDA7706 MICROPROCESSOR I2C/SPI BB_WCLK BB_I BB_Q BB_CLK FM/AM SPI2 SERIAL NORFLASH MEMORY STA 680 I2S_D I2S_WCLK blend I2S_CLK BB_I BB_Q Base-band I2S interface BB_CLK BB_WCLK SDRAM Digital audio Optional Audio Processing Blended L/R TDA7706 FM/AM DAC The architecture of STA680 consists of a mixed hardware/software implementation. Computation-intensive functional blocks are implemented using custom logic. Software implementation is more efficient for functional blocks where flexibility is needed. 2.1 Receiver system overview Such flexibility enables the STA680 to support both the HD 1.0 single-channel, and HD 1.5 double-channel applications, as shown in Figure 5 shows the internal simplified block diagram of the STA680. The STA680 receives the digital base-band signal from the digital tuner (e.g. TDA7706) and extracts the HD-encoded audio and data services as shown in Figure 5. STA680 is compatible with conventional base-band radio reception tuners (e.g. TDA7706). Doc ID 14860 Rev 4 17/43 General description STA680 Figure 5. Functional block diagram for HD Radio demodulating and decoding Blending signal SRC BBI1 Blending Logic Source Decoder Channel Decoder SRC 2.2 Digital PSK/QAM Demod OFDM Demod Deinterleaver and Convolutional Decoding DEMUX Secondary BB BBI2 HDC Decoder Data Processing DATA Sample Rate Converter and Serial Interfaces Main BB I2S SPI I2C HD Radio processing The STA680 HD Radio decoder performs the processing of the IBOC signal. The native internal processing data rate is 744.1875 kS/s for FM and 46.51171875 kS/s for AM. The input I2S base-band interface accepts several input sample rates thanks to the availability of a reconfigurable sample rate converter.The supported rates are: 650 kS/s, 675 kS/s, 882 kS/s and 912 kS/s. The STA680 is responsible for the detection, acquisition and demodulation of the IBOC signal. This processing is mainly performed inside the Vectra DSP core. The demodulated signal is then passed to the Hi-Fi processor for decoding and handling of data services. The digital 44.1 kHz decompressed audio is streamed out by means of the Digital Audio Interface. The STA680 requires a 4Mwords x16bits external SDRAM (with up to 32Mword x16bits supported) for data storage in order to process the HD Radio stream 2.3 Dual channel HD 1.5 Radio processing The is capable of simultaneously demodulating two different HD Radio streams. This feature enables the device to decode the main HD Radio audio stream in parallel with the data service broadcast by a different radio channel (for instance this feature allows to continue receiving traffic information provided by one radio station while listing to music from a different station). The implementation of the dual stream HD Radio processing requires that two AM/FM RF tuners be connected to the STA680, as shown in Figure 4 18/43 Doc ID 14860 Rev 4 STA680 General description 2.4 Overview of main functional blocks 2.4.1 Adjacent channel filter This module performs digital filtering of the IBOC channel. It receives the complex baseband I/Q IBOC signal input from the tuner and pre-conditions the signal for subsequent modem processing. 2.4.2 HiFi2 core The HiFi2 is a signal processing engine specifically designed to provide high quality 24-bit audio processing. The HiFi2 uses the Tensilica Xtensa LX engine with additional useful hardware capabilities such as: 2.4.3 Specialized instructions for 24-bit Audio MAC & stream coding Dual MAC (each supports 24 x 24 and 32 x 16 bit format) Huffman Encode / Decode and truncate functions Two way Single-Instruction-Multiple-Data arithmetic and logic operations Vectra core The Vectra LX is a powerful, configurable 32-bit RISC engine optimized for DSP with VLIW capabilities. The Vectra LX on board the STA680 includes eight MAC units, sixteen 160-bit vector operation registers, and a number of SIMD arithmetic instructions. Custom instructions in the Vectra are tailored to DSP applications such as filters and FFTs. The Vectra processor has been further configured with specific instructions for efficient performance on the HD Radio application. 2.4.4 DMA A ten-channel DMA controller is attached to the AHB bus to allow the Vectra and HiFi2 processor cores to efficiently move large data-blocks. 2.4.5 Hardware accelerator (VITERBI) The complex convolutional Viterbi hardware accelerator supports both K constant of 7 and 9, for IBOC digital FM and AM processing respectively. Doc ID 14860 Rev 4 19/43 Operation and general remarks STA680 3 Operation and general remarks 3.1 Clock schemes The STA680 needs an external clock source to drive the internal Phase Locked Loops (PLLs) that generates the clocks needed by the DSP cores and its peripherals. The STA680 accepts several external reference clock sources, as listed below: The reference clock can be supplied through the use of an external crystal or as a digital signal coming from an external IC. The reference clock can have different frequencies and can be fed to the STA680 through different input pins. The selection of the clock input mode is performed during the power-on phase of the device by latching the value of the pins ADAT3, BLEND and DAC256X on the rising edge of the RESET_N signal (see Chapter 3.2); this value shall be selected according to Table 3. Table 3. Reference clock configuration [ADAT3, BLEND, DAC256X] Clock type [0,0,0] (1) Crystal OSC_IN [0,0,1] Digital OSC_IN or CLK_IN (2) Digital OSC_IN or CLK_IN (2) 36.48 (2) 2.9184 [0,1,0] Clock frequency (MHz) Input pin 28.224 23.3472 [0,1,1] Digital OSC_IN or CLK_IN [1,0,0] Digital BB1_BCK 10.4 [1,0,1] Digital BB1_BCK 10.8 [1,1,0] Digital BB1_BCK 14.112 [1,1,1] Digital AUDIO_IN_ABCK 2.9184 1. Default setting. 2. When using OSC_IN pin to input the reference clock the CLK_IN pin must be connected to ground and vice versa. 20/43 Doc ID 14860 Rev 4 STA680 Operation and general remarks Figure 6 shows a simplified version of the internal clock generation unit. Figure 6. Clock generation unit SW application-controlled full - half frequency with 50% duty cycle DIV2 Core Clock PLL BB1_BCK AUDIO_IN_ABCK CLK_IN OSC_IN OSC_OUT clock to SDRAM up to 136 MHz (core in normal drive supply) up to 160 MHz (core in over drive supply) clock to Cores up to 166MHz Internal Oscillator 2 CLK_SEL Peripheral Clock PLL clock to Peripherals up to 70.56MHz (integer multiple of 44.1kHz audio sampling rate) PLL Settings OSC_EN Encoder DAC256X BLEND ADAT3 Clock generation unit Some remarks on the clock input pin follows: OSC_IN is always a 1.8 V input pin. CLK_IN, BB1_BCK and AUDIO_IN_ABCK are 3.3 V for the LQFP package, whereas they can be configured as either 3.3 V or 1.8 V pins for the LFBGA (see Chapter 1.2.4) When the clock is fed through the CLK_IN pin, the OSC_IN pin must be connected to ground. The BB1_BCK pin is the bit clock of the digital interface to the baseband Tuner. When this pin is selected as input for the reference clock, the selected clock frequency must be chosen compatibly with the Primary baseband Interface settings (see Chapter 5.2): - 10.4 MHz = 16 * 2 * 650 kHz BBI set to 650 Ksample/s - 10.8 MHz = 16 * 2 * 675 kHz BBI set to 675 Ksample/s - 14.112 MHz = 16 * 2 * 882 kHz BBI set to 882 Ksample/s The AUDIO_IN_ABCK pin is the bit clock of the digital audio input interface to the Tuner. When this pin is selected as the reference lock source, the STA680 Input Serial Audio Interface must be configured as follows: - Slave mode - Input sample rate = 45.6 kHz - Word length = 32 bit With this settings the reference clock frequency is 2.9184 MHz = 32 * 2 * 45.6 kHz. Doc ID 14860 Rev 4 21/43 Operation and general remarks 3.2 STA680 Power on This chapter describes the power-on procedure for the cold start (i.e. when the device is not supplied before being turned on). Figure 7 and Table 4 show the timing for the power up sequence of the cold start. Boot pins are latched at startup. Their default value is logic 0, in case logic 1 is needed a 6K2 pull-up resistor is needed on the corresponding boot line. After reset release, the boot selection lines becomes outputs. Figure 7. Power on timing SUPPLY 1V2 SUPPLY 3V3 TDC1V 8 SUPPLY 1V8 OSC_IN TOSC OSC_OUT TRST RESET_N ADAT3 BLEND DAC256X clock configuration default (no drive on lines) -> crystal 28.22MHz selected as clock source TCFG,H TCFG,S don't care stable data high impedance Generated Clocks primary boot secondary boot functional mode Min @ 2. 9184MHz @ 28. 224MHz @ 127MHz Max @ 38.48MHz Table 4. Power on timing parameters Symbol Parameter Min Max Same ramp-up time for 3.3 V and 1.2 V supply Unit Tramp-up External supply ramp-up time TDC1V8 DC1V8 regulator start-up time - 1 ms TOSC(1) Oscillator start-up time - 400 s Reset release time 2 - ms TRST - TCFG,S Setup time for clock configuration 0.1 - s TCFG,H Hold time for clock configuration 10 - ns 1. The oscillator start-up time depends on the crystal connected to the internal oscillator. The given value is estimated for a crystal with characteristic shown in Figure 8. Figure 8. Crystal characteristics Co CI1 Cm Rm Lm CI2 Model Rm Lm Cm CO Ci = CI1 = CI3 Equivalent circuit of a quartz crystal 22/43 Doc ID 14860 Rev 4 Value 50 Ohm 1.33 mH 26 fF 7 pF 38pF (33pF + 5pF parasitic) STA680 4 Power supply ramp-up phase Power supply ramp-up phase The external power supply circuit on the board has to ensure that all the power supplies be ramped-up to their specified levels within the time TRamp-up, The ramp up phase of each power domain should start at the same time. The RESET_N pin must be kept low since the beginning. For normal applications, the TESTMODE pin (Factory test mode enable, see Table 3) must be connected to ground. 4.1 Oscillator setting time Once the power supply has reached the operating level, the internal voltage regulator gets functional after TDC1V8 = 1 s (see Table 4) and starts supplying the 1.8 V voltage to internal IPs such as PLLs and Crystal Oscillator. The PLL is powered up but not yet functioning since the internal logic keeps it in bypass mode until a stable clock is available and STA680 has entered the secondary boot phase. As shown in Figure 7, if an external crystal is connected to the internal oscillator this will output a correct waveform after TOSC = 400 s (seeTable 4). Alternatively, if no crystal is used, a digital clock must be supplied according to the instructions detailed in Section 3.1. The RESET_N pin must be kept low for an additional TRST = 1.1 s both when using a crystal and when using an external reference clock. As described in Section 3.1 the internal clock configuration is defined by the status of the pins ADAT3, BLEND and DAC256X; this is latched on the rising edge of the RESET_N signal. The voltage of the three pins must be stable from at least TCFG = 0.1 s before the rising edge of the RESET_N signal. 4.2 Boot sequence Once the RESET_N signal has been released and the power up sequence correctly executed, the STA680 enters the boot procedure, which consists of two phases: 1. device setup 2. application authentication and download. During the first phase, the STA680 executes the on-chip primary boot code contained in the Boot ROM. The primary boot synchronizes the internal cores, initializes the SPI and IIC interfaces and automatically selects the secondary boot code source by looking for a pre-defined pattern into UART1, Flash, SPI1, IIC1 and IIC2. Once the source of the secondary boot code has been identified, the STA680 executes the following steps: 1. code authentication 2. SDRAM initialization 3. secondary boot code download to SDRAM. Doc ID 14860 Rev 4 23/43 Power supply ramp-up phase STA680 In order to decrease the boot time during the secondary phase, the STA680 performs the setup of the PLLs and sets the internal clock frequency to 28.224 MHz (see Figure 7). Subsequently it downloads and validates the application code either from the external Flash memory or from the host microcontroller. This ends the boot procedure. 4.3 Normal operation mode After the execution of the boot code, the device enters the normal operation mode by jumping to the main program loop. 24/43 Doc ID 14860 Rev 4 STA680 Digital I/O and memory interfaces 5 Digital I/O and memory interfaces 5.1 Interfaces: LQFP vs. LFBGA The STA680 connectivity depends on the selected package. The differences between the two package options are listed in Table 5. Table 5. Interface list Interface name Direction LQFP LFBGA Baseband interface 1 I Baseband interface 2 (data only) I I2S audio input I audio output (six channels) O primary interface (Micro) I/O secondary Interface I/O x SPI micro interface I/O SPI Flash interface (double chip select) I/O SPI Flash interface extension (up to 4 chip select) I/O x SPI SD/MMC I/O x SDRAM interface I/O S/PDIF interface O UART interface I/O 4 GPIO lines I/O x JTAG test interface (boundary scan only) I/O I 2S I2C I 2C Doc ID 14860 Rev 4 25/43 Digital I/O and memory interfaces 5.2 STA680 Base-band I2S interface The STA680 has two digital Base-Band Interfaces (BBI1 and BBI2), The tuners receive the analog signals from the antenna, sample them, perform down conversion and channel selection, and transmit the digital base-band streams to the STA680 by means of BBI1 and BBI2 Each BB interface consists of four wires: two serial data lines (I/Q), one bit clock line and one frame clock line. The serial data is always transmitted with the MSB first and a 16-bit word length. The complex base-band signal needs to be at zero IF. Most common data rates are supported by using the internal base-band sample rate converter. The allowed base-band interface data rates are: 650 kS/s, 675 kS/s, 882 kS/s 912 kS/s. Table 6. describes the pin functionality of both BBI1 and BBI2. Table 6. Baseband interfaces pin list Pin name Designation Type Drive BB1_WS Secondary base band interface word strobe I - BB1_BCK Primary baseband interface bit clock I - BB1_I Primary baseband interface serial I data I - BB1_Q Primary baseband interface serial Q data I - BB2_WS Secondary baseband interface word strobe I - BB2_BCK Secondary baseband interface bit clock I - BB2_I Secondary baseband interface serial I data I - BB2_Q Secondary baseband interface serial Q data I - The base-band interface supports the modes shown in Figure 9 Timing information for the protocols shown in Figure 9 is detailed in In Table 7. 26/43 Doc ID 14860 Rev 4 STA680 Figure 9. Digital I/O and memory interfaces BBI waveforms and timings 2/Fws BBx_WS Sample N+1 (I and Q) Sample N (I and Q) 1/Fbck,split BBx_BCK Ts BBx_I BBx_Q Th I11 ... ... I4 I3 I2 I1 I0 Q15 Q14 Q13 Q12 Q11 ... ... Q4 Q3 Q2 Q1 Q0 I15 I14 I13 I12 I11 ... ... I4 I3 I2 I1 I0 Q15 Q14 Q13 Q12 Q11 ... ... Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 I15 I14 I13 I12 Split Mode 1/Fws BBx_WS Sample N (Q) Sample N (I) 1/Fbck,mux BBx_BCK Ts BBx_I Th I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q3 Q2 Q1 Q0 Multiplexed Mode 1/Fws BBx_WS Sample N (Q) Sample N (I) 1/Fbck,afe BBx_BCK Th Ts BBx_I I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Q15 Q14 Q13 Q12 Q11 ... ... Q4 Q3 Q2 Q1 Q0 AFE Mode Table 7. AC00713 BBI timing values Working rate Symbol Parameter Unit Min. Fws 5.3 Max. Word strobe 650 675 744.188 882 912 kHz Fbck, split Bit clock in SPLIT mode 16 x Fws - - - 66 MHz Fbck, mux Bit clock in MUX mode 32 x Fws - - - 32 x Fws MHz Fbck, afe 32 x Fws - - - 66 MHz Bit clock in AFE mode Th Data hold time 4 - - - - ns Ts Data setup time 8 - - - - ns Base-band I2S interface frequency diversity When the STA680 is paired with the TDA7706 tuner it can benefit from the supported baseband interface frequency diversity that allows to improve the EMI robustness of the system. The frequency diversity technique allows the base-band data-rate to be varied in run-time depending on the frequency of the tuned station, thus moving the intrinsic radiation of the BBI digital lines away from the signal of interest. Doc ID 14860 Rev 4 27/43 Digital I/O and memory interfaces 5.4 STA680 Audio interface (AIF) The STA680 uses a stereo I2S interface for sending the decoded digital audio back to the tuner, where the blending with the legacy AM/FM demodulated audio occurs. The receivers and transmitters can be used either in master mode, running with the STA680 internal audio frequency of 44.1 kHz or in slave mode running with a frequency determined by the external device. In slave mode, the internal Audio Sample Rate Converter ((ASRC, see Chapter 5.4.2) adapts the external data rate (from 44.1 to 48 kSps) to the internal one. Table 8. AIF pin list Pin name Type Drive AWS Digital audio output word strobe I/O 4mA ABCK Digital audio output clock I/O 4mA ADAT Digital audio output serial data O 4mA Digital audio output oversampling clock (256 x Fs) O 4mA Digital audio output blend output O 4mA DAC256X BLEND 5.4.1 Designation Output serial audio interface (SAI) The output serial audio interface is used to send the decoded audio from the HD Radio Decoder to an external IC (e.g. TDA7706). The output SAI is an I2S interface which provides audio samples in stereo at a 44,1 kS/s data rate in master mode. In slave mode, other sample rates (from 44.1 to 48kSps) are supported by means of the internal ASRC (see Chapter 5.4.2). The output SAI interface is composed by three lines: one data line and two clock lines. The output SAI supports a 32x or 64x bit clock with 16-bit precision audio data. The 32x clock mode has not bit padding. The 64x clock mode adds 16-bits zero padding at the end of the 16-bit audio data. Figure 10 shows timing diagrams for the supported modes. An oversampled audio master-clock is also available for directly interfacing the STA680 to an external DAC. Table 8 shows the timing values for the output SAI interface. 28/43 Doc ID 14860 Rev 4 STA680 Digital I/O and memory interfaces Figure 10. Serial audio interface waveforms and timings 1/Faws RIGHT LEFT AWS 1/Fabck,16 ABCK ADAT D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D6 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 0 0 0 D3 D2 D1 D0 0 0 32X Mode (16 - bit data) 1/Faws RIGHT LEFT AWS 1/Fabck,32 ABCK Th Ts ADAT D15 D14 D13 ... ... D3 D2 D1 D0 0 0 0 ... ... 0 0 D15 D14 D13 D3 D2 D1 D0 64X Mode (32 - bit data) Table 9. Serial audio interface timing values Symbol Faws 5.4.2 AC00717 Parameter Word strobe Working rate 44.1 10 Hz 45.6 15 Hz Unit 48 15 Hz kHz Fabck,16 Bit clock for 16-bit data 32 x Faws MHz Fabck,32 Bit clock for 32-bit data 64 x Faws MHz Th Data hold time 5 ns Ts Data setup time 20 ns Audio sample rate converter (ASRC) The STA680 embeds a stereo channel sample rate converter to be used in combination with either the output (one single data-line) or the input SAI. The ASRC has a Total Harmonic Distortion plus Noise (THD+N) level at 1 kHz smaller than -85 dB (0.0056%). The supported data rates are: 44,100 ( 10 Hz), 45,600 ( 15 Hz) 48,000 ( 15 Hz) Doc ID 14860 Rev 4 29/43 Digital I/O and memory interfaces 5.5 STA680 Serial peripheral interfaces (SPI) The STA680 provides two serial peripheral interfaces: SPI1 is intended for communicating with the Host Microcontroller. SPI2 interfaces the STA680 to the external flash memory The maximum SPI clock frequency in master mode is 25 MHz. In slave mode the maximum input clock frequency is a function of the internal peripheral clock. F perif In particular the maximum frequency is F SPI = -------------- , where Fperif 56.448MHz 8 (for STA680-51001569-05000033-C0002.000 firmware version) is the frequency of the clock feeding the peripheral bus and blocks. Figure 11 shows the timing diagrams and waveform for the three SPI interfaces. Figure 11. SPI interface timings diagrams and waveforms Tss Tss SPIx_SS_N SPIx_SS_N 1/Fsck 1/Fsck SPIx_SCK cpol =0 SPIx_SCK cpol =0 SPIx_MOSI/MISO Z D7 D6 D5 Ts Th Ts D4 D3 D2 D1 D0 Z Z SPIx_MOSI/MISO D7 D6 Th D5 D4 D3 D1 D0 Z D1 D0 Z 1/Fsck 1/Fsck SPIx_SCK cpol =1 SPIx_SCK cpol =1 Z D7 D6 D5 D4 D3 D2 Th Ts Th Ts SPIx_MOSI/MISO D2 D1 D0 Z Z SPIx_MOSI/MISO D7 D6 D5 D4 D3 D2 SPIx_SCK cpha =1 SPIx_SCK cpha =0 AC00718 Table 10 shows the timing values for the SPI interface. Table 10. SPI interface timing values Working rate Symbol 30/43 Parameter Unit Min. Max. Tss Chip select 8/Fsck - ns Fsck Serial bit clock, slave mode 1.076 8000 kHz Fsck Serial bit clock, master mode 1.076 25000 kHz Th Data hold time 7 - ns Ts Data setup time 15 - ns Doc ID 14860 Rev 4 STA680 5.5.1 Digital I/O and memory interfaces Host micro serial peripheral interface (SPI1) SPI1 is used to interface the STA680 with a host processor interface. The communication with the host-microcontroller can alternatively be performed via I2C as described in Chapter 5.6.1. The Host Micro SPI is a slave only interface. For the relevant pin description see Table 11. Table 11. Host micro SPI pin list Pin name 5.5.2 Designation Type Drive SPI1_MISO Host Micro SPI data master in/slave out O 4mA SPI1_MOSI Host Micro SPI data master out/slave in I - SPI1_SCK Host Micro SPI clock i 4mA SPI1_SS_N Host Micro SPI active-low slave select 1 i 4mA Flash serial peripheral interface (SPI2) SPI2 is typically used for connecting the STA680 to an external Flash memory where the boot code and configuration parameters could be stored. The minimum required capacity for this purpose is 1 Mbit. SPI2 is master-only. Up to 4 chip select lines are available on the STA680 with the BGA package. For the relevant pin description see Table 12. Table 12. Flash SPI pin list Pin name Designation Type Drive SPI2_MISO Flash SPI data master in/slave out I - SPI2_MOSI Flash SPI data master out/slave in O 4mA SPI2_SCK Flash SPI clock O 4mA SPI2_SS_N Flash SPI active-low slave select 1 O 4mA SPI2_SS1_N Flash SPI active-low slave select 2 SPI2_SS2_N SPI2_SS3_N O 4mA Flash SPI active-low slave select 3 (1) O 4mA Flash SPI active-low slave select 4 (1) O 4mA 1. Only available in BGA package. Doc ID 14860 Rev 4 31/43 Digital I/O and memory interfaces STA680 I2C interfaces 5.6 The STA680 feature an I2C interfaces. For the relevant pin description see Table 13. Host and auxiliary I2C interface pin list Table 13. Pin name Designation Type Drive I/O 4mA Host Micro I2C interface serial clock line IIC1_SCL 2 IIC1_SDA Host Micro I C interface serial data line I/O 4mA IIC1_DA (1) Host Micro I2C interface data acknowledged IIC2_SCL 4mA I/O 4mA 2 I/O 4mA I/O 4mA Auxiliary I C interface serial clock line IIC2_SDA IIC2_DA I/O 2 Auxiliary I C interface serial data line (1) Auxiliary I 2C interface data acknowledged 1. Only available in BGA package. The data pin of the I2C interface is an open drain driver and it needs a resistive pull- up as required by Philip's IIC specification. Figure 12 shows timing diagrams and waveform for the two I2C interface. Figure 12. Timing diagrams and waveform for the two I2C interfaces Th,sta Th,sto Bit 1 IICx_SDA Ts,dat Bit n Bit 2 Thigh Th,dat IICx_SCL Stop Start 1/Fscl Tlow AC00719 In Table 14 the timing values for the I2C interfaces are reported. Table 14. I2C interface timing values Standard-mode Symbol 32/43 Fast-mode Parameter Unit Min. Max. Min. Max. - 100 - 400 kHz Fscl SCL clock frequency Tlow Low period of SCL clock 4.7 - 1.3 - s Thigh High period of SCL clock 4 - 0.6 - s Th, dat Data hold time 5 - - s Ts, dat Data setup time 250 - 100 - s Th, sta Hold time for start condition 4 - 0.6 - s Ts, sto Setup time for stop condition 4 - 0.6 - s Doc ID 14860 Rev 4 STA680 5.6.1 Digital I/O and memory interfaces Host micro I2C interface (I2C1) I2C1 is used to connect the STA680 to the host microcontroller to transmit commands, diagnostic information, and data. The I2C1 interface is a standard bi-directional I2C interface. The I2C1 interface supports 7-bit addressing and 8-bit data. It can run in both standard mode (serial clock frequency up to 100 kHz) and fast mode (up to 400 kHz). The I2C device addresses are reported in Table 15. An additional control line called IIC1_DA is provided as an extension of the I2C standard. This line is used as a flag to show the host controller that data is available and it can be polled by the host micro in either master or slave modes. Table 15. I2C1 interface device address I2C1 Primary address Secondary address Read Address 0101111b (0x2F) 0101101b (0x2D) Write Address 0101110b (0x2E) 0101100b (0x2C) Doc ID 14860 Rev 4 33/43 Digital I/O and memory interfaces 5.7 STA680 SDRAM interface The SDRAM interface supports up to 32M x 16 SDRAM; both standard and mobile protocols are accepted. For the relevant pin description see Table 16 Table 16. SDRAM Interface pin description Pin Name Designation Type Drive SDR_D[0:15] SDRAM interface data bus I/O 4 mA SDR_A[0:12] SDRAM interface address bus O 4 mA SDR_BA[0:1] Bank address O 4 mA SDR_CAS_N Active-low column address strobe O 8 mA SDR_RAS_N Active-low row address strobe O 8 mA SDR_WE_N Active-low write enable O 8 mA SDR_CS_N Active-low chip select O 8 mA SDR_DQM0 low-byte data input/output mask O 4 mA SDR_DQM1 high-byte data input/output mask O 4 mA Clock enable O 4 mA Clock to SDRAM for 3.3 V interface O 8 mA Feedback clock from SDRAM I 8 mA SDR_CKE SDR_CLK_RAM3V3 SDR_FEED_CLK The minimum required SDRAM size for single channel application is 64 Mbit while for a dual channel application at least 128 Mbit are needed. Figure 13 shows the timing diagrams and waveform for the SDRAM interface. Figure 13. Timing diagrams and waveform for the SDRAM interface Tck Tch SDR_CLK_RAM Tcl SDR_CLK_CS SDR_RAS SDR_CAS SDR_WE_N CAS latency = 3 SDR_BA BANK BANK BANK BANK SDR_A ROW COL ROW COL Tis Dout Din write Table 17 reports the timing values for the SDRAM interface 34/43 Tih Toh Tos SDR_D Doc ID 14860 Rev 4 read STA680 Table 17. Digital I/O and memory interfaces SDRAM interface timing values Symbol Parameter Tck Software application Condition Min. Max. Core in normal Full rate drive Half rate 7.35 - 12.05 - Core in overdrive Full rate 6.25 - Half rate 12.05 - SCL clock period Unit ns Tch CLK high level width - - 2.5 - ns Tcl CLK low level width - - 2.5 - ns Toh Data out hold time - - 0.9 - ns Tos Data out setup time - - 1.5 - ns Tis Data In setup time - - 0.8 - ns Tih Data In hold time - - 1.6 - ns Tt Transition time - - - 1.2 ns For power saving and reduced interference on the board, the SDRAM speed is programmed to work at half speed with respect to the internal data processing: Full Rate SW application: the SDRAM interface works at the same frequency as the internal data processing; Half Rate SW application: the SDRAM interface works at half frequency with respect to the internal data processing Doc ID 14860 Rev 4 35/43 Electrical specifications STA680 6 Electrical specifications 6.1 Absolute maximum ratings Table 18. Absolute maximum ratings Symbol Parameter VDD Test condition Min Typ Max Units Core supply voltage - - 1.47 - V VDD_GEN_IO Generic IO supply voltage - - 3.6 - V VDD_FSH_IO Flash IO supply voltage - - 3.6 - V VDD_RAM_IO SDRAM IO supply voltage - - 3.6 - V Osc 1V8 supply voltage - - 1.95 - V VDD_PLL_ANA PLL analog supply voltage - - 2.75 - V VDD_PLL_DIG PLL digital supply voltage - - 1.47 - V SAF core supply voltage - - 1.47 - V VDD_OSC VDD_SAF Vi Voltage on input pin - -0.5 - VDDIO+0. 5 V Vo Voltage on output pin - -0.5 - VDDIO+0. 5 V Tstg Storage temperature - -55 - 150 C Tamb Operative ambient temperature - -40 - 85 C VESD 6.2 ESD absolute minimum withstand voltage R = 1.5 k; C = 1.5 pF Human Body Model, BGA package >|1000| Charged device mode, BGA package >|500| V R = 1.5 k; C = 1.5 pF Human Body Model, LQFP package >|1000| Charged device mode, LQFP package >|450| Thermal data Table 19. Symbol Rth j-amb Thermal data Parameter Thermal resistance junction-to-ambient(1) 1. According to JEDEC specification on a 4 layers board. 36/43 Doc ID 14860 Rev 4 LQFP LFBGA Unit 43 37 C/W STA680 Electrical specifications 6.3 Operating conditions Table 20. DC electrical characteristics Symbol VDD Parameter Test condition Min. Typ. Max. Unit Normal drive 1.14 1.2 1.26 V Over drive 1.33 1.4 1.47 V Core supply voltage VDD_GEN_IO Generic IO supply voltage - 3.14 3.3 3.46 V VDD_FSH_IO Flash IO supply voltage - 3.14 3.3 3.46 V VDD_RAM_IO SDRAM IO supply voltage - 3.14 3.3 3.46 V - 1.71 1.8 1.89 V Oscillator analog supply voltage - 1.71 1.8 1.89 V VDD_PLL_ANA PLL analog supply voltage - 1.71 1.8 1.89 V PLL digital supply voltage Normal drive 1.14 1.2 1.26 V VDD_PLL_DIG Over drive 1.33 1.4 1.47 V Normal drive 1.14 1.2 1.26 V Over drive 1.33 1.4 1.47 V VDD_RAM_IO_ Supply for the SDRAM 1V8 clock at 1.8V VDD_OSC VDD_SAF SAF supply voltage I1V2 Current from 1.2V supply(1) I3V3 Current from 3.3V supply Pd(1) Power dissipation Tamb=25C VDD=1.20V - 90 - mA Tamb= 85C VDD=1.26V - - 149 mA Tamb=25C VDD_IO(2)=3.3V - 32 - mA Tamb= 85C VDD_IO=3.46V - - 41 mA Tamb=25C typical supply - 250 - mW Tamb=85C max supply - - 360 mW Iil Low level input leakage current(3) Vi = 0V - - 1.9 A Iih High level input leakage current(3) Vi = VDD_GEN_IO(4) - - 1.9 A Ilpu High level input leakage current on pull up(5) Vi = VDD_GEN_IO(4) - - 2.9 A Ilpd Low level input leakage current on pull-down(6) Vi = 0V - - 10 A Ipu Pull-up current Vi = 0V 20 - 72 A (4) Ipd Pull-down current Vi = VDD_GEN_IO 20 - 72 A Rpu Equivalent pull-up resistance(7) Vi = 0V 50 - 115 K Rpd Equivalent pull-down resistance(8) Vi = VDD_GEN_IO(4) 50 - 115 K Doc ID 14860 Rev 4 37/43 Electrical specifications Table 20. STA680 DC electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Vil Low level input voltage 3.3 supply mode -0.3 - 0.7 V Vih High level input voltage 3.3 supply mode 2.0 - VDD_G EN_IO +0.3 V Vhyst Input hysteresis voltage 3.3 supply mode 50 - - mV Voh Output high voltage Ioh =XmA(9) VDD_G EN_IO - 0.4V - - V Vol Output low voltage Iol =XmA(9) - - 0.3 V Ilatchup Injection current Maximum operating junction temperature 105 C 100 - - mA Iil_ram Low level input leakage current(3) Vi = 0V - - 4 A Iih_ram High level input leakage current(3) Vi = VDD_RAM_IO - - 4 A Ilpu_ram High level input leakage current on pull up(5) Vi = VDD_RAM_IO - - 4 A Ilpd_ram Low level input leakage current on pull-down(6) Vi = 0V - - - A Ipu_ram Pull-up current Vi = 0V 44 140 A Rpu_ram Equivalent pull-up resistance(7) Vi = 0V 25 - 87 k Vil_ram Low level input voltage - 0.8 - - V Vih_ram High level input voltage - - - 2 V 300 - 800 mV VDD_R AM_IO -0.4 - - V - - 0.3 V - - 100 mA - - 30 pF - - 30 pF - - 20 pF Vhyst_ram Schmitt trigger hysteresis - Voh_ram High level output voltage Ioh = -XmA(9) Vol_ram Low level output voltage Iol =XmA(9) Idc CL 38/43 3V3 to 1V8 DC regulator output current Output load for triple voltage pads (1.8V and 3.3V) 1.8V supply mode for 40 MHz 4mA buffer 3.3V supply 60 MHz mode (for both 4mA 75 MHz and 8mA) Doc ID 14860 Rev 4 STA680 Table 20. Symbol Electrical specifications DC electrical characteristics (continued) Parameter CL,3V3 Output load for 3.3V pads CL, DC DC regulator output load(10) Test condition Min. Typ. Max. Unit 4mA buffer 140MHz - - 10 pF 8mA buffer 140MHz - - 20 pF 2.2 - 4.7 F - 1. Current consumption and power dissipation measured for single channel software application running at 127MHz on core and 65MHz on SDRAM interface. This is the half rate commercial software release identified as STA680-5100056901800003-C0001.000.bin. 2. VDD_IO generally refers to the supply of the VDD_GEN_IO, VDD_FSH_IO and VDD_RAM_IO groups. 3. Performed on all the input pins excluded the pull-down and pull-up ones. 4. VDD_GEN_IO may be VDD_FHS_IO or VDD_GEN_IO depending on interface considered. 5. Performed only on the Input pins with pull up. 6. Performed only on the Input pins with pull down. 7. Guaranteed by Ipu measurements. 8. Guaranteed by Ipd measurements. 9. XmA = 4mA for a BD4, 8mA for BD8 pad type. 10. Dielectric=X7R ESRmax=100ohm, 2.2F +-5% or any above 3F+-10% but less than 4.7F+-10%.It is also recommended to distribute the 2.2F capacitance on the board by placing equivalent number of smaller capacitance value (for example, 470nF) near each VDD_REG1V8 supply pad. Doc ID 14860 Rev 4 39/43 Package information 7 STA680 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 14. LQFP144 (20x20mm) mechanical data and package dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.600 0.0630 0.150 0.0020 0.0059 A1 0.050 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 0.200 0.0035 17.500 0.0079 0.6890 E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 17.500 e L L1 k ccc 0.6890 0.500 0.450 0.600 OUTLINE AND MECHANICAL DATA MAX. 0.0197 0.750 0.0177 0.0236 0.0295 1.000 0.0394 LQFP144 (20x20x1.40mm) Low profile plastic Quad Flat Package 0(min.), 3.5(typ.), 7(max.) 0.080 0.0031 Note 1: Exact shape of each corner is optional. 0099183 C 40/43 Doc ID 14860 Rev 4 STA680 Package information Figure 15. LFBGA 168 balls (12x12x1.4 mm) mechanical data and package dimensions mm inch DIM. MIN. TYP. A A1 MAX. MIN. TYP. 1.400 0.210 A2 MAX. 0.0551 0.0083 0.200 A4 0.0078 0.800 0.350 D 11.850 12.000 12.150 0.4665 0.4724 0.4783 E 0.400 0.0315 b D1 OUTLINE AND MECHANICAL DATA 0.450 0.0138 0.0157 0.0177 10.400 0.4094 11.850 12.000 12.150 0.4665 0.4724 0.4783 E1 10.400 0.4094 e 0.800 0.0315 Z 0.800 0.0315 Body: 12 x 12 x 1.4mm ddd 0.100 0.0039 eee 0.150 0.0059 fff 0.080 0.0031 LFBGA 168 balls Low profile Fine Pitch Ball Grid Array 8123111 B Doc ID 14860 Rev 4 41/43 Revision history 8 STA680 Revision history Table 21. Document revision history Date Revision 25-Jul-2008 1 Initial release. 19-Dec-2008 2 Update ECOPACK(R) information in Section 7 on page 40. 3 Added Section 2: HD RadioTM system on page 7. Changed Table 2, 4, 7, 12, 13, 13, 17 and 20. Changed Figure 14, 15, 6, 3, 8 and 11. Add Figure 10: Crystal characteristics on page 26. 4 Document status promoted from preliminary data to datasheet. Modified Features. and Description on page 1. Modified the flow of the sections. Modified Section 1: Block diagram and pin description. Add Section 2: General description. Changed Figure 7: Power on timing and updated Table 4: Power on timing parameters. Modified Section 5.5: Serial peripheral interfaces (SPI). Updated Section 6: Electrical specifications. 31-Jul-2009 09-Nov-2010 42/43 Changes Doc ID 14860 Rev 4 STA680 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 14860 Rev 4 43/43