Detailed Description
PWM Controller
The MAX5098A dual DC-DC converter uses a
pulse-width-modulation (PWM) voltage-mode control
scheme. On each converter the device includes one inte-
grated n-channel MOSFET switch and requires an external
low-forward-drop Schottky diode for output rectification.
The controller generates the clock signal by dividing down
the internal oscillator (fCKO) or the SYNC input when
driven by an external clock, therefore each controller’s
switching frequency equals half the oscillator frequency
(fSW = fCKO/2) or half of the SYNC input frequency (fSW
= fSYNC/2). An internal transconductance error amplifier
produces an integrated error voltage at COMP_, providing
high DC accuracy. The voltage at COMP_ sets the duty
cycle using a PWM comparator and a ramp generator.
At each rising edge of the clock, converter 1’s MOSFET
switch turns on and remains on until either the appropriate
or maximum duty cycle is reached, or the maximum current
limit for the switch is reached. Converter 2 operates 180°
out-of-phase, so its MOSFET switch turns on at each fall-
ing edge of the clock.
In the case of buck operation (see the Typical Application
Circuit), the internal MOSFET is used in high-side config-
uration. During each MOSFET’s on-time, the associated
inductor current ramps up. During the second half of the
switching cycle, the high-side MOSFET turns off and forward
biases the Schottky rectifier. During this time, the SOURCE_
voltage is clamped to a diode drop (VD) below ground. A
low forward voltage drop (0.4V) Schottky diode must be
used to ensure the SOURCE_ voltage does not go below
-0.6V abs max. The inductor releases the stored energy
as its current ramps down, and provides current to the
output. The bootstrap capacitor is also recharged when the
SOURCE_ voltage goes low during the high-side MOSFET
off-time. The maximum duty-cycle limit ensures proper
bootstrap charging at startup or low input voltages. The
circuit goes in discontinuous conduction mode operation at
light load, when the inductor current completely discharges
before the next cycle commences. Under overload condi-
tions, when the inductor current exceeds the peak current
limit of the respective switch, the high-side MOSFET turns
off quickly and waits until the next clock cycle.
In the case of boost operation, the MOSFET is a low-
side switch (Figure 6). During each on-time, the induc-
tor current ramps up. During the second half of the
switching cycle, the low-side switch turns off and for-
ward biases the Schottky diode. During this time, the
DRAIN_ voltage is clamped to a diode drop (VD) above
VOUT_ and the inductor provides energy to the output
as well as replenishes the output capacitor charge.
ON/OFF
The MAX5098A provides an input (ON/OFF) to turn on and
off the external load-dump protection MOSFET. Drive ON/
OFF high for normal operation. Drive ON/OFF low to turn
off the external n-channel load-dump protection MOSFET
and reduce the supply current to 7µA (typ). When ON/OFF
is driven low, the converter also turns off, and the PGOOD_
outputs are driven low. V+ will be self discharged through
the converters output currents and the IC supply current.
Internal Oscillator/Out-of-Phase Operation
The internal oscillator generates the 180° out-of-phase
clock signal required by each regulator. The switching
frequency of each converter (fSW) is programmable from
200kHz to 2.2MHz using a single 1% resistor at ROSC. See
the Setting the Switching Frequency section.
With dual synchronized out-of-phase operation, the
MAX5098A’s internal MOSFETs turn on 180° out-of-phase.
The instantaneous input current peaks of both regulators
do not overlap, resulting in reduced RMS ripple current and
input-voltage ripple. This reduces the required input capac-
itor ripple current rating, allows for fewer or less expensive
capacitors, and reduces shielding requirements for EMI.
Synchronization (SYNC)/
Clock Output (CKO)
The main oscillator can be synchronized to the system
clock by applying an external clock (fSYNC) at SYNC. The
fSYNC frequency must be twice the required operating
frequency of an individual converter. Use a TTL logic sig-
nal for the external clock with at least 100ns pulse width.
ROSC is still required when using external synchronization.
Program the internal oscillator frequency to have fSW = 1/2
fSYNC. The device is properly synchronized if the SYNC
frequency, fSYNC, varies within ±20%.
Two MAX5098As can be connected in the master-slave
configuration for four ripple-phase operation (Figure 1).
The MAX5098A provides a clock output (CKO) that is 45°
phase-shifted with respect to the internal switch turn-on
edge. Feed the CKO of the master to the SYNC input of the
slave. The effective input ripple switching frequency is four
times the individual converter’s switching frequency. When
driving the master converter using an external clock at
SYNC, set the fSYNC clock duty cycle to 50% for effective
90° phase-shifted interleaved operation. When a SYNC is
applied (and FSEL_1 = 0), converter 1 duty cycle is limited
to 75% (max).
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14
MAX5098A Dual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection