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SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER ICS308

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 1

ICS308 REV J 120507

Description

The ICS308 is a versatile serially progra mma ble, qua d

PLL clock source. The ICS308 can generate any

frequency from 250 kHz to 200 MHz, and up to 6

different output frequencies simultaneously. The

outputs can be reprogrammed on the fly, and will lock to

a new frequency in 10 ms or less. Smooth transitions

(in which the clock duty cycle remains roughly 50%) are

guaranteed if the output divider is not changed.

The device includes a PDTS pin which tri-states the

output clocks and powers down the entire chip.

The ICS308 default for non-programmed start-up are

buff ered reference clock outputs on all clock output

pins.

Features

•Packaged in 20-pin SSOP (QSOP)

•Available in Pb (lead) free package

•Operating voltage of 3.3 V

•Highly accurate frequency generation

•M/N Multiplier PLL: M = 1..2048, N = 1..1024

•Serially programmable: user determines the output

frequency via a 3-wir e inte rface

•Eliminates need for custom quartz oscillators

•Input crystal frequency of 5 - 27 MHz

•Optional programmable on-chip crystal capacitors

•Output clock frequencies up to 200 MHz

•Reference clock output

•Power down tri-state mode

•Very low jitter

Block Diagram

Crystal

Oscillator

GND 2

VDD

PDTS

PLL2

PLL3

Divide

Logic

and

Output

Enable

Control

SCLK

DATA

CLK1

CLK9

CLK8

CLK7

CLK6

CLK5

CLK4

CLK3

CLK2

PLL4

PLL1

Crystal or

clock input

External capacitors are

required with a crystal input.

X1/ICLK

STROBE

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 2

ICS308 REV J 120507

Pin Assignment

Pin Descriptions

DATA STROBE

X1/ICLK

SCLK

CLK9

PDTS

VDD

GND

VDD

GND

CLK1 CLK5

CLK2 CLK6

CLK3 CLK7

CLK4 CLK8

20 pin (150 mil) SSOP (QSOP)

Number Pin

Name Pin

Type Pin Description

1 DATA Input Serial data input.

2 X2 XO Crystal Output. Connect this pin to a crystal. Float for clock input.

3 X1/ICLK XI Connect this pin to a crystal or external clock input.

4 CLK9 Output Output clock 9. Default of Reference frequency output when unprogrammed.

5 VDD Power Connect to +3.3 V.

6 GND Power Connect to Ground.

7 CLK1 Output Output clock 1. Default of Reference frequency output when unprogrammed.

8 CLK2 Output Output clock 2. Default of Reference frequency output when unprogrammed.

9 CLK3 Output Output clock 3. Default of Reference frequency output when unprogrammed.

10 CLK4 Output Output clock 4. Default of Reference frequency output when unprogrammed.

11 CLK8 Output Output clock 8. Default of Reference frequency output when unprogrammed.

12 CLK7 Output Output clock 7. Default of Reference frequency output when unprogrammed.

13 CLK6 Output Output clock 6. Default of Reference frequency output when unprogrammed.

14 CLK5 Output Output clock 5. Default of Reference frequency output when unprogrammed.

15 GND Power Connect to Ground.

16 VDD Power Connect to +3.3 V.

17 VDD Power Connect to +3.3 V.

18 PDTS Input Powers down entire chip, tri-states all outputs when low. Internal pull-up.

19 SCLK Input Serial Shift register clock. See timing diagram.

20 STROBE Input Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 3

ICS308 REV J 120507

Configuring the ICS308

Initial State: The ICS308 may be configured to have up to nine frequency outputs, utilizing the four

on-board PLLs. Unprogrammed, the pa rt has the following ou tpu ts, related to th e re ference input clock:

The STR OBE pin must have an external 250 kOhm pull-up resistor to achieve the Initial State.

The input crystal range for the ICS308 is 5 MHz to 27 MHz.

The ICS308 can be programmed to set the output functions and frequencies. 160 data bits generated by

the VersaClockTM software are written in DATA pin in this order: MSB (left most bit) first.

As show in Figure 2, after these 160 bits are clocked into the ICS308, taking STROBE high will send this

data to the internal hatch and the CLK output will lock within 10 ms.

Note: STROBE utilizes a transparent latch that is latched when in the high state. If STR OBE is in the high

state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will

change accordingly. Although this will not damage the ICS308, it is recommended that STROBE be kept

low while D ATA is being clock ed into the ICS308 in order to av oid unintended chang es on the output cloc ks.

All outputs may be turned off during initialization by bringing the PDTS pin to Ground. When PDTS is

brought high, after the Strobe pin in brought high, the programmed output frequencies will be available.

AC Parameters for Writing to the ICS308

Default Outputs

Output Frequency

Clock 1-9 (Pins 4, 10 - 14) Reference Output

Parameter Condition Min. Max. Units

tSETUP Setup time 10 ns

tHOLD Hold time after SCLK 10 ns

tWData wait time 10 ns

tSStrobe pulse width 40 ns

SCLK Frequency 30 MHz

DATA

thold

tsetup

SCLK

STROBE

Figure 2. Tim ing D iagram for Program m ing the ICS308

Bit160 Bit2 Bit1

Bit3

Bit159 Bit158

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 4

ICS308 REV J 120507

External Components

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50Ω tr ace (a

commonly used tr ace impedance), place a 33 Ω resistor

in series with the cloc k line, as close to the cloc k output

pin as possible. The nominal impedance of the clock

output is 20Ω.

STROBE Pull-up Resistor

In order for the device to start up in the default state , a

250 kOhm pull-up re sist or is requ ire d .

Decoupling Capacitors

As with any high-performance mixed-signal IC, the

ICS308 must be isolated from system power supply

noise to perform optimally.

Decoupling capacitors of 0.01µF must be connected

between each VDD and th e PCB ground pla ne.

Crystal Load Capacitors

The de vice crystal connections should include pads f or

small capacitors from X1 to ground and from X2 to

ground. These capacitors are used to adjust the stray

capacitance of the bo ard to match the nominally

required crystal load capacitance. Because load

capacitance can only be increased in this trimming

process, it is important to keep stray capacitance to a

minimum b y using very short PCB traces (and no vias)

between the crystal and device. Crystal capacitors must

be connected from each of the pins X1 and X2 to

ground.

The value (in pF) of these crystal caps should equal (CL

-6 pF)*2. In this equat ion, CL= crystal load capacitance

in pF. Example: For a crystal with a 16 pF load

capacitance, each crystal capacitor would be 20 pF

[(16-6) x 2 = 20].

PCB Layout Recommendations

For optimum device performance and low est output

phase noise, the following guidelines should be

observed.

1) Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible. No vias should be used

between decoupling capacitor and VDD pin. The PCB

trace to VDD pin should be kept as short as possible, as

should the PCB trace to the ground via.

2) The external crystal should be mounted just next to

the device with short traces. The X1 and X2 tr aces

should not be rout ed next to each other with minimum

spaces, instead they should be sep arate d an d away

from other traces.

3) To minimize EMI, the 33Ω series termination resistor

(if needed) should be placed close to each cloc k output.

4) An optim um lay out is one with all components on the

same side of the board, minimizing vias through other

signal layers.

ICS308 Configuration Capabilities

The architecture o f the ICS308 allows the user to easily

configure the device to a wide range of output

frequencies, for a given input reference frequency.

The frequency m ultiplier PLL pro vides a h igh degree of

precision. The M/N values (the mu ltiplier/divide values

av ailable to generate the target VCO frequency) can be

set within the r ange of M = 1 to 2048 and N = 1 to 1024.

The ICS308 also provides separate output divide

va lues, fr om 2 through 20, to allow the t wo output cloc k

banks to support widely diff ering frequency values from

the same PLL.

Each output frequency can be represented as:

Output Freq. = (Ref. Freq)*(M/N)/Output Divide

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 5

ICS308 REV J 120507

VersaClock Software

IDT applies y ears of PLL optimi zation e xperience into a user f riendly software that accepts the user’s target

reference clock and output frequencies and generates the lowest jitter, lowest power configuratio n, with

only a press of a button. The user does not need to have prior PLL experience or determine the optimal

VCO frequency to support multiple output frequencies.

VersaCloc k software quic kly ev aluates accessib le VCO frequencies with av ailab le output divide v alues and

provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate

output accuracy, performance trade-off scenarios in seconds.

Absolute Maximum Ratings

Stresses abo ve the r atings listed below can cause permanent damage t o the ICS308. These ra tings, which

are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only o ver the recommended operating

temperature range.

Recommended Operation Conditions

Parameter Item Min. Typ. Max. Units

Supply Voltage, VDD Referenced to GND 7 V

Inputs Referenced to GND -0.5 VDD+ 0.5 V

Clock Outputs Referenced to GND -0.5 VDD+ 0.5 V

Storage Temperature -65 150 °C

Soldering Temperature Max 10 seconds 260 °C

Parameter Min. Typ. Max. Units

Ambient Operating Temperature (ICS308R) 0 +70 °C

Ambient Operating Temperature (ICS308RI) -40 +85 °C

Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V

Power Supply Ramp Time 4 ms

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 6

ICS308 REV J 120507

DC Electrical Characteristics

VDD=3.3 V ±10%, Ambient temperature -40 to +85°C, unless stated otherwise

Parameter Symbol Conditions Min. Typ. Max. Units

Operating Voltage VDD 3.00 3.60 V

Operating Supply Current

Input High Voltage IDD Configuration

Dependent mA

Ex. 25 MHz crystal,

VDD=3.3 V, No load, 25 mA

PDTS = 0 20 µA

Input High Voltage VIH X1/ICLK only (VDD/2)+1 V

Input Low Voltage VIL X1/ICLK only (VDD/2)-1 V

Input High Voltage VIH VDD-0.5 V

Input Low Voltage VIL PDTS, SRCLOCK,

DATA, STROBE 0.8 V

Output High Voltage VOH IOH = -8 mA 2.4 V

Output Low Voltage VOL IOL = 8 mA 0.4 V

Output High Voltage,

CMOS level VOH IOH = -4 mA VDD-0.4 V

Short Circuit Current CLK outputs +70 mA

Input Capacitance CIN PDTS pin 4 pF

Internal Pull-down

Resistor RPD CLK outputs 525 kΩ

Internal Pull-up Resistor RPU PDTS pin 250 kΩ

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 7

ICS308 REV J 120507

AC Electrical Characteristics

VDD = 3.3 V±10%, Ambient Temp er at ur e -40 to +85° C, unless stated otherwise

Note 1: Measured with 15 pF load.

Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%

Thermal Characteristics

Parameter Symbol Conditions Min. Typ. Max. Units

Input Frequency FIN Fundamental crystal 5 27 MHz

Input Clock 2 50 MHz

Output Frequency VDD=3.3 V 0.25 200 MHz

Output Clock Rise Time tOR 20% to 80%, Note 1 0.8 ns

Output Clock Fall Time tOF 80% to 20%, No te 1 0.8 ns

Output Clock Duty Cycle Note 2 40 49-51 60 %

P ower -up Time STR OBE goes high until

stable CLK out 310ms

PDTS goes high until

stable CLK out .2 2 ms

Maximum Output Jitter, short term tjReference Clock ±300 ps

Maximum Output Jitter, short term tjAll other clocks,

CL=15 pF, configuration

dependent

±200 ps

Pin-to-Pin Skew Low Skew Outputs -250 250 ps

Parameter Symbol Conditions Min. Typ. Max. Units

Thermal Resistance Junction to

Ambient θJA Still air 135 °C/W

θJA 1 m/s air flow 93 °C/W

θJA 3 m/s air flow 78 °C/W

Thermal Resistance Junction to Case θJC 60 °C/W

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 8

ICS308 REV J 120507

Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body)

Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been check ed for both accuracy and reliability, Integrated Device Technology (IDT)

assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result

from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

applications. Any other applications such as those requiring extended temperature range, high reliability, or other e x traordinary

environmental requirements are not recommended withou t additional processing by IDT. IDT reserves the right to change any

circuitr y or specifications without notice. IDT does not authorize or warrant any IDT product fo r use in life support de vices or

critical medical instruments.

Part / Order Number Marking Shipping Packaging Package Temperature

ICS308R ICS308R Tubes 20-pin SSOP 0 to +70° C

ICS308RT Tape and Reel 20-pin SSOP 0 to +70° C

ICS308RI ICS308RI Tubes 20-pin SSOP -40 to +85° C

ICS308RIT Tape and Reel 20-pin SSOP -40 to +85° C

ICS308RLF 308RLF Tubes 20-pin SSOP 0 to +70° C

ICS308RLFT Tape and Reel 20-pin SSOP 0 to +70° C

ICS308RILF 308RILF Tubes 20-pin SSOP -40 to +85° C

ICS308RILFT Tape and Reel 20-pin SSOP -40 to +85° C

INDEX

AREA

1 2

E1 E

SEATING

PLANE

- C -

aaa C

*For reference only. Controlling dimensions in mm.

Millimeters Inches*

Symbol Min Max Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 -- 1.50 -- 0.059

b 0.20 0.30 0.008 0.012

c 0.18 0.25 0.007 0.010

D 8.55 8.75 0.337 0.344

E 5.80 6.20 0.228 0.244

E1 3.80 4.00 0.150 0.157

e .635 Basic .025 Basic

L 0.40 1.27 0.016 0.050

α0°8°0°8°

aaa -- 0.10 -- 0.004

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ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER