NC No internal connection–
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN
1IN+
GND
NC
1SHDN
NC
VDD+
2OUT
2IN
2IN+
NC
2SHDN
NC
(TOP VIEW)
TLV2463
D OR PW PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN
1IN+
VDD+
2IN+
2IN
2OUT
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
(TOP VIEW)
TLV2464
D OR PW PACKAGE
1
2
3
4
8
7
6
5
1OUT
1IN
1IN +
GND
VDD+
2OUT
2IN
2IN+
TLV2462
D, DGK, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN
IN +
GND
NC
VDD+
OUT
NC
TLV2461
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN
IN +
GND
SHDN
VDD+
OUT
NC
TLV2460
D OR PW PACKAGE
(TOP VIEW)
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS
WITH SHUTDOWN
Check for
Samples: TLV2460-Q1,TLV2461-Q1,TLV2462-Q1,TLV2463-Q1,TLV2464-Q1,TLV2460A-Q1,TLV2461A-Q1,TLV2462A-Q1,TLV2463A-
Q1,TLV2464A-Q1
1FEATURES
• Qualified for Automotive Applications • Supply Current . . . 500 mA/Channel
• ESD Protection Exceeds 2000 V Per • Input Offset Voltage . . . 100 mV
MIL-STD-883, Method 3015; Exceeds 200 V • Input Noise Voltage . . . 11 nV/√Hz
Using Machine Model (C = 200 pF, R = 0) • Slew Rate . . . 1.6 V/ms
• Rail-to-Rail Output Swing • Micropower Shutdown Mode
• Gain Bandwidth Product . . . 6.4 MHz (TLV2460/TLV2463) . . . 0.3 mA/Channel
• ±80-mA Output Drive Capability • Universal Operational Amplifier EVM
DESCRIPTION
The devices in the TLV246x family of low-power rail-to-rail input/output operational amplifiers are specifically
designed for portable applications. The input common-mode voltage range extends beyond the supply rails for
maximum dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with
high-output-drive capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers.
This rail-to-rail dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital
converters.
The operational amplifier has 6.4-MHz bandwidth and 1.6-V/ms slew rate with only 500-mA supply current,
providing good ac performance with low power consumption. Devices are available with an optional shutdown
terminal, which places the amplifier in an ultralow supply-current mode (IDD = 0.3 mA/channel). While in
shutdown, the operational amplifier output is placed in a high-impedance state. DC applications are also well
served with an input noise voltage of 11 nV/√Hz and input offset voltage of 100 mV.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
ORDERING INFORMATION(1)
VIOmax ORDERABLE PART
TAPACKAGE(2) TOP-SIDE MARKING
AT 25�C NUMBER
TLV2460QDRQ1 2460Q1
TLV2461QDRQ1 2461Q1
SOP −D Reel of 2500 TLV2462QDRQ1 2462Q1
TLV2463QDRQ1 2463Q1
TLV2464QDRQ1(3) 2464Q1
2000 mV TLV2460QPWRQ1 2460Q1
TLV2461QPWRQ1 2461Q1
TSSOP −PW Reel of 2000 TLV2462QPWRQ1 2462Q1
TLV2463QPWRQ1 2463Q1
TLV2464QPWRQ1(3) 2464Q1
–40°C to 125°C MSOP −DGK Reel of 2500 TLV2462QDGKRQ1 QVM
TLV2460AQDRQ1 2460AQ
TLV2461AQDRQ1 2461AQ
SOP −D Reel of 2500 TLV2462AQDRQ1 2462AQ
TLV2463AQDRQ1 TLV2463AQ1
TLV2464AQDRQ1(3) 2464AQ
1500 mVTLV2460AQPWRQ1 2460AQ
TLV2461AQPWRQ1 2461AQ
TSSOP −PW Reel of 2000 TLV2462AQPWRQ1 2462AQ
TLV2463AQPWRQ1 2463AQ
TLV2464AQPWRQ1 2464AQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Product Preview
2Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VDD Supply voltage(2) 6 V
VID Differential input voltage range –0.2 V to VDD + 0.2 V
IIInput current (any input) ±200 mA
IOOutput current ±175 mA
IITotal input current (into VDD+) 175 mA
IOTotal output current (out of GND) 175 mA
TAOperating free-air temperature range –40°C to 125°C
TJMaximum junction temperature 150°C
D (8 pin) 176°C/W
D (14 pin) 123°C/W
qJA Thermal impedance, junction to ambient(3) PW (8 pin) 259°C/W
PW (14 pin) 174°C/W
DGK (8 pin) 242°C/W
Tstg Storage temperature range –65°C to 150°C
Latch-Up performance meets 100 mA per AEC-Q100 ( Class I ) Class I
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND.
(3) Package thermal impedance is calculated in accordance with JESD 51-5.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Single supply 2.7 6
VDD Supply voltage V
Split supply ±1.35 ±3
VICR Common-mode input voltage range –0.2 VDD + 0.2 V
TAOperating free-air temperature –40 125 °C
VIH 2
Shutdown on/off voltage level(1) V
VIL 0.7
(1) Relative to voltage on the GND terminal of the device
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
25°C 100 2000
VDD = 3 V, TLV246x Full range 2200
VIC = 1.5 V,
VIO Input offset voltage mV
VO= 1.5 V, 25°C 150 1500
TLV246xA
RS= 50 ΩFull range 1700
Temperature coefficient of VDD = 3 V, VIC = 1.5 V,
aVIO 2mV/°C
input offset voltage VO= 1.5 V, RS= 50 Ω
25°C 2.8 7
VDD = 3 V, VIC = 1.5 V,
IIO Input offset current pA
VO= 1.5 V, RS= 50 ΩFull range 75
25°C 4.4 14
IIB Input bias current VIC = 1.5 V, VO= 1.5 V, RS= 50 ΩpA
Full range 75
25°C 2.9
IO= –2.5 mA Full range 2.8
VOH High-level output voltage V
25°C 2.7
IO= –10 mA Full range 2.5
25°C 0.1
VIC = 1.5 V, IOL = 2.5 mA Full range 0.2
VOL Low-level output voltage V
25°C 0.3
VIC = 1.5 V, IOL = 10 mA Full range 0.5
25°C 50
Sourcing Full range 20
IOS Short circuit output current mA
25°C 40
Sinking Full range 20
IOOutput current Measured 1 V from rail 25°C ±40 mA
25°C 90 105
Large-signal differential
AVD RL= 10 kΩdB
voltage amplification Full range 89
ri(d) Differential input resistance 25°C 109Ω
Common-mode input
ci(o) f = 10 kHz 25°C 7 pF
capacitance
Closed-loop output
zof = 100 kHz, AV= 10 25°C 33 Ω
impedance 25°C 66 80
Common-mode rejection
CMRR VICR = 0 V to 3 V, RS= 50 ΩdB
ratio Full range 60
25°C 80 85
VDD = 2.7 V to 6 V, VIC = VDD/2, No load Full range 75
Supply-voltage rejection
kSVR dB
ratio (ΔVDD±/ΔVIO)25°C 85 95
VDD = 3 V to 5 V, VIC = VDD/2, No load Full range 80
25°C 0.5 0.575
Supply current
IDD VO= 1.5 V, No load mA
(per channel) Full range 0.9
25°C 0.3
Supply current in shutdown
IDD(SHDN) SHDN < 0.7 V, Per channel in shutdown mA
(TLV2460, TLV2463) Full range 2.5
(1) Full range is –40°C to 125°C.
4Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
OPERATING CHARACTERISTICS
VDD = 3 V, at specified free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
25°C 1 1.6
SR Slew rate at unity gain VO(PP) = 2 V, CL= 160 pF, RL= 10 kΩV/ms
Full range 0.8
f = 100 Hz 16
VnEquivalent input noise voltage 25°C nV/√Hz
f = 1 kHz 11
InEquivalent input noise current f = 1 kHz 25°C 0.13 pA/√Hz
AV= 1 0.006
Total harmonic distortion VO(PP) = 2 V,
THD+N AV= 10 25°C 0.02 %
plus noise RL= 10 kΩ, f = 1 kHz AV= 100 0.08
Both channels 7.6
Channel 1
t(on) Amplifier turn-on time AV= 1, RL= 10 kΩ25°C ms
only, 7.65
Channel 2 on
Both channels 333
Channel 1
only, 328
t(off) Amplifier turn-off time AV= 1, RL= 10 kΩChannel 2 on 25°C ns
Channel 2
only, 329
Channel 1 on
Gain-bandwidth product f = 10 kHz, CL= 160 pF, RL= 10 kΩ25°C 5.2 MHz
V(STEP)PP = 2 V, 0.1% 1.47
AV= –1, CL= 10 pF, 0.01% 1.78
RL= 10 kΩ
tsSettling time 25°C ms
V(STEP)PP = 2 V, 0.1% 1.77
AV= –1, CL= 56 pF, 0.01% 1.98
RL= 10 kΩ
fmPhase margin at unity gain RL= 10 kΩ, CL= 160 pF 25°C 44 °
Gain margin RL= 10 kΩ, CL= 160 pF 25°C 7 dB
(1) Full range is –40°C to 125°C.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
25°C 150 2000
VDD = 5 V, TLV246x Full range 2200
VIC = 2.5 V,
VIO Input offset voltage mV
VO= 2.5 V, 25°C 150 1500
TLV246xA
RS= 50 ΩFull range 1700
Temperature coefficient of VDD = 5 V, VIC = 2.5 V,
aVIO 2mV/°C
input offset voltage VO= 2.5 V, RS= 50 Ω
25°C 0.3 7
VDD = 5 V, VIC = 2.5 V,
IIO Input offset current pA
VO= 2.5 V, RS= 50 ΩFull range 60
25°C 1.3 14
VDD = 5 V, VIC = 2.5 V,
IIB Input bias current pA
VO= 2.5 V, RS= 50 ΩFull range 60
25°C 4.9
IO= –2.5 mA Full range 4.8
25°C 4.8
VOH High-level output voltage TLV246x,TLV246xA V
Full range 4.7
IO= –10 mA 25°C 4.8
TLV2462QDGKRQ1 Full range 4.4
25°C 0.1
VIC = 2.5 V, IOL = 2.5 mA Full range 0.2
VOL Low-level output voltage V
25°C 0.2
VIC = 2.5 V, IOL = 10 mA Full range 0.3
25°C 145
Sourcing Full range 60
IOS Short circuit output current mA
25°C 100
Sinking Full range 60
IOOutput current Measured 1 V from rail 25°C ±80 mA
25°C 92 109
Large-signal differential VIC = 2.5 V, RL= 10 kΩ,
AVD dB
voltage amplification VO= 1 V to 4 V Full range 90
Differential input
ri(d) 25°C 109Ω
resistance
Common-mode input
ci(o) f = 10 kHz 25°C 7 pF
capacitance
Closed-loop output
zof = 100 kHz, AV= 10 25°C 29 Ω
impedance 25°C 71 85
Common-mode rejection
CMRR VICR = 0 V to 5 V, RS= 50 ΩdB
ratio Full range 60
25°C 80 85
VDD = 2.7 V to 6 V, VIC = VDD/2, No load Full range 75
Supply-voltage rejection
kSVR dB
ratio (ΔVDD±/ΔVIO)25°C 85 95
VDD = 3 V to 5 V, VIC = VDD/2, No load Full range 80
25°C 0.55 0.65
Supply current
IDD VO= 2.5 V, No load mA
(per channel) Full range 1
Supply current in 25°C 1
IDD(SHD shutdown SHDN < 0.7 V, Per channel in shutdown mA
N) Full range 3
(TLV2460, TLV2463)
(1) Full range is –40°C to 125°C.
6Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
OPERATING CHARACTERISTICS
VDD = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
25°C 1 1.6
SR Slew rate at unity gain VO(PP) = 2 V, CL= 160 pF, RL= 10 kΩV/ms
Full range 0.8
f = 100 Hz 14
VnEquivalent input noise voltage 25°C nV/√Hz
f = 1 kHz 11
InEquivalent input noise current f = 100 Hz 25°C 0.13 pA/√Hz
AV= 1 0.004
Total harmonic distortion VO(PP) = 4 V,
THD+N AV= 10 25°C 0.01 %
plus noise RL= 10 kΩ, f = 10 kHz AV= 100 0.04
Both channels 7.6
Channel 1
only, 7.65
t(on) Amplifier turn-on time AV= 1, RL= 10 kΩChannel 2 on 25°C ms
Channel 2
only, 7.25
Channel 1 on
Both channels 333
Channel 1
only, 328
t(off) Amplifier turn-off time AV= 1, RL= 10 kΩChannel 2 on 25°C ns
Channel 2
only, 329
Channel 1 on
Gain-bandwidth product f = 10 kHz, CL= 160 pF, RL= 10 kΩ25°C 6.4 MHz
V(STEP)PP = 2 V, 0.1% 1.53
AV= –1, CL= 10 pF, 0.01% 1.83
RL= 10 kΩ
tsSettling time 25°C ms
V(STEP)PP = 2 V, 0.1% 3.13
AV= –1, CL= 56 pF, 0.01% 3.33
RL= 10 kΩ
fmPhase margin at unity gain RL= 10 kΩ, CL= 160 pF 25°C 45 °
Gain margin RL= 10 kΩ, CL= 160 pF 25°C 7 dB
(1) Full range is –40°C to 125°C.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs FIGURE
VIO Input offset voltage vs Common-mode input voltage 1,2
IIB Input bias current vs Free-air temperature 3,4
IIO Input offset current vs Free-air temperature 3,4
VOH High-level output voltage vs High-level output current 5,6
VOL Low-level output voltage vs Low-level output current 7,8
VO(PP) Maximum peak-to-peak output voltage vs Frequency 9,10
Open-loop gain vs Frequency 11,12
Phase vs Frequency 11,12
AVD Differential voltage amplification vs Load resistance 13
Capacitive load vs Load resistance 14
zoOutput impedance vs Frequency 15,16
CMRR Common-mode rejection ratio vs Frequency 17
kSVR Supply-voltage rejection ratio vs Frequency 18,19
vs Supply voltage 20
IDD Supply current vs Free-air temperature 21
Amplifier turnon characteristics 22
Amplifier turnoff characteristics 23
Supply current turnon 24
Supply current turnoff 25
Shutdown supply current vs Free-air temperature 26
SR Slew rate vs Load capacitance 27
vs Frequency 28,29
VnEquivalent input noise voltage vs Common-mode input voltage 30,31
THD Total harmonic distortion vs Frequency 32,33
THD + N Total harmonic distortion plus noise vs Peak-to-peak signal amplitude 34,35
vs Frequency 11,12
fmPhase margin vs Load capacitance 36
vs Free-air temperature 37
vs Supply voltage 38
Gain-bandwidth product vs Free-air temperature 39
Large signal follower 40,41
Small signal follower 42,43
Inverting large signal 44,45
Inverting small signal 46,47
8Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
Common-Mode Input Voltage, (V)VICR
Input Offset Voltage, V (mV)
IO
0.2
0.6
1
0
0.4
0.8
1
21 3 50 4
VDD = 5 V
TA= 25°C
0.4
0.6
0.2
0.8
0.2
0.6
1
0
0.4
0.8
1
Common-Mode Input Voltage, (V)VICR
1
0.50
VDD = 3 V
TA= 25°C
Input Offset Voltage, V (mV)
IO
0.4
0.6
0.2
1.5 22.5 3
Input Bias and Input Offset Current, I and I ( )
IB IO nA
1
3
2
1
0
4
5
IIB
IIO
VDD = 5 V
VI= 2.5 V
6
Free-Air Temperature (, T C)
A
°
–55 –35–15
525 45 65 85 105 125
2.5
1.5
0.5
0.5
3
2
1
0
4.5
3.5
4
VDD = 3 V
VI= 1.5 V
Input Bias and Input Offset Current, I and I ( )
IB IO nA
5
IIB
IIO
Free-Air Temperature (, T C)
A
°
–55 –35–15
525 45 65 85 105 125
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE
vs vs
COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE
Figure 1. Figure 2.
INPUT BIAS AND INPUT OFFSET CURRENT INPUT BIAS AND INPUT OFFSET CURRENT
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 3. Figure 4.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TA= 125°C
TA= 85°C
0 5010 20 30 40 60 70 80
2.5
1
0
2
1.5
0.5
3
VDD = 3 VDC
TA= 55 °C
TA= 25°C
TA= 40 °C
High-Level Output Current, I (mA)
OH
High-Level Output Voltage, V (V)
OH
0 14010020 12040 60 160 180 20080
High-Level Output Current, I (mA)
OH
High-Level Output Voltage, V (V)
OH
TA= 125°C
TA= 85°C
2.5
1
0
2
1.5
0.5
3
VDD = 5 VDC
TA= 55 °C
4
5
4.5
3.5
TA= 25°C
TA= 40 °C
0 1004020 120 140 16060 80
Low-Level Output Voltage, V (V)
OL
2.5
1
0
2
1.5
0.5
3
VDD = 5 VDC
4.5
4
3.5
TA= 55 °C
TA= 85°C
TA= 125°C
TA= 25°C
TA= 40 °C
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 5. Figure 6.
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 7. Figure 8.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
10k 100k
Frequency, f (Hz)
1M 10M
3
2
1
0
2.5
1.5
0.5
Peak-to-Peak Output Voltage, V (V)
O(PP)
VDD = 3 V
AV= 10
THD = 1%
RL= 10 kΩ
Frequency, f (Hz)
10M
Peak-to-Peak Output Voltage, V (V)
O(PP)
10k 100k 1M
3
2
1
0
2.5
1.5
0.5
VDD = 5 V
AV= 10
THD = 1%
RL= 10 kΩ
3.5
5
4
5.5
4.5
Frequency, f (Hz)
40
20
0
–20
100 10k
50
30
10
–10
1k
60
80
10
70
90
140 °
200 °
120 °
100 °
80°
100
60°
40°
20°
0°
20°
40°
180 °
160 °
Open-Loop Gain (dB)
Phase
AVD
Phase
VDD =±1.5 V
RL= 10 kΩ
CL= 0
TA= 25°C
100k 1M 10M
140°
200°
120°
100°
80°
60°
40°
20°
0°
20°
40°
180°
160°
Phase
AVD
Phase
VDD =±2.5 V
RL= 10 kΩ
CL= 0
TA= 25°C
40
20
0
–20
50
30
10
–10
60
80
70
90
100
Open-Loop Gain (dB)
Frequency, f (Hz)
100 10k
1k
10 100k 1M 10M
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
PEAK-TO-PEAK OUTPUT VOLTAGE PEAK-TO-PEAK OUTPUT VOLTAGE
vs vs
FREQUENCY FREQUENCY
Figure 9. Figure 10.
OPEN-LOOP GAIN AND PHASE OPEN-LOOP GAIN AND PHASE
vs vs
FREQUENCY FREQUENCY
Figure 11. Figure 12.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
10000
100
1000
Phase Margin > 30°
VDD = 5 V
Phase Margin = 30°
TA= 25°C
Phase Margin < 30°
Capacitance, C (pF)
L
Load Resistance, R ( )
LΩ
10
100 10k
1k
120
80
40
0
140
100
60
20
180
160
TA= 25°C
Differential Voltage Amplification, A (V/mV)
VD
VDD =±2.5 V
VDD =±1.5 V
Load Resistance, R ( )
LΩ
100
1k 100k 1M
10k
1
0.1
0.01
10
1000
AV= 100
VDD =±1.5 V
TA= 25°C
AV= 10
AV= 1
Output Impedance, Z ( )
OΩ
Frequency, f (Hz)
100
100
1k 100k 1M 10M10k
1
0.1
0.01
10
1000
AV= 100
Output Impedance, Z ( )
OΩ
VDD =±2.5 V
TA= 25°C
AV= 10
AV= 1
Frequency, f (Hz)
100
100
1k 100k 1M 10M10k
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
DIFFERENTIAL VOLTAGE AMPLIFICATION CAPACITIVE LOAD
vs vs
LOAD RESISTANCE LOAD RESISTANCE
Figure 13. Figure 14.
OUTPUT IMPEDANCE OUTPUT IMPEDANCE
vs vs
FREQUENCY FREQUENCY
Figure 15. Figure 16.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
Common-Mode Rejection Ratio, dB)CMRR (
90
80
70
60
85
75
65
VDD = 5 V
VIC = 2.5 V
VDD = 3 V
VIC = 1.5 V
Frequency, f (Hz)
10
100 10k 100k 1M 10M
1k
110
80
60
40
90
70
50
100
VDD =±1.5 V
TA= 25°C
Supply Voltage Rejection Ratio , k (dB)
SVR
kSVR
+kSVR
+kSVR
kSVR
Frequency, f (Hz)
10
100 1k 100k 1M 10M10k
80
60
40
90
70
50
VDD =±2.5 V
TA= 25°C
Supply Voltage Rejection Ratio , k (dB)
SVR
kSVR
+kSVR
+kSVR
kSVR
Frequency, f (Hz)
10
100 1k 100k 1M 10M10k
Supply Voltage, V (V)
DD
0.7
0.5
0.30
0.10
3 4
0.8
0.6
0.40
0.20
3.5 4.5
2.5 5 5.5
IDD = 25°C
Supply Current, I (mA)
DD
IDD = 85°C
IDD = 55 °C
IDD = 125°C
IDD = 40
6
°C
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
COMMON-MODE REJECTION RATIO SUPPLY-VOLTAGE REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 17. Figure 18.
SUPPLY-VOLTAGE REJECTION RATIO SUPPLY CURRENT
vs vs
FREQUENCY SUPPLY VOLTAGE
Figure 19. Figure 20.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
Supply Voltage, V (V)
DD
0.7
0.5
0.30
0.10
3 4
0.8
0.6
0.40
0.20
3.5 4.5
2.5 5 5.5
IDD = 25°C
Supply Current, I (mA)
DD
IDD = 85°C
IDD = 55 °C
IDD = 125°C
IDD = 40
6
°C
Supply Current, I (mA)
DD
0.60
0.50
0.40
0.30
–35 5
0.65
0.55
0.45
0.35
–15 25
0.80
–55
45 65
0.70
0.75
VDD = 5 V
VI= 2.5 V
VDD = 3 V
VI= 1.5 V
85 105 125
Free-Air Temperature (, T C)
A
°
Time, t (μs)
2
0
2
0
–3 1
1
3
1
–1 3
5
–55 7
Shutdown Voltage, V (V)
SD
3
11
9
4
VDD = 5 V
RL= 10 kΩ
AV= 1
TA= 25°C
Shutdown Pin
Amplifier Output
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
SUPPLY CURRENT
vs AMPLIFIER WITH A SHUTDOWN PULSE
FREE-AIR TEMPERATURE TURNON CHARACTERISTICS
Figure 21. Figure 22.
AMPLIFIER WITH A SHUTDOWN PULSE SUPPLY CURRENT WITH A SHUTDOWN PULSE
TURNOFF CHARACTERISTICS TURNON CHARACTERISTICS
Figure 23. Figure 24.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
VDD = 5 V
VI= 2.5 V
AV= 1
TA= 25°C
0.4
0.2
0.2
0
0.8
1
0.6
Supply Current
Shutdown Pin
Supply Current, I (mA)
DD
4.5
5.5
2.5
3.5
0.5
1.5
0.5
Time, t (μs)
–0.40 –0.20 00.40.2 0.6
Shutdown Voltage, V (V)
SD
10
14
12
15
13
11
17
18
16
VDD = 3 V
AV= 10
VI= 1.5 V
TA= 25°C
Frequency, f (Hz)
100
1k 10k
(nV/ Hz)
Equivalent Input Noise Voltage, Vn
100k
Supply Voltage V), V (
DD
1.6
1.5
1.4
1.3
1.55
1.45
1.35
1.8
1.7
1.75
1.65
VO(PP) = 2 V
CL= 160 pF
AV= 1
RL= 10 kΩ
TA= 25°C
SR+
SR
Slew Rate (V/, SR s)m
3 43.5 4.5
2.5 5 5.5 6
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
SHUTDOWN SUPPLY CURRENT
TURNOFF SUPPLY CURRENT vs
WITH A SHUTDOWN PULSE FREE-AIR TEMPERATURE
Figure 25. Figure 26.
SLEW RATE EQUIVALENT INPUT NOISE VOLTAGE
vs vs
SUPPLY VOLTAGE FREQUENCY
Figure 27. Figure 28.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
10
14
12
15
13
11
17
18
16
VDD = 5 V
AV= 10
VI= 2.5 V
TA= 25°C
Frequency, f (Hz)
100
1k 10k
(nV/ Hz)
Equivalent Input Noise Voltage, Vn
100k
12
10
14
13
11
20
15
VDD = 3 V
AV= 10
f = 1 kHz
TA= 25°C
(nV/ Hz)
Common-Mode Input Voltage, (V)VICR
0
Equivalent Input Noise Voltage, Vn
0.5 11.5 22.5
0.001 100 10k1k 100k10
0.1
VDD =±1.5 V
VO(PP) = 2 V
RL= 10 kΩ
AV= 1
AV= 10
AV= 100
0.5
Frequency, f (Hz)
Total Harmonic Distortion, THD (%)
12
10
14
13
11
20
15
VDD = 5 V
AV= 10
f = 1 kHz
TA= 25°C
Common-Mode Input Voltage, (V)VICR
21 3 50 4
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
EQUIVALENT INPUT NOISE VOLTAGE EQUIVALENT INPUT NOISE VOLTAGE
vs vs
FREQUENCY COMMON-MODE INPUT VOLTAGE
Figure 29. Figure 30.
EQUIVALENT INPUT NOISE VOLTAGE TOTAL HARMONIC DISTORTION
vs vs
COMMON-MODE INPUT VOLTAGE FREQUENCY
Figure 31. Figure 32.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
0.001 100 10k
Frequency, f (Hz)
1k 100k10
0.1
VDD =±2.5 V
VO(PP) = 4 V
RL= 10 kΩ
AV= 1
AV= 10
AV= 100
1
Total Harmonic Distortion, THD (%)
0.010
0.001
0.1
VDD = 3 V
AV= 1
TA = 25°C
1
RL= 10 kΩ
RL= 2 kΩ
RL= 250 Ω
RL= 100 kΩ
Peak-to-Peak Signal Amplitude ( V)
1 1.2 1.8 2.41.4 2 2.6 31.6 2.2 2.8 3.2
Total Harmonic Distortion + Noise, THD+N (%)
44.1 4.4 4.7
4.2 4.5 4.84.3 4.6 4.9 5
0.010
0.001
0.1
VDD = 5 V
AV= 1
TA= 25°C
1
RL= 10 kΩ
RL= 250 Ω
RL= 100 kΩ
Peak-to-Peak Signal Amplitude (V)
RL= 2 kΩ
Total Harmonic Distortion + Noise, THD+N (%)
Load Capacitance, C (pF)
L
60
40
20
0
70
50
30
10
100 1k
90
10 10k
80
Phase Margin, (degrees)φm
VDD =±2.5 V
TA= 25°C
RL= 10 kΩ
Rnull = 50 Ω
Rnull = 20 Ω
Rnull = 0 Ω
100k
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
FREQUENCY PEAK-TO-PEAK SIGNAL AMPLITUDE
Figure 33. Figure 34.
TOTAL HARMONIC DISTORTION PLUS NOISE PHASE MARGIN
vs vs
PEAK-TO-PEAK SIGNAL AMPLITUDE LOAD CAPACITANCE
Figure 35. Figure 36.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
Phase Margin, (degrees)φm
60
50
40
30
55
45
35
RL= 10 kΩ
CL= 160 pF
VDD =±2.5 V
VDD =±1.5 V
–35 5
–15 25
–55
45 65 85 105 125
Free-Air Temperature (, T C)
A°
5
4.5
4
3.5
4.75
4.25
3.75
Gain Bandwidth Product (MHz)
CL= 160 pF
RL= 10 kΩ
f = 10 kHz
TA= 25°C
Supply Voltage V), V (
DD
3 43.5 4.5
2.5 5 5.5 6
Voltage, V (V)
O
1.4
0.8
1.2
1
2.2
1.8
2
1.6
Input
Output
Output
Input
VDD = 3 V
VI(PP) = 1 V
VI= 1.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
Time, t (μs)
–2 08
210
4 12 166 14 18
Gain Bandwidth Product (MHz)
4.5
4
3.5
3
4.25
3.75
3.25
RL= 10 kΩ
CL= 160 pF
VDD =±2.5 V
VDD =±1.5 V
5
4.75
–35 5
–15 25
–55
45 65 85 105 125
Free-Air Temperature (, T C)
A°
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
PHASE MARGIN GAIN BANDWIDTH PRODUCT
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 37. Figure 38.
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE LARGE SIGNAL FOLLOWER
Figure 39. Figure 40.
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Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
Voltage, V (V)
O
2.1
1.7
1.3
3.7
2.9
3.3
2.5
Input
Output
Output
Input
VDD = 5 V
VI(PP) = 2 V
VI= 2.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
Time, t (μs)
–2 08
210
4 12 166 14 18
Voltage, V (V)
O
1.5
1.4
1.45
1.6
1.55
Input
Output
VDD = 3 V
VI(PP) = 100 mV
VI= 1.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
Time, t (μs)
–0.2 0 0.8
0.2 1
0.4 1.2 1.60.6 1.4 1.8
Voltage, V (V)
O
2.5
2.4
2.45
2.6
2.55
Input
Output
VDD = 5 V
VI(PP) = 100 mV
VI= 2.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
Time, t (μs)
–0.2 0 0.8
0.2 1
0.4 1.2 1.60.6 1.4 1.8
VDD = 3 V
VI(PP) = 1 V
VI= 1.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
1.1
0.5
0.9
0.7
1.9
1.5
1.7
1.3
2.3
2.1 Input
Output
Voltage, V (V)
O
Time, t (μs)
–0.2 0 0.8
0.2 1
0.4 1.2 1.60.6 1.4 1.8
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
LARGE SIGNAL FOLLOWER SMALL SIGNAL FOLLOWER
Figure 41. Figure 42.
SMALL SIGNAL FOLLOWER INVERTING LARGE SIGNAL
Figure 43. Figure 44.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
1.5
1.4
1.45
1.6
1.55
Input
Output
VDD = 3 V
VI(PP) = 100 mV
VI= 1.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
Voltage, V (V)
O
Time, t (μs)
–0.2 0 0.8
0.2 1
0.4 1.2 1.60.6 1.4 1.8
VDD = 5 V
VI(PP) = 2 V
VI= 2.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
2.5
1
2
1.5
3.5
4
3
Input
Output
Voltage, V (V)
O
Time, t (μs)
–0.2 0 0.8
0.2 1
0.4 1.2 1.60.6 1.4 1.8
2.5
2.4
2.45
2.6
2.55
Input
Output
VDD = 5 V
VI(PP) = 100 mV
VI= 2.5 V
RL= 10 kΩ
CL= 160 pF
AV= 1
TA= 25°C
Voltage, V (V)
O
Time, t (μs)
–0.2 0 0.8
0.2 1
0.4 1.2 1.60.6 1.4 1.8
_
+
R
RC
null
LL
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
INVERTING LARGE SIGNAL INVERTING SMALL SIGNAL
Figure 45. Figure 46.
INVERTING SMALL SIGNAL
Figure 47.
PARAMETER MEASUREMENT INFORMATION
Figure 48.
20 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
CLOAD
R
Input
F
Output
RGRNULL
_
+
+
V
+
I
R
R
G
S
R
I
F
IB
VO
IIB+
(1 ( )) (1 ( ))
F F
OO IO IB S IB F
G G
R R
V V I R I R
R R
-= + ± + + ±
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
APPLICATION INFORMATION
Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10
pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in
Figure 49. A minimum value of 20 Ωworks well for most applications.
Figure 49. Driving a Capacitive Load
Offset Voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The schematic and formula in Figure 50 can be used to calculate the output offset
voltage.
Figure 50. Output Offset Voltage Model
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
V
V
I
O
C1
+
R R
R1
G F
f–3dB
1
2pR1C1
1
(1 )( )
1 1 1
O F
I G
V R
V R sR C
= +
+
=
VI
C2
R2R1
C1
R
RF
G
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
_
+
RG
R
2
F
–
Q
f
–3dB
1
1
2pRC
=
=
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 51).
Figure 51. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
Figure 52. 2-Pole Low-Pass Sallen-Key Filter
Shutdown Function
Two members of the TLV246x family (TLV2460 and TLV2463) have a shutdown terminal for conserving battery
life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3
mA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the
amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left
floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not
inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always
referenced to VDD/2. Therefore, when operating the device with split supply voltages (e.g., ±2.5 V), the shutdown
terminal must be pulled to VDD−(not GND) to disable the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figure 22,Figure 23,Figure 24, and Figure 25. The
amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The
amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of
the output waveform. The times for the single, dual, and quad are listed in the data tables.
Circuit Layout Considerations
To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
• Ground planes −It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
22 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
( )
MAX A
D
JA
T T
P
q
-
=
1
0.75
0.5
0
Maximum Power Dissipation (W)
1.25
1.5
1.75
0.25
2
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ= 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
–40 –25
–55
50 65 80 95 110 125
Free-Air Temperature (, T C)
A
°
–10 520 35
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
• Proper power supply decoupling −Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-mF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
• Sockets −Sockets can be used but are not recommended. The additional lead inductance in the socket pins
often leads to stability problems. Surface-mount packages soldered directly to the printed circuit board is the
best implementation.
• Short trace runs/compact part placements −Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the input of the
amplifier.
• Surface-mount passive components −Using surface-mount passive components is recommended for
high-performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
General Power Dissipation Considerations
For a given qJA, the maximum power dissipation is shown in Figure 53 and is calculated by Equation 1:
(1)
Where:
PD= Maximum power dissipation of TLV246x (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA= Ambient free-air temperature (°C)
qJA =qJC +qCA
qJC = Thermal coefficient from junction to case
qCA = Thermal coefficient from case to ambient air (°C/W)
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
www.ti.com
Macromodel Information
Macromodel information provided was derived using Microsim Parts™ Release 8, the model generation software
used with Microsim PSpice™. The Boyle macromodel(1) and subcircuit in Figure 54 were generated using the
TLV246x typical electrical and operating characteristics at TA= 25°C. Using this information, output simulations
of the following key parameters can be generated to a tolerance of 20% (in most cases):
(1) G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974). • Unity gain frequency
• Maximum positive output voltage swing • Common-mode rejection ratio
• Maximum negative output voltage swing • Phase margin
• Slew rate • DC output resistance
• Quiescent power dissipation • AC output resistance
• Input bias current • Short-circuit output current limit
• Open-loop voltage amplification
24 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
+
+
+ +
+
VDD +
RP
IN
2
IN +
1
GND
RD1
11
J1 J2
10
RSS
ISS
3
12
RD2
DP
VD
DC
4
C1
53
EGND
FB
HLIM
90
DLP
91
DLN
92
VLNVLP
99
CSS
+
VE
DE
54
OUT
+
+
R2 6
9
VB
C2
GA
VLIM
8
5
RO1
RO2
7
GCM
.SUBCKT TLV246X 1 2 3 4 5
C1
C2
CSS
DC
DE
DLP
DLN
DP
EGND
FB
11
6
10
5
54
90
92
4
99
7
12
7
99
53
5
91
90
3
0
99
2.46034E-12
10.0000E-12
443.21E-15
DY
DY
DX
DX
DX
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
+ VLN 0 21.600E6 1E3 1E3 22E6 22E6– –
GA
GCM
ISS
HLIM
J1
J2
R2
6
0
10
90
11
12
6
0
6
4
0
2
1
9
11 12 345.26E- 6
99 15.4226E- 9
10
DC 18.850E- 6
VLIM 1K
10 JX1
10 JX2
100.00E3
RD1
RD2
R01
R02
RP
RSS
VB
VC
VE
VLIM
VLP
VLN
3
3
8
7
3
10
9
3
54
7
91
0
11
12
5
99
4
99
0
53
4
8
0
92
2.8964E3
2.8964E3
5.6000
6.2000
8.9127
10.610E6
DC 0
DC .7436
DC .7836
DC 0
DC 117
DC 117
dc 117
dc 117
dc 0
dc 0
6 4 s1x
1G
dc .7436
6 4 s2x
6 4 s1x
1G
dc .7836
6 4 s1x
1G
1G
10.610E6
.MODEL DX D (IS=800.00E 18)–
.MODEL DY D (IS=800.00E 18 Rs = 1m Cjo=10p)–
.MODEL JX1 NJF (IS=1.0000E 12 BETA=6.3239E 3– –
+ VTO= 1)–
.MODEL JX2 NJF (IS=1.0000E 12 BETA=6.3239E 3– –
+ VTO= 1)–
.ENDS
.subckt TLV_246Y 1 2 3 4 5 6
c1
c2
css
dc
de
dlp
dln
dp
egnd
fb
11
72
10
70
54
90
92
4
99
7
12
7
99
53
70
91
90
3
0
99
2.4603E-12
10.000E-12
443.21E-15
dy
dy
dx
dx
dx
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
21.600E6 1E3 1E3 22E6 22E6– –
ga
gcm
iss
hlim
j1
j2
r2
rd1
rd2
ro1
ro2
72
0
74
90
11
12
72
3
3
8
7
0
72
4
0
2
1
9
11
12
70
99
11 12 345.26E- 6
10 99 15.422E- 9
dc 18.850E- 6
vlim 1K
10 jx1
10 jx2
100.00E3
2.8964E3
2.8964E3
5.6000
6.2000
rp
rss
rs1
rs2
rs3
rs4
s1
s2
s3
s4
vb
vc
ve
vlim
vlp
vln
3
10
6
6
6
6
71
70
10
74
9
3
54
7
91
0
71
99
4
4
4
4
4
5
74
4
0
53
4
8
0
92
8.9127
.model dx D(Is=800.00E 18)–
.model dy D(Is=800.00E 18 Rs=1m Cjo=10p)–
.model jx1 NJF(Is=1.0000E 12 Beta=6.3239E 3 Vto= 1)– – –
.model jx2 NJF(Is=1.0000E 12 Beta=6.3239E 3 Vto= 1)– – –
.model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0)
.model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5)
.ends
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com
SGLS008D –MARCH 2003–REVISED SEPTEMBER 2010
Figure 54. Boyle Macromodel and Subcircuit
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1
TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2460AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460AQDRQ1 ACTIVE SOIC D 8 TBD Call TI Call TI
TLV2460AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460AQPWRQ1 ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2460QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460QDRQ1 ACTIVE SOIC D 8 TBD Call TI Call TI
TLV2460QPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2460QPWRQ1 ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2461AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461AQDRQ1 ACTIVE SOIC D 8 TBD Call TI Call TI
TLV2461AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461AQPWRQ1 ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2461QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461QDRQ1 ACTIVE SOIC D 8 TBD Call TI Call TI
TLV2461QPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2461QPWRQ1 ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2462AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462AQPWRQ1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2462QDGKRQ1 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV2462QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462QPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2462QPWRQ1 ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2463AQDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463AQDRQ1 ACTIVE SOIC D 14 TBD Call TI Call TI
TLV2463AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463AQPWRQ1 ACTIVE TSSOP PW 14 TBD Call TI Call TI
TLV2463QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463QDRQ1 ACTIVE SOIC D 14 TBD Call TI Call TI
TLV2463QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2463QPWRQ1 ACTIVE TSSOP PW 14 TBD Call TI Call TI
TLV2464AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2464AQPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1, TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1,
TLV2464A-Q1 :
•Catalog: TLV2460, TLV2460A, TLV2461, TLV2461A, TLV2462, TLV2462A, TLV2463, TLV2463A, TLV2464A
•Enhanced Product: TLV2462A-EP, TLV2464A-EP
•Military: TLV2460M, TLV2460AM, TLV2461M, TLV2461AM, TLV2462M, TLV2462AM, TLV2463M, TLV2463AM
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2462QDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2462QDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2462QDGKRQ1 VSSOP DGK 8 2500 364.0 364.0 27.0
TLV2462QDGKRQ1 VSSOP DGK 8 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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