TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN Check for Samples: TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1, TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463AQ1, TLV2464A-Q1 FEATURES 1 * * * * * Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Rail-to-Rail Output Swing Gain Bandwidth Product . . . 6.4 MHz 80-mA Output Drive Capability TLV2460 D OR PW PACKAGE (TOP VIEW) NC IN IN + GND 1 8 2 7 3 6 4 5 1OUT 1IN 1IN+ GND NC 1SHDN NC * * * * * Supply Current . . . 500 mA/Channel Input Offset Voltage . . . 100 mV Input Noise Voltage . . . 11 nV/Hz Slew Rate . . . 1.6 V/ms Micropower Shutdown Mode (TLV2460/TLV2463) . . . 0.3 mA/Channel Universal Operational Amplifier EVM * TLV2461 D OR PW PACKAGE (TOP VIEW) NC IN IN + GND SHDN VDD+ OUT NC 1 8 2 7 3 6 4 5 TLV2462 D, DGK, OR PW PACKAGE (TOP VIEW) 1OUT 1IN 1IN + GND NC VDD+ OUT NC TLV2463 D OR PW PACKAGE TLV2464 D OR PW PACKAGE (TOP VIEW) (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD+ 2OUT 2IN 2IN+ NC 2SHDN NC 1OUT 1IN 1IN+ VDD+ 2IN+ 2IN 2OUT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1 8 2 7 3 6 4 5 VDD+ 2OUT 2IN 2IN+ 4OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT NC - No internal connection DESCRIPTION The devices in the TLV246x family of low-power rail-to-rail input/output operational amplifiers are specifically designed for portable applications. The input common-mode voltage range extends beyond the supply rails for maximum dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters. The operational amplifier has 6.4-MHz bandwidth and 1.6-V/ms slew rate with only 500-mA supply current, providing good ac performance with low power consumption. Devices are available with an optional shutdown terminal, which places the amplifier in an ultralow supply-current mode (IDD = 0.3 mA/channel). While in shutdown, the operational amplifier output is placed in a high-impedance state. DC applications are also well served with an input noise voltage of 11 nV/Hz and input offset voltage of 100 mV. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2010, Texas Instruments Incorporated TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com ORDERING INFORMATION (1) VIOmax AT 25C TA PACKAGE (2) SOP - D Reel of 2500 2000 mV TSSOP - PW Reel of 2000 ORDERABLE PART NUMBER TLV2460QDRQ1 2460Q1 TLV2461QDRQ1 2461Q1 TLV2462QDRQ1 2462Q1 TLV2463QDRQ1 2463Q1 TLV2464QDRQ1 (3) 2464Q1 TLV2460QPWRQ1 2460Q1 TLV2461QPWRQ1 2461Q1 TLV2462QPWRQ1 2462Q1 TLV2463QPWRQ1 TLV2464QPWRQ1 MSOP - DGK -40C to 125C SOP - D Reel of 2500 Reel of 2500 1500 mV TSSOP - PW (1) (2) (3) 2 Reel of 2000 TOP-SIDE MARKING 2463Q1 (3) 2464Q1 TLV2462QDGKRQ1 QVM TLV2460AQDRQ1 2460AQ TLV2461AQDRQ1 2461AQ TLV2462AQDRQ1 2462AQ TLV2463AQDRQ1 TLV2463AQ1 TLV2464AQDRQ1 (3) 2464AQ TLV2460AQPWRQ1 2460AQ TLV2461AQPWRQ1 2461AQ TLV2462AQPWRQ1 2462AQ TLV2463AQPWRQ1 2463AQ TLV2464AQPWRQ1 2464AQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Product Preview Submit Documentation Feedback Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VDD Supply voltage (2) VID Differential input voltage range II Input current (any input) 200 mA IO Output current 175 mA II Total input current (into VDD+) 175 mA IO Total output current (out of GND) 175 mA TA Operating free-air temperature range TJ Maximum junction temperature 6V -0.2 V to VDD + 0.2 V -40C to 125C 150C Thermal impedance, junction to ambient (3) qJA D (8 pin) 176C/W D (14 pin) 123C/W PW (8 pin) 259C/W PW (14 pin) 174C/W DGK (8 pin) Tstg (1) (2) (3) 242C/W Storage temperature range -65C to 150C Latch-Up performance meets 100 mA per AEC-Q100 ( Class I ) Class I Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to GND. Package thermal impedance is calculated in accordance with JESD 51-5. RECOMMENDED OPERATING CONDITIONS Single supply MIN MAX 2.7 6 1.35 3 UNIT VDD Supply voltage VICR Common-mode input voltage range -0.2 VDD + 0.2 V TA Operating free-air temperature -40 125 C Shutdown on/off voltage level (1) (1) Split supply VIH 2 VIL 0.7 V V Relative to voltage on the GND terminal of the device Copyright (c) 2003-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 3 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage TEST CONDITIONS VDD = 3 V, VIC = 1.5 V, VO = 1.5 V, RS = 50 TLV246x TLV246xA aVIO Temperature coefficient of input offset voltage VDD = 3 V, VIC = 1.5 V, VO = 1.5 V, RS = 50 IIO Input offset current VDD = 3 V, VIC = 1.5 V, VO = 1.5 V, RS = 50 IIB Input bias current VIC = 1.5 V, VO = 1.5 V, RS = 50 IO = -2.5 mA VOH High-level output voltage IO = -10 mA VIC = 1.5 V, IOL = 2.5 mA VOL Low-level output voltage VIC = 1.5 V, IOL = 10 mA Sourcing IOS Short circuit output current Sinking IO Output current AVD Large-signal differential voltage amplification ri(d) Differential input resistance ci(o) Common-mode input capacitance zo Measured 1 V from rail RL = 10 k TA (1) MIN 25C TYP MAX 100 2000 Full range 2200 25C 150 Full range 1500 25C 2.8 Full range 25C 4.4 14 pA pA 2.9 2.8 25C V 2.7 2.5 25C 0.1 Full range 0.2 25C 0.3 Full range V 0.5 25C 50 20 25C Full range 7 75 25C Full range mV/C 75 Full range Full range mV 1700 2 Full range UNIT mA 40 20 25C 40 25C 90 Full range 89 mA 105 dB 25C 109 f = 10 kHz 25C 7 pF Closed-loop output impedance f = 100 kHz, AV = 10 25C 33 CMRR Common-mode rejection ratio VICR = 0 V to 3 V, RS = 50 kSVR Supply-voltage rejection ratio (VDD/VIO) VDD = 2.7 V to 6 V, VIC = VDD/2, No load VDD = 3 V to 5 V, VIC = VDD/2, No load IDD Supply current (per channel) VO = 1.5 V, No load IDD(SHDN) Supply current in shutdown (TLV2460, TLV2463) SHDN < 0.7 V, Per channel in shutdown (1) 4 25C 66 Full range 60 25C 80 Full range 75 25C 85 Full range 80 25C 80 85 dB 95 0.5 Full range 25C dB 0.575 0.9 0.3 Full range 2.5 mA mA Full range is -40C to 125C. Submit Documentation Feedback Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 OPERATING CHARACTERISTICS VDD = 3 V, at specified free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS SR Slew rate at unity gain VO(PP) = 2 V, CL = 160 pF, RL = 10 k Vn Equivalent input noise voltage In Equivalent input noise current f = 1 kHz THD+N Total harmonic distortion plus noise f = 100 Hz (1) MIN TYP 25C 1 1.6 TA Full range 25C f = 1 kHz 25C AV = 1 VO(PP) = 2 V, RL = 10 k, f = 1 kHz AV = 10 Amplifier turn-on time AV = 1, RL = 10 k t(off) Amplifier turn-off time AV = 1, RL = 10 k 25C ts fm (1) Settling time f = 10 kHz, CL = 160 pF, RL = 10 k V(STEP)PP = 2 V, AV = -1, CL = 10 pF, RL = 10 k 0.1% V(STEP)PP = 2 V, AV = -1, CL = 56 pF, RL = 10 k 0.1% 11 0.13 nV/Hz pA/Hz 0.02 % 7.65 ms 333 328 25C Channel 2 only, Channel 1 on Gain-bandwidth product 16 7.6 Both channels Channel 1 only, Channel 2 on V/ms 0.8 0.08 Both channels t(on) UNIT 0.006 25C AV = 100 Channel 1 only, Channel 2 on MAX ns 329 25C 5.2 MHz 1.47 0.01% 1.78 25C 0.01% 1.77 ms 1.98 Phase margin at unity gain RL = 10 k, CL = 160 pF 25C 44 Gain margin RL = 10 k, CL = 160 pF 25C 7 dB Full range is -40C to 125C. Copyright (c) 2003-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 5 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Input offset voltage TEST CONDITIONS VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 TLV246x TLV246xA TA (1) IIO Input offset current VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Full range IIB Input bias current VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Full range TLV2462QDGKRQ1 VIC = 2.5 V, IOL = 2.5 mA Low-level output voltage VIC = 2.5 V, IOL = 10 mA Sourcing IOS Short circuit output current Sinking IO Output current Measured 1 V from rail AVD Large-signal differential voltage amplification VIC = 2.5 V, RL = 10 k, VO = 1 V to 4 V ri(d) Differential input resistance ci(o) Common-mode input capacitance zo 1500 25C 0.3 1.3 pA 4.9 4.8 V 4.7 4.8 4.4 25C 0.1 Full range 0.2 25C 0.2 Full range V 0.3 25C 145 60 25C Full range 14 pA 4.8 25C Full range 7 60 25C Full range mV mV/C 60 25C Full range UNIT 1700 25C IO = -10 mA VOL 150 2 Full range TLV246x,TLV246xA 2000 Full range aVIO High-level output voltage MAX 150 2200 25C VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 IO = -2.5 mA TYP Full range Temperature coefficient of input offset voltage VOH MIN 25C mA 100 60 25C 80 25C 92 Full range 90 mA 109 dB 25C 109 f = 10 kHz 25C 7 pF Closed-loop output impedance f = 100 kHz, AV = 10 25C 29 CMRR Common-mode rejection ratio VICR = 0 V to 5 V, RS = 50 kSVR Supply-voltage rejection ratio (VDD/VIO) VDD = 2.7 V to 6 V, VIC = VDD/2, No load VDD = 3 V to 5 V, VIC = VDD/2, No load IDD Supply current (per channel) VO = 2.5 V, No load IDD(SHD Supply current in shutdown (TLV2460, TLV2463) SHDN < 0.7 V, Per channel in shutdown N) (1) 6 25C 71 Full range 60 25C 80 Full range 75 25C 85 Full range 80 25C 85 85 dB 95 0.55 Full range 25C dB 0.65 1 mA 1 Full range 3 mA Full range is -40C to 125C. Submit Documentation Feedback Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 OPERATING CHARACTERISTICS VDD = 5 V, at specified free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS SR Slew rate at unity gain VO(PP) = 2 V, CL = 160 pF, RL = 10 k Vn Equivalent input noise voltage In Equivalent input noise current f = 100 Hz THD+N Total harmonic distortion plus noise f = 100 Hz (1) MIN TYP 25C 1 1.6 TA Full range 25C f = 1 kHz 25C AV = 1 VO(PP) = 4 V, RL = 10 k, f = 10 kHz AV = 10 t(off) Amplifier turn-on time Amplifier turn-off time AV = 1, RL = 10 k AV = 1, RL = 10 k ts fm (1) Settling time 11 0.13 ms 333 0.1% V(STEP)PP = 2 V, AV = -1, CL = 56 pF, RL = 10 k 0.1% % 7.65 25C Both channels V(STEP)PP = 2 V, AV = -1, CL = 10 pF, RL = 10 k pA/Hz 0.01 7.25 f = 10 kHz, CL = 160 pF, RL = 10 k nV/Hz 7.6 328 25C Channel 2 only, Channel 1 on Gain-bandwidth product 14 Channel 2 only, Channel 1 on Channel 1 only, Channel 2 on V/ms 0.8 0.04 Both channels t(on) UNIT 0.004 25C AV = 100 Channel 1 only, Channel 2 on MAX ns 329 25C 6.4 MHz 1.53 0.01% 1.83 25C 0.01% 3.13 ms 3.33 Phase margin at unity gain RL = 10 k, CL = 160 pF 25C 45 Gain margin RL = 10 k, CL = 160 pF 25C 7 dB Full range is -40C to 125C. Copyright (c) 2003-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 7 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage 1, 2 IIB Input bias current vs Free-air temperature 3, 4 IIO Input offset current vs Free-air temperature 3, 4 VOH High-level output voltage vs High-level output current 5, 6 VOL Low-level output voltage vs Low-level output current 7, 8 VO(PP) Maximum peak-to-peak output voltage vs Frequency 9, 10 Open-loop gain vs Frequency 11, 12 Phase vs Frequency 11, 12 Differential voltage amplification vs Load resistance Capacitive load vs Load resistance zo Output impedance vs Frequency CMRR Common-mode rejection ratio vs Frequency 17 kSVR Supply-voltage rejection ratio vs Frequency 18, 19 IDD Supply current AVD 13 14 15, 16 vs Supply voltage 20 vs Free-air temperature 21 Amplifier turnon characteristics 22 Amplifier turnoff characteristics 23 Supply current turnon 24 Supply current turnoff 25 Shutdown supply current vs Free-air temperature 26 SR Slew rate vs Load capacitance 27 Vn Equivalent input noise voltage THD THD + N fm vs Frequency 28, 29 vs Common-mode input voltage 30, 31 Total harmonic distortion vs Frequency 32, 33 Total harmonic distortion plus noise vs Peak-to-peak signal amplitude 34, 35 vs Frequency 11, 12 Phase margin Gain-bandwidth product 8 vs Load capacitance 36 vs Free-air temperature 37 vs Supply voltage 38 vs Free-air temperature 39 Large signal follower 40, 41 Small signal follower 42, 43 Inverting large signal 44, 45 Inverting small signal 46, 47 Submit Documentation Feedback Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 1 1 VDD = 5 V TA = 25C 0.8 0.6 Input Offset Voltage, VIO (mV) Input Offset Voltage, VIO (mV) VDD = 3 V TA = 25C 0.4 0.2 0 0.2 0.4 0.6 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 0.8 1 1 0 0.5 1.5 1 2.5 2 3 0 1 2 3 4 Common-Mode Input Voltage, VICR (V) 5 Figure 1. Figure 2. INPUT BIAS AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE INPUT BIAS AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE 5 VDD = 3 V VI = 1.5 V 4.5 IIB 4 3.5 3 2.5 2 1.5 1 0.5 IIO 0 0.5 -55 -35 -15 5 25 45 65 85 Free-Air Temperature, TA (C) Figure 3. Copyright (c) 2003-2010, Texas Instruments Incorporated 105 125 Input Bias and Input Offset Current, IIB and IIO (nA) Input Bias and Input Offset Current, IIB and IIO (nA) Common-Mode Input Voltage, VICR (V) 6 VDD = 5 V VI = 2.5 V 5 IIB 4 3 2 1 IIO 0 1 -55 -35 -15 5 25 45 65 85 105 125 Free-Air Temperature, TA (C) Figure 4. Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 9 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3 5 VDD = 3 V DC VDD = 5 V DC 2.5 High-Level Output Voltage, VOH (V) High-Level Output Voltage, VOH (V) 4.5 TA = 55 C 2 1.5 TA = 125C TA = 85C TA = 25C 1 TA = 40 C 0.5 TA = 55 C 4 3.5 3 TA = 125C TA = 85C 2.5 2 TA = 25C 1.5 TA = 40 C 1 0.5 0 0 0 10 20 30 40 50 60 70 80 0 High-Level Output Current, IOH (mA) 20 40 60 80 100 120 140 160 180 200 High-Level Output Current, IOH (mA) Figure 5. Figure 6. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4.5 3 VDD = 5 V DC VDD = 3 V DC Low-Level Output Voltage, VOL (V) Low-Level Output Voltage, VOL (V) 4 2.5 TA = 40 C 2 TA = 25C TA = 85C TA = 125C 1.5 1 0.5 3.5 TA = 40 C 3 TA = 25C 2.5 TA = 85C TA = 125C 2 1.5 1 TA = 55 C 0.5 TA = 55 C 0 0 0 10 20 30 40 50 60 70 0 20 40 60 80 100 120 140 160 Low-Level Output Current, IOL (mA) Figure 7. 10 Submit Documentation Feedback Figure 8. Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 5.5 VDD = 3 V AV = 10 THD = 1% RL = 10 k 2.5 Peak-to-Peak Output Voltage, VO(PP) (V) Peak-to-Peak Output Voltage, VO(PP) (V) 3 2 1.5 1 0.5 VDD = 5 V AV = 10 THD = 1% RL = 10 k 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 10k 1M 100k 10M 1M 100k Frequency, f (Hz) Frequency, f (Hz) Figure 9. Figure 10. OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPEN-LOOP GAIN AND PHASE vs FREQUENCY VDD = 1.5 V RL = 10 k CL = 0 TA = 25C 90 80 70 60 40 100 20 90 0 80 20 70 AVD 50 60 40 80 30 100 Phase 20 120 Phase 40 Open-Loop Gain (dB) 100 Open-Loop Gain (dB) 0 10k 10M 40 VDD = 2.5 V RL = 10 k CL = 0 TA = 25C 60 20 0 20 40 AVD 50 60 40 80 100 30 Phase 20 120 10 140 10 140 0 160 0 160 -10 180 -10 180 -20 200 10M -20 10 100 1k 10k 100k 1M Frequency, f (Hz) Figure 11. Copyright (c) 2003-2010, Texas Instruments Incorporated Phase 0 200 10 100 1k 10k 100k 1M 10M Frequency, f (Hz) Figure 12. Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 11 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE 10000 180 TA = 25C 160 140 Capacitance, CL (pF) Differential Voltage Amplification, AVD (V/mV) CAPACITIVE LOAD vs LOAD RESISTANCE 120 VDD = 2.5 V 100 VDD = 1.5 V 80 60 Phase Margin < 30 1000 Phase Margin > 30 40 VDD = 5 V Phase Margin = 30 TA = 25C 20 100 0 100 1k 100k 10k Load Resistance, RL () Figure 13. Figure 14. OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 1000 VDD = 2.5 V TA = 25C 100 100 Output Impedance, ZO () Output Impedance, ZO () 10k 1000 VDD = 1.5 V TA = 25C 10 AV = 100 1 AV = 10 0.1 100 1k Load Resistance, RL () 10 1M 10 AV = 100 1 AV = 10 0.1 AV = 1 AV = 1 0.01 100 1k 10k 100k Frequency, f (Hz) Figure 15. 12 Submit Documentation Feedback 1M 10M 0.01 100 1k 10k 100k 1M 10M Frequency, f (Hz) Figure 16. Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 COMMON-MODE REJECTION RATIO vs FREQUENCY SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY 110 Supply Voltage Rejection Ratio , kSVR (dB) Common-Mode Rejection Ratio,CMRR (dB) 90 85 80 VDD = 5 V VIC = 2.5 V 75 VDD = 3 V VIC = 1.5 V 70 65 60 10 100 10k 100k 1k Frequency, f (Hz) 1M 10M k SVR 80 70 60 +kSVR 50 k SVR 100 10k 100k 1k Frequency, f (Hz) Figure 17. Figure 18. SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY SUPPLY CURRENT vs SUPPLY VOLTAGE 1M 10M 0.8 +kSVR IDD = 125C VDD = 2.5 V TA = 25C 70 60 +kSVR 50 IDD = 85C 0.7 k SVR Supply Current, IDD (mA) Supply Voltage Rejection Ratio , kSVR (dB) VDD = 1.5 V TA = 25C 90 40 10 90 80 +kSVR 100 0.6 0.5 0.40 IDD = 25C 0.30 IDD = 55 C IDD = 40 C 0.20 k SVR 40 10 0.10 100 10k 100k 1k Frequency, f (Hz) Figure 19. Copyright (c) 2003-2010, Texas Instruments Incorporated 1M 10M 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage, VDD (V) Figure 20. Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 13 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com SUPPLY CURRENT vs FREE-AIR TEMPERATURE AMPLIFIER WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS 0.8 0.80 IDD = 125C 0.75 0.7 0.70 VDD = 5 V VI = 2.5 V 0.65 Supply Current, IDD (mA) Supply Current, IDD (mA) IDD = 85C 0.60 0.55 VDD = 3 V VI = 1.5 V 0.50 0.45 0.6 0.5 0.40 IDD = 25C 0.30 IDD = 55 C 0.40 IDD = 40 C 0.20 0.35 0.30 -55 -35 0.10 -15 5 45 25 65 85 105 2.5 125 3 5 4 Shutdown Pin VDD = 5 V RL = 10 k AV = 1 TA = 25C Shutdown Pin 3 Shutdown Voltage, VSD (V) Shutdown Voltage, VSD (V) 6 SUPPLY CURRENT WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS 2 1 0 Amplifier Output 3 VDD = 5 V RL = 10 k AV = 1 TA = 25C -3 -1 2 1 0 3 Amplifier Output 2 1 1 3 Time, t (s) Figure 23. 14 5.5 AMPLIFIER WITH A SHUTDOWN PULSE TURNOFF CHARACTERISTICS 3 0 -5 5 Figure 22. 4 1 4.5 Figure 21. 5 2 4 3.5 Supply Voltage, VDD (V) Free-Air Temperature, TA (C) Submit Documentation Feedback 5 7 9 11 0 -5 -3 -1 3 1 Time, t (s) 5 7 Figure 24. Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE TURNOFF SUPPLY CURRENT WITH A SHUTDOWN PULSE Shutdown Pin 4.5 0.6 0.4 3.5 Supply Current 2.5 0.2 1.5 0 0.5 0.2 -0.40 0.2 0 Time, t (s) -0.20 0.4 2.5 Shutdown Supply Current, IDD (mA) VDD = 5 V VI = 2.5 V AV = 1 TA = 25C Shutdown Voltage, VSD (V) Supply Current, IDD (mA) 0.8 3 5.5 1 1.5 1 VDD = 3 V VI = 1.5 V 0.5 0 0.5 1 0.5 0.6 -55 -35 -15 5 25 45 65 85 105 125 Free-Air Temperature, TA (C) Figure 25. Figure 26. SLEW RATE vs SUPPLY VOLTAGE EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 18 Equivalent Input Noise Voltage, Vn (nV/ Hz) 1.8 1.75 1.7 Slew Rate, SR (V/ms) VDD = 5 V VI = 2.5 V 2 SR+ 1.65 1.6 1.55 SR 1.5 1.45 VO(PP) = 2 V CL = 160 pF AV = 1 RL = 10 k TA = 25C 1.4 1.35 1.3 2.5 3 5 3.5 4 4.5 Supply Voltage, VDD (V) Figure 27. Copyright (c) 2003-2010, Texas Instruments Incorporated 5.5 6 VDD = 3 V AV = 10 VI = 1.5 V TA = 25C 17 16 15 14 13 12 11 10 100 10k 1k Frequency, f (Hz) 100k Figure 28. Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 15 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY EQUIVALENT INPUT NOISE VOLTAGE vs COMMON-MODE INPUT VOLTAGE 20 VDD = 5 V AV = 10 VI = 2.5 V TA = 25C 17 Equivalent Input Noise Voltage, Vn (nV/ Hz) Equivalent Input Noise Voltage, Vn (nV/ Hz) 18 16 15 14 13 12 11 10 100 15 14 13 12 11 10 10k 1k Frequency, f (Hz) 0 100k 0.5 1.5 2.5 1 2 Common-Mode Input Voltage, VICR (V) Figure 29. Figure 30. EQUIVALENT INPUT NOISE VOLTAGE vs COMMON-MODE INPUT VOLTAGE TOTAL HARMONIC DISTORTION vs FREQUENCY 0.5 20 Total Harmonic Distortion, THD (%) VDD = 5 V AV = 10 f = 1 kHz TA = 25C 15 14 13 12 11 VDD = 1.5 V VO(PP) = 2 V RL = 10 k 0 1 2 3 4 Common-Mode Input Voltage, VICR (V) Figure 31. Submit Documentation Feedback 5 AV = 100 0.1 AV = 10 AV = 1 0.001 10 16 VDD = 3 V AV = 10 f = 1 kHz TA = 25C 10 100 1k 10k 100k Frequency, f (Hz) Figure 32. Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK SIGNAL AMPLITUDE 1 VDD = 2.5 V VO(PP) = 4 V RL = 10 k Total Harmonic Distortion + Noise, THD+N (%) Total Harmonic Distortion, THD (%) 1 0.1 AV = 100 AV = 10 AV = 1 0.001 10 100 1k 10k VDD = 3 V AV = 1 TA = 25C RL = 2 k 0.1 RL = 10 k 0.010 RL = 100 k 0.001 100k 1 Frequency, f (Hz) 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Peak-to-Peak Signal Amplitude ( V) Figure 33. Figure 34. TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK SIGNAL AMPLITUDE PHASE MARGIN vs LOAD CAPACITANCE 1 VDD = 2.5 V TA = 25C RL = 10 k 80 RL = 2 k 0.1 3.2 90 RL = 250 Phase Margin, m (degrees) Total Harmonic Distortion + Noise, THD+N (%) RL = 250 RL = 10 k 0.010 RL = 100 k 70 Rnull = 50 60 50 40 Rnull = 20 30 20 VDD = 5 V AV = 1 TA = 25C Rnull = 0 10 0.001 0 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Peak-to-Peak Signal Amplitude (V) Figure 35. Copyright (c) 2003-2010, Texas Instruments Incorporated 5 10 100 1k 10k 100k Load Capacitance, CL (pF) Figure 36. Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 17 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com PHASE MARGIN vs FREE-AIR TEMPERATURE GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 60 5 RL = 10 k CL = 160 pF 4.75 Gain Bandwidth Product (MHz) Phase Margin, m (degrees) 55 50 VDD = 2.5 V 45 VDD = 1.5 V 40 35 CL = 160 pF RL = 10 k f = 10 kHz TA = 25C 4.5 4.25 4 3.75 30 -55 -35 -15 5 25 45 65 85 105 3.5 2.5 125 5 3.5 4 4.5 Supply Voltage, VDD (V) 3 Free-Air Temperature, TA (C) Figure 37. LARGE SIGNAL FOLLOWER 2.2 5 RL = 10 k CL = 160 pF 2 VDD = 2.5 V 4.25 4 3.75 3.5 VDD = 1.5 V Output 1.6 1.4 VDD = 3 V VI(PP) = 1 V VI = 1.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 1.2 1 3.25 3 -55 -35 -15 5 25 45 65 85 Free-Air Temperature, TA (C) Figure 39. 18 Input 1.8 Voltage, VO (V) Gain Bandwidth Product (MHz) 4.5 6 Figure 38. GAIN BANDWIDTH PRODUCT vs FREE-AIR TEMPERATURE 4.75 5.5 Submit Documentation Feedback 105 125 0.8 -2 0 2 4 Input Output 8 6 10 Time, t (s) 12 14 16 18 Figure 40. Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 LARGE SIGNAL FOLLOWER SMALL SIGNAL FOLLOWER 3.7 1.6 3.3 1.55 Voltage, VO (V) Voltage, VO (V) Input 2.9 Output 2.5 VDD = 5 V VI(PP) = 2 V VI = 2.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 2.1 1.7 1.3 -2 0 2 4 Input 12 1.5 Output 1.45 Output 8 6 10 Time, t (s) Input 14 16 1.4 -0.2 18 VDD = 3 V VI(PP) = 100 mV VI = 1.5 V RL = 10 k 0 Figure 41. 0.2 0.4 0.6 0.8 1 Time, t (s) 1.2 1.4 1.6 1.8 Figure 42. SMALL SIGNAL FOLLOWER INVERTING LARGE SIGNAL 2.6 2.3 Input 2.1 1.9 Voltage, VO (V) 2.55 Voltage, VO (V) CL = 160 pF AV = 1 TA = 25C Input 2.5 Output VDD = 3 V VI(PP) = 1 V VI = 1.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 1.7 1.5 1.3 1.1 2.45 2.4 -0.2 VDD = 5 V VI(PP) = 100 mV VI = 2.5 V RL = 10 k 0 Output 0.9 CL = 160 pF AV = 1 TA = 25C 0.2 0.4 0.6 0.8 1 Time, t (s) 1.2 1.4 Figure 43. Copyright (c) 2003-2010, Texas Instruments Incorporated 0.7 1.6 1.8 0.5 -0.2 0 0.2 0.4 0.6 0.8 1 Time, t (s) 1.2 1.4 1.6 1.8 Figure 44. Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 19 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com INVERTING LARGE SIGNAL INVERTING SMALL SIGNAL 1.6 4 Input Input 1.55 VDD = 5 V VI(PP) = 2 V VI = 2.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 3 2.5 Voltage, VO (V) Voltage, VO (V) 3.5 VDD = 3 V VI(PP) = 100 mV VI = 1.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 1.5 2 1.45 Output Output 1.5 1 -0.2 0 0.2 0.4 0.6 0.8 1 Time, t (s) 1.4 -0.2 1.6 1.8 1.2 1.4 0 0.2 0.4 0.6 0.8 1 Time, t (s) Figure 45. 1.2 1.4 1.6 1.8 Figure 46. INVERTING SMALL SIGNAL 2.6 Input Voltage, VO (V) 2.55 VDD = 5 V VI(PP) = 100 mV VI = 2.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 2.5 2.45 Output 2.4 -0.2 0 0.2 0.4 0.6 0.8 1 Time, t (s) 1.2 1.4 1.6 1.8 Figure 47. PARAMETER MEASUREMENT INFORMATION _ Rnull + RL CL Figure 48. 20 Submit Documentation Feedback Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 APPLICATION INFORMATION Driving a Capacitive Load When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device's phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 49. A minimum value of 20 works well for most applications. RF RG RNULL _ Input Output + CLOAD Figure 49. Driving a Capacitive Load Offset Voltage The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The schematic and formula in Figure 50 can be used to calculate the output offset voltage. RF RG IIB + VI + VO RS IIB+ VOO = VIO (1 + ( RF RF )) IIB + RS (1 + ( )) IIB - RF RG RG Figure 50. Output Offset Voltage Model Copyright (c) 2003-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 21 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com General Configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 51). RG VI RF VO + R1 C1 f -3dB = 1 2pR1C1 VO RF 1 )( ) = (1 + VI RG 1 + sR1C1 Figure 51. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f -3dB = C2 RG RF RG = 1 2pRC RF 1 2 -Q Figure 52. 2-Pole Low-Pass Sallen-Key Filter Shutdown Function Two members of the TLV246x family (TLV2460 and TLV2463) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 mA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2. Therefore, when operating the device with split supply voltages (e.g., 2.5 V), the shutdown terminal must be pulled to VDD- (not GND) to disable the operational amplifier. The amplifier's output with a shutdown pulse is shown in Figure 22, Figure 23, Figure 24, and Figure 25. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Circuit Layout Considerations To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. * Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. 22 Submit Documentation Feedback Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com * * * * SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 Proper power supply decoupling - Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-mF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. Sockets - Sockets can be used but are not recommended. The additional lead inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to the printed circuit board is the best implementation. Short trace runs/compact part placements - Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the input of the amplifier. Surface-mount passive components - Using surface-mount passive components is recommended for high-performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. General Power Dissipation Considerations For a given qJA, the maximum power dissipation is shown in Figure 53 and is calculated by Equation 1: TMAX - TA ) PD = ( q JA (1) Where: PD = Maximum power dissipation of TLV246x (watts) TMAX = Absolute maximum junction temperature (150C) TA = Ambient free-air temperature (C) qJA = qJC + qCA qJC = Thermal coefficient from junction to case qCA = Thermal coefficient from case to ambient air (C/W) 2 Maximum Power Dissipation (W) 1.75 1.5 1.25 TJ = 150C PDIP Package Low-K Test PCB JA = 104C/W SOIC Package Low-K Test PCB JA = 176C/W MSOP Package Low-K Test PCB JA = 260C/W 1 0.75 0.5 0.25 SOT-23 Package Low-K Test PCB JA = 324C/W 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Free-Air Temperature, TA (C) Figure 53. Maximum Power Dissipation vs Free-Air Temperature Copyright (c) 2003-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 23 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 www.ti.com Macromodel Information Macromodel information provided was derived using Microsim PartsTM Release 8, the model generation software used with Microsim PSpiceTM. The Boyle macromodel (1) and subcircuit in Figure 54 were generated using the TLV246x typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): (1) * * * * * * 24 G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Submit Documentation Feedback * * * * * * Unity gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit Copyright (c) 2003-2010, Texas Instruments Incorporated Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1 TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008D - MARCH 2003 - REVISED SEPTEMBER 2010 99 EGND + FB RO2 R2 3 VDD + C2 6 7 + + ISS RSS CSS 9 VD VLIM + VB RP IN J1 8 GA GCM 53 10 2 DC J2 RO1 OUT IN + 1 11 12 92 54 C1 DP RD1 5 DLN DE + RD2 VE 90 HLIM + DLP 91 + VLP VLN + 4 GND .SUBCKT TLV246X 1 2 3 4 5 11 12 2.46034E-12 C1 7 10.0000E-12 6 C2 10 99 443.21E-15 CSS 53 DY 5 DC 54 5 DE DY 90 91 DX DLP 92 90 DX DLN 3 4 DP DX POLY (2) (3,0) (4,0) 0 .5 .5 EGND 99 0 99 POLY (5) VB VC VE VLP 7 FB + VLN 0 21.600E6 - 1E3 1E3 22E6 - 22E6 0 6 12 345.26E- 6 11 GA 10 99 15.4226E- 9 6 GCM 0 DC 18.850E- 6 10 4 ISS VLIM 1K HLIM 90 0 10 JX1 J1 11 2 10 JX2 12 1 J2 9 6 100.00E3 R2 11 2.8964E3 3 RD1 12 2.8964E3 3 RD2 5.6000 5 8 R01 99 6.2000 7 R02 4 8.9127 3 RP 99 10.610E6 10 RSS 9 0 DC 0 VB 53 3 VC DC .7836 4 VE 54 DC .7436 8 DC 0 7 VLIM 0 DC 117 VLP 91 0 92 DC 117 VLN .MODEL DX D (IS=800.00E-18) .MODEL DY D (IS=800.00E-18 Rs = 1m Cjo=10p) .MODEL JX1 NJF (IS=1.0000E-12 BETA=6.3239E-3 + VTO=-1 ) .MODEL JX2 NJF (IS=1.0000E-12 BETA=6.3239E-3 + VTO=-1 ) .ENDS .subckt TLV_246Y 1 2 3 4 5 6 11 12 2.4603E-12 c1 72 7 10.000E-12 c2 10 99 443.21E-15 css 70 53 dy dc 54 70 dy de 90 91 dx dlp 92 90 dx dln 4 dp 3 dx poly(2) (3,0) (4,0) 0 .5 .5 egnd 99 0 99 poly(5) vb vc ve vlp vln 0 7 fb 21.600E6 - 1E3 1E3 22E6 - 22E6 72 0 ga 11 12 345.26E- 6 gcm 0 72 10 99 15.422E- 9 dc 18.850E- 6 74 iss 4 vlim 1K hlim 90 0 j1 11 2 10 jx1 10 jx2 j2 12 1 100.00E3 r2 72 9 3 rd1 11 2.8964E3 3 12 2.8964E3 rd2 ro1 8 70 5.6000 ro2 7 99 6.2000 rp 8.9127 3 71 rss 10.610E6 99 10 rs1 6 4 1G rs2 4 6 1G rs3 4 6 1G rs4 4 6 1G s1 4 71 6 4 s1x 5 s2 70 6 4 s1x 74 s3 10 6 4 s1x 4 s4 6 4 s2x 74 0 9 dc 0 vb vc 53 3 dc .7836 ve 4 dc .7436 54 vlim 8 7 dc 0 vlp 0 91 dc 117 0 92 dc 117 vln .model dx D(Is=800.00E-18) .model dy D(Is=800.00E-18 Rs=1m Cjo=10p) .model jx1 NJF(Is=1.0000E-12 Beta=6.3239E-3 Vto=-1) .model jx2 NJF(Is=1.0000E-12 Beta=6.3239E-3 Vto=-1) .model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0) .model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5) .ends Figure 54. Boyle Macromodel and Subcircuit Copyright (c) 2003-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1 25 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) TLV2460AQDRG4Q1 ACTIVE Package Type Package Drawing SOIC Pins Package Qty D 8 2500 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) TLV2460AQDRQ1 ACTIVE SOIC D 8 TLV2460AQPWRG4Q1 ACTIVE TSSOP PW 8 TLV2460AQPWRQ1 ACTIVE TSSOP PW 8 TLV2460QDRG4Q1 ACTIVE SOIC D 8 TLV2460QDRQ1 ACTIVE SOIC D 8 TLV2460QPWRG4Q1 ACTIVE TSSOP PW 8 TLV2460QPWRQ1 ACTIVE TSSOP PW 8 TLV2461AQDRG4Q1 ACTIVE SOIC D 8 TLV2461AQDRQ1 ACTIVE SOIC D 8 TLV2461AQPWRG4Q1 ACTIVE TSSOP PW 8 TLV2461AQPWRQ1 ACTIVE TSSOP PW 8 TLV2461QDRG4Q1 ACTIVE SOIC D 8 TLV2461QDRQ1 ACTIVE SOIC D 8 TLV2461QPWRG4Q1 ACTIVE TSSOP PW 8 Eco Plan (2) TBD TBD TBD 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) TBD TBD TBD TBD 2000 Green (RoHS & no Sb/Br) TBD Lead/ Ball Finish MSL Peak Temp Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM TLV2461QPWRQ1 ACTIVE TSSOP PW 8 TLV2462AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2462AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2462AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2462AQPWRQ1 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Call TI Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM Call TI (3) Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 17-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TLV2462QDGKRQ1 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV2462QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2462QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2462QPWRG4Q1 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) TLV2462QPWRQ1 ACTIVE TSSOP PW 8 TLV2463AQDRG4Q1 ACTIVE SOIC D 14 TLV2463AQDRQ1 ACTIVE SOIC D 14 TLV2463AQPWRG4Q1 ACTIVE TSSOP PW 14 TLV2463AQPWRQ1 ACTIVE TSSOP PW 14 TLV2463QDRG4Q1 ACTIVE SOIC D 14 TLV2463QDRQ1 ACTIVE SOIC D 14 TLV2463QPWRG4Q1 ACTIVE TSSOP PW 14 TBD TBD 2000 Green (RoHS & no Sb/Br) TBD 2500 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) TBD TBD Call TI Samples (Requires Login) Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU Level-1-260C-UNLIM TLV2463QPWRQ1 ACTIVE TSSOP PW 14 TLV2464AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Call TI Call TI TLV2464AQPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1, TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 : * Catalog: TLV2460, TLV2460A, TLV2461, TLV2461A, TLV2462, TLV2462A, TLV2463, TLV2463A, TLV2464A * Enhanced Product: TLV2462A-EP, TLV2464A-EP * Military: TLV2460M, TLV2460AM, TLV2461M, TLV2461AM, TLV2462M, TLV2462AM, TLV2463M, TLV2463AM NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV2462QDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2462QDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2462QDGKRQ1 VSSOP DGK 8 2500 364.0 364.0 27.0 TLV2462QDGKRQ1 VSSOP DGK 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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