ACPL-H342-000E - Avago Technologies

ACPL-H342 and ACPL-K342

2.5 Amp Output Current IGBT Gate Drive Optocoupler

with Active Miller Clamp, Rail-to-Rail Output Voltage

and UVLO in Stretched SO8

Data Sheet

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

Description

The ACPL-H342/ACPL-K342 contains an AlGaAs LED,

which is optically coupled to an integrated circuit with a

power output stage. This optocoupler is ideally suited for

driving power IGBTs and MOSFETs used in motor control

inverter applications. The high operating voltage range of

the output stage provides the drive voltages required by

gate controlled devices. The voltage and high peak output

current supplied by this optocoupler make it ideally suited

for direct driving IGBT with ratings up to 1200V/150A. For

IGBTs with higher ratings, the ACPL-H342/ACPL-K342 can

be used to drive a discrete power stage which drives the

IGBT gate. The ACPL-H342 and ACPL-K342 have the highest

insulation voltage of VIORM = 891Vpeak and 1140Vpeak

respectively in the IEC/ EN/DIN EN 60747-5-5.

Functional Diagram

Features

 2.5 A Maximum Peak Output Current

 2.0A Minimum Peak Output Current

 Built-in Active Miller Clamp

 Rail-to-Rail Output Voltage

 Fast Propagation Delay to minimize Dead Time

 t

PHL < tPLH to provide “Anti-Cross” Conduction

 LED input threshold current hysteresis

 I

CC = 2.5 mA Maximum Supply Current to allow boot-

strap power supply

 Under Voltage Lock-Out Protection (UVLO) with

Hysteresis

 40 kV/s Minimum Common Mode Rejection (CMR) at

VCM = 1500 V

 Wide Operating VCC Range: 15 to 30 Volts

 Industrial Temperature Range: -40°C to 105°C

 Safety Approval:

– UL Recognized 3750/5000 VRMS for 1min.

– CSA

– IEC/EN/DIN EN 60747-5-5 VIORM = 891/1140 Vpeak

Applications

 IGBT/MOSFET Gate Drive

 AC and Brushless DC Motor Drives

 Renewable Energy Inverters

 Industrial Inverters

 Switching Power Supplies

VCC

VOUT

VCLAMP

VEE

CATHODE

ANODE

CLAMP

Note: Design Note: A 1 F bypass capacitor must be connected between

pins VCC and VEE.

Truth Table

LED

VCC – VEE

“POSITIVE GOING”

(i.e., TURN-ON)

VCC – VEE

“NEGATIVE GOING”

(i.e., TURN-OFF) VOVCLAMP

OFF 0 – 30V 0 – 30V LOW LOW

ON 0 – 11V 0 – 9.5V LOW LOW

ON 11 – 13.5V 9.5 – 12V TRANSITION TRANSITION

ON 13.5 – 30V 12 – 30V HIGH Hi-Z

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Ordering Information

ACPL-H342 is UL Recognized with 3750 VRMS for 1 minute per UL1577.

ACPL-K342 is UL Recognized with 5000 VRMS for 1 minute per UL1577.

Part number

Option

(RoHS Compliant) Package

Surface

Mount

Tape &

Reel

UL 5000 VRMS /1

Minute rating

IEC/EN/DIN EN

60747-5-5 Quantity

ACPL-H342 -000E Stretched

SO-8

X 80 per tube

-500E X X 1000 per reel

-060E X X 80 per tube

-560E X X X 1000 per reel

ACPL-K342 -000E Stretched

SO-8

X X 80 per tube

-500E X X X 1000 per reel

-060E X X X 80 per tube

-560E X X X X 1000 per reel

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry.

Example 1:

ACPL-H342-560E to order product of Stretched SO-8 Surface Mount package in Tape and Reel packaging with IEC/EN/

DIN EN 60747-5-5 Safety Approval and RoHS compliant.

Example 2:

ACPL-K342-000E to order product of Stretched SO-8 Surface Mount package in Tube packaging with UL 5000 VRMS/1

minute and RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Lead Coplanarity = 0.1mm [0.004 Inches]

Floating Lead protusions max. 0.25 [0.0]

Dimensions in Millimeters [Inches]

0.381 + 0.127

0.015 + 0.005

5.850 + 0.254

0.230 + 0.010

0.450

0.018

7.620

0.300

6.807

0.268

1.270

0.050

7°

45°

5° NOM.

1.590 ±0.127

0.063 ±0.005

0.200 ±0.100

0.008 ±0.004

1 ±0.250

0.040 ±0.010 9.7 ±0.25

0.382 ±0.010

0.254 ±0.050

0.010 ±0.002

3.180 ±0.127

0.125 ±0.005

10.7

(0.421)

1.27 (0.05)

0.76 (0.03)

2.16

(0.085)

Land Pattern Recommendation

Lead Coplanarity = 0.1mm [0.004 Inches]

Floating Lead protusions max. 0.25 [0.0]

Dimensions in Millimeters [Inches]

5.850 + 0.25

0.230 + 0.010

 0.000

¬º

0.450

0.018

¬º

7.62

0.300

¬º

35° NOM.

0.381 ±0.13

0.015 ±0.005

¬º

6.807 ±0.127

0.268 ±0.005

¬º

¼1.590 ±0.127

0.063 ±0.005

¬º

¼3.180 ±0.127

0.125 ±0.005

¬º

0.254 ±0.050

0.010 ±0.002

¬º

11.5 ±0.250

0.453 ±0.010

¬º

7°

7° 45°

0.200 ±0.100

0.008 ±0.004

¬º

0.750 ±0.25

0.0295 ±0.01

¬º

7°

1.270BSG

0.050

¬º

12.65

(0.5)

1.27 (0.05)

0.76 (0.03)

1.905

(0.075)

Land Pattern Recommendation

Package Outline Drawings

ACPL-H342 Outline Drawing

ACPL-K342 Outline Drawing

Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-H342 / ACPL-K342 Option 060)

Description Symbol

ACPL-H342

Option 060

ACPL-K342

Option 060 Unit

Installation classi cation per DIN VDE 0110/39, Table 1

for rated mains voltage  150 Vrms

for rated mains voltage  300 Vrms

for rated mains voltage  450 Vrms

I – IV

I – III

I – IV

for rated mains voltage  600 Vrms I – III I – IV

for rated mains voltage  1000 Vrms I – III

Climatic Classi cation 40/105/21 40/105/21

Pollution Degree (DIN VDE 0110/39) 2 2

Maximum Working Insulation Voltage VIORM 891 1140 Vpeak

Input to Output Test Voltage, Method b*

VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC

VPR 1671 2137 Vpeak

Input to Output Test Voltage, Method a*

VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC

VPR 1426 1824 Vpeak

Highest Allowable Overvoltage*

(Transient Overvoltage tini = 60 sec)

VIOTM 6000 8000 Vpeak

Safety-limiting values – maximum values allowed in the event of a failure

Case Temperature

Input Current

Output Power

IS, INPUT

PS, OUTPUT

175

230

600

175

230

600

°C

Insulation Resistance at TS, VIO = 500 V RS>109>109

* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/

DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test pro les.

Note:

These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by

means of protective circuits. Surface mount classi cation is Class A in accordance with CECC 00802.

Recommended Pb-Free IR Pro le

Recommended re ow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used.

Regulatory Information

The ACPL-H342 / ACPL-K342 is approved by the following organizations:

Recognized under UL 1577, component recognition program up to VISO = 3750 VRMS (ACPL-H342) and VISO = 5000 VRMS

(ACPL-K342), File 55361

CSA

CSA Component Acceptance Notice #5, File CA 88324

IEC/EN/DIN EN 60747-5-5 (ACPL-H342/K342 Option 060 Only)

Maximum Working Insulation Voltage Viorm = 891Vpeak (ACPL-H342) and Viorm = 1140 Vpeak(ACPL-K342)

Table 2. Insulation and Safety Related Speci cations

Parameter Symbol ACPL-H342 ACPL-K342 Units Conditions

Minimum External Air Gap

(Clearance)

L(101) 7.0 8.0 mm Measured from input terminals to output

terminals, shortest distance through air.

Minimum External Tracking

(Creepage)

L(102) 8.0 8.0 mm Measured from input terminals to output

terminals, shortest distance path along body.

Minimum Internal Plastic Gap

(Internal Clearance)

0.08 0.08 mm Through insulation distance conductor to

conductor, usually the straight line distance

thickness between the emitter and detector.

Tracking Resistance

(Comparative Tracking Index)

CTI > 175 > 175 V DIN IEC 112/VDE 0303 Part 1

Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Notes:

1. All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting

point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board,

minimum creepage and clearance requirements must be met as speci ed for individual equipment standards. For creepage, the shortest distance

path along the surface of a printed circuit board between the solder  llets of the input and output leads must be considered (the recommended

Land Pattern does not necessarily meet the minimum creepage of the device). There are recommended techniques such as grooves and ribs which

may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending

on factors such as pollution degree and insulation level.

Table 3. Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note

Storage Temperature TS-55 125 °C

Operating Temperature TA-40 105 °C

Output IC Junction Temperature TJ125 °C

Average Input Current IF(AVG) 25 mA 1

Peak Transient Input Current

(<1 s pulse width, 300pps)

IF(TRAN) 1A

Reverse Input Voltage VR5V

“High” Peak Output Current IOH(PEAK) 2.5 A 2

“Low” Peak Output Current IOL(PEAK) 2.5 A 2

Peak Clamp Sink Current ICLAMP 2.5 A 2

Total Output Supply Voltage (VCC - VEE) 0 35 V

Output Voltage VO(PEAK) -0.5 VCC V

Output IC Power Dissipation PO210 mW 3

Total Power Dissipation PT255 mW 4

Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane

Table 4. Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note

Operating Temperature TA- 40 105 °C

Output Supply Voltage (VCC - VEE)1530V

Input Current (ON) IF(ON) 716mA

Input Voltage (OFF) VF(OFF) - 3.6 0.8 V

Table 5. Electrical Speci cations (DC)

Unless otherwise noted, all typical values are at TA = 25°C, VCC - VEE = 30 V, VEE = Ground; all Minimum/Maximum speci-

 cations are at Recommended Operating Conditions (TA = -40 to 105°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC =

15 to 30 V, VEE = Ground).

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

High Level Peak Output Current IOH -0.5 -1.2 A VO = VCC – 4 3, 4, 23 5

-2.0 A VO = VCC – 15 2

Low Level Peak Output Current IOL 0.5 2.7 A VO = VEE + 2.5V 6, 7, 24 5

2.0 A VO = VEE + 15V 2

High Output Transistor RDS(ON) RDS,OH 2.6 5.0 IOH = -2.0A 8

Low Output Transistor RDS(ON) RDS,OL 0.8 2.0 IOL = 2.0A 9

Clamp Output Peak Current ICLAMP 1.0 2.5 A VO = VEE + 2.5 14, 16,

Clamp Pin Threshold VtCLAMP 2.3 V 15,16,

Clamp Output Transistor

RDS(ON)

RDS,CLAMP 0.8 2.0 ICLAMP = 1.5 A

High Level Output Voltage VOH VCC-2.0 VCC-0.80 V IO = -100 mA 2, 4, 25 6, 7

High Level Output Voltage VOH VCC VI

O = 0 mA , IF=10 mA 1

Low Level Output Voltage VOL 0.07 0.25 V IO = 100 mA 5, 7, 26

High Level Supply Current ICCH 1.68 2.5 mA Rg = 10,

Cg = 25 nF, IF = 10 mA,

10, 11

Low Level Supply Current ICCL 2.0 2.5 mA Rg = 10,

Cg = 25 nF, IF = 0 mA

Threshold Input Current

Low to High

IFLH 0.5 1.5 4.0 mA Rg = 10,

Cg = 25 nF, VO > 5 V

12, 13,

Threshold Input Voltage

High to Low

VFHL 0.8 V

Input Forward Voltage VF1.2 1.55 1.95 V IF = 10 mA 22

Temperature Coe cient of

Input Forward Voltage

VF/TA-1.7 mV/°C

Input Reverse Breakdown

Voltage

BVR5V

IR = 100 A

Input Capacitance CIN 70 pF f = 1 MHz, VF = 0 V

UVLO Threshold VUVLO+ 11.0 12.3 13.5 V VO > 5 V, IF = 10 mA 30

VUVLO- 9.5 10.7 12.0

UVLO Hysteresis UVLOHYS 1.4

Table 6. Switching Speci cations (AC)

Unless otherwise noted, all typical values are at TA = 25°C, VCC - VEE = 30 V, VEE = Ground; all Minimum/Maximum speci-

 cations are at Recommended Operating Conditions (TA = -40 to 105°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC =

15 to 30 V, VEE = Ground).

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

Propagation Delay Time to

High Output Level

tPLH 0.100 0.260 0.350 sR

g = 10,

Cg = 25 nF,

f = 20 kHz ,

Duty Cycle = 50%,

IF = 7 mA to 16 mA,

VCC = 15 V to 30V

17, 18,

19, 20,

21, 31

Propagation Delay Time to

Low Output Level

tPHL 0.050 0.145 0.250 s

Propagation Delay Di erence

Between Any Two Parts

PDD

(tPHL - tPLH)

-0.010 -0.100 -0.200 s39, 40 11

Rise Time tR22 ns VCC = 30V 31

Fall Time tF18 ns

Output High Level Common

Mode Transient Immunity

|CMH|40 50 kV/sTA = 25°C, IF = 10 mA,

VCC = 30 V, VCM = 1500

V with split resistors

32 12, 13

25 35 TA = 25°C, IF = 10 mA,

VCC = 30 V, VCM = 1000

V without split resistors

Output Low Level Common

Mode Transient Immunity

|CML|40 50 kV/sTA = 25°C, VF = 0 V,

VCC = 30 V, VCM = 1500

V with split resistors,

32 12, 14

25 35 TA = 25°C, VF = 0 V,

VCC = 30 V, VCM = 1000

V without split resistors

Table 7. Package Characteristics

Unless otherwise noted, all typical values are at TA = 25°C; all Minimum/Maximum speci cations are at Recommended

Operating Conditions.

Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note

Input-Output Momentary

Withstand Voltage*

VISO ACPL-H342 3750 VRMS RH < 50%,

t = 1 min., TA = 25°C

8,10

ACPL-K342 5000 VRMS RH < 50%,

t = 1 min., TA = 25°C

9,10

Input-Output Resistance RI-O >5012 VI-O = 500 VDC 10

Input-Output Capacitance CI-O 0.2 pF f =1 MHz

LED-to-Ambient Thermal

Resistance

R11 311 °C/W Thermal Model in

Application Notes

Below

LED-to-Detector Thermal

Resistance

R12, R21 111

Detector-to-Ambient

Thermal Resistance

R22 168

* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating, refer to your equipment level safety speci cation or Avago Technologies Application Note 1074

entitled “Optocoupler Input-Output Endurance Voltage.”

Notes:

1. Derate linearly above 70°C free-air temperature at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10s

3. Derate linearly above 85°C free-air temperature at a rate of 5.5 mW/°C.

4. Derate linearly above 85°C free-air temperature at a rate of 6.3 mW/°C. The maximum LED junction temperature should not exceed 125°C.

5. Maximum pulse width = 50 μs.

6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.

7. Maximum pulse width = 1 ms.

8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection

current limit, II-O 5 A).

9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 6000 Vrms for 1 second (leakage detection

current limit, II-O 5 A).

10. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.

11. The di erence between tPHL and tPLH between any two ACPL-H342 parts under the same test condition.

12. Pins 2 and 4 need to be connected to LED common.

13. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output

will remain in the high state (i.e., VO > 15.0 V).

14. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output

will remain in a low state (i.e., VO < 1.0 V).

15. This load condition approximates the gate load of a 1200V/150A IGBT.

Figure 2. VOH vs. temperature.Figure 1. High Ouput Rail Voltage vs. Temperature.

Figure 4. IOH vs. VOH.Figure 3. IOH vs. temperature.

Figure 6. IOL vs. temperature.Figure 5. VOL vs. temperature.

29.966

29.967

29.968

29.969

29.97

29.971

29.972

29.973

29.974

29.975

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

VOH - HIGH OUTPUT RAIL VOLTAGE- V

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

IOH - OUTPUT HIGH CURRENT - A

VOL - OUTPUT LOW VOLTAGE - V

IOL - OUTPUT LOW CURRENT - A

-2.50

-2.00

-1.50

-1.00

-0.50

0.00

0.00 1.00 2.00 3.00 4.00 5.00 6.00

(VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V

IOH - OUTPUT HIGH CURRENT - A

0.02

0.04

0.06

0.08

0.1

0.12

0.5

1.5

2.5

3.5

IF = 10 mA

VCC = 30 V

VEE = 0 V

(VOH - VCC) - HIGH OUTPUT

VOLTAGE DROP - V

IF = 10 mA

IOUT = -100 mA

VCC = 15 to 30 V

VEE = 0 V

IF = 10 mA

VOUT = (VCC  4 V)

VCC = 15 to 30 V

VEE = 0 V

TA = 25°C

VF(OFF) = 0 V

VOUT = 2.5 V

VCC = 15 to 30 V

VEE = 0 V

VF(OFF) = 0 V

IOUT = 100 mA

VCC = 15 to 30 V

VEE = 0 V

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Figure 8. RDS,OH vs. temperature.Figure 7. IOL vs. VOL

Figure 10. ICC vs. temperarure.Figure 9. RDS,OL vs. temperature.

Figure 12. IFLH hysteresis.Figure 11. ICC vs. VCC.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0123

VOL - OUTPUT LOW VOLTAGE - V

IOL - OUTPUT LOW CURRENT - A

0.5

1.5

2.5

3.5

RDS,OH - HIGH OUTPUT

TRANSISTOR RDS(ON) - Ω

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

RDS,OL - LOW OUTPUT TRANSISTOR

RDS (ON) - Ω

0.5

1.5

2.5

ICC - SUPPLY CURRENT -mA

0.5

1.5

2.5

15 20 25 30

VCC - SUPPLY VOLTAGE - V

ICC - SUPPLY CURRENT - mA

0.0 0.5 1.0 1.5 2.0 2.5 3.0

IFLH - LOW TO HIGH CURRENT THRESHOLD - mA

VO - OUTPUT VOLTAGE- V

VF(OFF) = 0 V

IOUT = 2 A

VCC = 15 to 30 V

VEE = 0 V

TA = 25°C

VCC = 30 V

VEE = 0 V

IF = 10 mA

IOUT = -2 A

VCC = 15 to 30 V

VEE = 0 V

ICCH

ICCL

IFLH ON

IFLH OFF

ICCH

ICCL

TA = 25°C

VF(OFF) = 0 V

IF = 10 mA for ICCH

IF = 0 mA for ICCL

VCC = 30 V

VEE = 0 V

IF = 10 mA for ICCH

IF = 0 mA for ICCL

TA = 25°C

VEE = 0 V

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

Figure 14. ICLAMP vs. temperature.Figure 13. IFLH vs. temperature.

Figure 16. ICLAMP vs. VtCLAMP

.Figure 15. VtCLAMP vs. temperature.

Figure 18. Propagation delay vs. IF.Figure 17. Propagation delay vs. VCC.

0.0

0.5

1.0

1.5

2.0

2.5

IFLH - LOW TO HIGH CURRENT

THRESHOLD - mA

0.5

1.5

2.5

3.5

ICLAMP - CLAMP OUTPUT PEAK CURRENT - A

0.5

1.5

2.5

3.5

VtCLAMP - CLAMP PIN THRESHOLD - V

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 0.5 1 1.5 2 2.5

VtCLAMP - CLAMP PIN THRESHOLD - V

ICLAMP - CLAMP OUTPUT PEAK CURRENT - A

100

150

200

250

300

15 20 25 30

VCC - SUPPLY VOLTAGE - V

TP - PROPAGATION DELAY - ns

100

150

200

250

300

6 8 10 12 14 16

IF - FORWAR LED CURRENT - mA

TP - PROPAGATION DELAY - ns

IFLH ON

IFLH OFF

TPHL

TPLH

VCC = 30 V, VEE = 0 V

TA = 25°C

Rg = 10 Ω, Cg = 25 nF

DUTY CYCLE = 50%

f = 20 kHz

TPHL

TPLH

VCC = 15 to 30 V

VEE = 0 V

VOUT = 2.5 V

VCC = 15 to 30 V

VEE = 0 V

VCC = 15 V

VEE = 0 V

TA = 25°C

IF = 7 mA

TA = 25°C

Rg = 10 Ω, Cg = 25 nF

DUTY CYCLE = 50%

f = 20 kHz

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

Figure 20. Propagation delay vs. Rg.Figure 19. Propagation delay vs. temperature.

Figure 22. Input current vs. forward voltage.Figure 21. Propagation delay vs. Cg.

100

150

200

250

300

350

TP - PROPAGATION DELAY - ns

100

150

200

250

300

Rg - SERIES LOAD RESISTANCE - Ω

TP - PROPAGATION DELAY - ns

100

150

200

250

300

0 5 10 15 20 25 30 35 40 45 50

Cg - LOAD CAPACITANCE - nF

TP - PROPAGATION DELAY - ns

0.1

100

1.4 1.45 1.5 1.55 1.6 1.65

VF - FORWARD VOLTAGE - VOLTS

IF - FORWARD CURRENT - mA

IF = 7 mA

VCC = 30 V, VEE = 0 V

Rg = 10 Ω, Cg = 25 nF

DUTY CYCLE = 50%

f = 20 kHz

TPHL

TPLH

VCC = 30 V, VEE = 0 V

IF = 7 mA, TA = 25°C

Cg = 25 nF

DUTY CYCLE = 50%

f = 20 kHz

TPLH

TPHL

TPLH

TPHL

VCC = 30 V, VEE = 0 V

IF = 7 mA, TA = 25°C

Rg = 10 Ω

DUTY CYCLE = 50%

f = 20 kHz

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

TA - TEMPERATURE - °C

0 5 10 15 20 25 30 35 40 45 50

IF = 10mA +

1PF

4V Pulsed

IOH

VCC = 15 to 30V

CLAMP

1PF

2.5V

Pulsed

IOL

VCC = 15 to 30V

CLAMP

IF = 10mA +

1PF

100mA

VCC = 15 to 30V

VOH

CLAMP

1PF100mA VCC = 15 to 30V

VOL

CLAMP

Figure 23. IOH test circuit.

Figure 24. IOL test circuit.

Figure 25. VOH test circuit.

Figure 26. VOL test circuit.

1PF

2.5V Pulsed

ICLAMP

VCC = 15 to 30V

CLAMP

1PF

VCC = 15 to 30V

1k:

VtCLAMP +

CLAMP

IF+

1PFVCC = 15 to 30V

VO > 5V

10:

25nF

CLAMP

IF = 10mA +

1PF

VO > 5V

CLAMP

Figure 27. ICLAMP test circuit.

Figure 28. VtCLAMP test circuit.

Figure 29. IFLH test circuit.

Figure 30. UVLO test circuit.

Figure 31. tPLH, tPHL, tr and tf test circuit and waveforms.

Figure 32. CMR test circuit with split resistors network and waveforms.

Application Information

Product Overview Description

The ACPL-H342/K342 is an optically isolated power output

stage capable of driving IGBTs of up to 150 A and 1200

V. It has very high CMR rating which allows the micro-

controller and the IGBT to operate at very large common

mode noise found in industrial motor drives and other

power switching applications. And to achieve better

system reliability in such noisy environment, this power

control device incorporates new features like Active Miller

clamp, Rail-to-Rail output voltage, Anti-cross conduction

and LED input current hysteresis.

Active Miller clamp function eliminates the need of

negative gate drive in most application and allows the

use of simple bootstrap supply for high side driver. Rail-to-

Rail output voltage ensures that the IGBT’s gate voltage is

driven to the optimum intended level with no power loss

across IGBT. Anti-cross conduction prevents current shoot

through between the high and low side of half bridge

IGBT con guration. This will help to simplify the controller

design in terms of having to account for the delay needed

at the LED input. And lastly, the LED input current hyster-

esis prevents output oscillation if insu cient LED driving

current is applied. This will eliminates the need of addi-

tional Schmitt trigger circuit at the input LED.

This feature rich IGBT gate driver is designed to increase the

performance and reliability of a motor drive without the

cost, size, and complexity of external circuitry or control.

Recommended Application Circuit

The recommended application circuit shown in Figure 33

illustrates a typical gate drive implementation using the

ACPL-H342. The following describes about driving IGBT.

However, it is also applicable to MOSFET. Designers will

need to adjust the VCC supply voltage, depending on the

MOSFET or IGBT gate threshold requirements (Recom-

mended VCC = 18V for IGBT and 12V for MOSFET).

The supply bypass capacitors (1 μF) provide the large

transient currents necessary during a switching transition.

Because of the transient nature of the charging currents,

a low current (2.5mA) power supply will be enough to

power the device. The split resistors across the LED will

provide a high CMR response by providing a balanced re-

sistance network across the LED.

The gate resistor RG serves to limit gate charge current

and controls the IGBT collector voltage rise and fall times.

In PC board design, care should be taken to avoid routing

the IGBT collector or emitter traces close to the ACPL-H342

input as this can result in unwanted coupling of transient

signals into ACPL-H342 and degrade performance.

IF = 7 to 16mA,

20kHz, 50% Duty

Cycle +

1PF

10:

25nF

VCC = 15 to 30V

VCLAMP

OUT

PHL

PLH

10%

50%

90%

5 V +

1PF

VCM = 1500V

170 ohm

_VCC = 30V

VCLAMP

VCM

Δt

0 V

SWITCH AT B: IF = 0 mA

SWITCH AT A: IF = 10 mA

VOL

VOH

Δt

VCM

δV

δt =

Figure 33. Recommended application circuit with split resistors LED drive and active Miller Clamp.

VCC

VOUT

VCLAMP

VEE

CATHODE

ANODE

VCE

+ HVDC

-HVDC

3-PHASE

VCE

1μF

VCC=18V

Active Miller Clamp

A Miller clamp allows the control of the Miller current

during a high dV/dt situation. And it can also eliminate

the use of a negative supply voltage by quickly discharg-

ing the large gate capacitance of IGBT to low level without

a ecting the IGBT turn-o characteristics. During turn-o ,

the gate voltage is monitored and the clamp output is

activated when gate voltage goes below 2.3V (relative to

VEE). The clamp voltage is VOL+2.5V typ for a Miller current

up to 2.5 A. The clamp is disabled when the LED input is

triggered again.

AN5314 application note describes how the clamp reduces

the parasitic turn-on e ect due to the Miller capacitor and

at the same time eliminates the need of a negative power

supply.

The Miller pin should be connected to VEE when not in use.

Rail-to-Rail Output

Figure 34 shows a typical gate driver’s high current

output stage with 3 bipolar transistors in darlington con-

 guration. During the output high transition, the output

voltage rises rapidly to within 3 diode drops of VCC. To

ensure the VOUT is at VCC in order to achieve IGBT rated

VCE(ON) voltage. The level of VCC will be need to be raised

to beyond VCC+3(VBE) to account for the diode drops. And

to limit the output voltage to VCC, a pull-down resistor,

RPULL-DOWN between the output and VEE is recommended

to sink a static current while the output is high.

ACPL-H342 uses a power NMOS follower stage to deliver

the initial large current and a smaller PMOS to pull it to VCC

to achieve Rail-to-Rail output voltage as shown in Figure

35. This ensures that the IGBT’s gate voltage is driven to

the optimum intended level with no power loss across

IGBT even when an unstable power supply is used.

Figure 34. Typical gate driver with output stage in darlington con guration

Figure 35. ACPL-H342 with NMOS and PMOS output stage for Rail-to-Rail output voltage

VCC

VOUT

VEE

CATHODE

ANODE

RPULL-DOWN

VCC

VOUT

VCLAMP

VEE

CATHODE

ANODE

VCLAMP

Selecting the Gate Resistor (Rg)

Step 1: Calculate Rg minimum from the IOL peak speci cation. The IGBT and Rg in Figure 33 can be analyzed as a simple

RC circuit with a voltage supplied by ACPL-H342/K342.

g ≥ VCC  VEE  VOL

IOLPEAK

= 6.28 7

18V  0V  2.3V

2.5A

The VOL value of 2.3V in the previous equation is the VOL at the peak current of 2.5A (see Figure 7).

Step 1: Check the ACPL-H342/K342 power dissipation and increase Rg if necessary. The ACPL-H342/K342 total power dis-

sipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO).

PT = PE + PO

PE = IF • VF • Duty Cycle

PO = PO(BIAS) + PO(SWITCHING)

= ICC • (VCC-VEE) + ESW(Rg;Qg) • f

Using IF(worst case) = 16mA, Rg = 7, Max Duty Cycle = 80%, Qg = 500nC, f = 25kHz and TA max = 85°C:

PE = 16mA • 1.95V • 0.8 = 25mW

PO = 2.5mA • 18V + 4μJ • 25 kHz

= 45mW + 100mW

= 145mW < 210mW (PO(MAX) @ 85°C)

The value of 2.5mA for ICC in the previous equation is the maximum ICC over the entire operating temperature range.

Since PO is less than PO(MAX), Rg = 7 is alright for the power dissipation.

0 1020304050

Rg - GATE RESISTANCE - Ω

Esw - ENERGY PER SWITCHING CYCLE - μJ

Qg = 100nc

Qg = 500nc

Qg = 1000nc

Figure 36. Energy Dissipated in the ACPL-H342/K342 for each IGBT switching cycle.

Anti-Cross Conduction to Prevent Current Shoot Through and Determining Dead Time

The ACPL-H342 includes a Propagation Delay Di erence (PDD = tPHL – tPLH ) speci cation to help prevent both the

high(Q1) and low(Q2) side power transistors from turning on at the same time. This “Anti-Cross” conduction feature

prevents large currents from  owing through the power transistors by ensuring tPHLMAX is faster than tPLHMIN. In another

words, the “Anti-Cross” feature will ensure one power transistor is turned o before the other is turned on.

A gate driver without Anti-Cross feature will for example has a PDDMIN of -350ns and a PDDMAX of 350ns. A positive

PDDMAX of 350ns would mean one transistor will be turn on before the other is o since tPHLMAX is longer than tPLHMIN.

This is shown in Figure 37. To prevent this and the shoot through current, the turn on of LED2 should be delayed (relative

to the turn o of LED1) so that under worst-case conditions, Q1 has just turned o when Q2 turns on. The amount of

delay to achieve this condition is equal to PDDMAX as shown in Figure 38.

+ HVDC

-HVDC

High Side PWM

Low Side PWM

LED1

LED2

VOUT1

VOUT2

ILED1

ILED2

VOUT1

VOUT2

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

tPHLMAX

tPLHMIN

Shoot

Through

ILED1

ILED2

VOUT1

VOUT2

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

tPHLMAX

tPLHMIN

PDDMAX = tPHLMAX - tPLHMIN = 350 ns

Figure 38. Adding delay to prevent shoot throughFigure 37. Current shoot through without Anti-Cross feature

The ACPL-H342 with the Anti-Cross feature has a PDDMIN

of -10ns and a PDDMAX of -200ns. Since the PDD is always

a negative value, the tPHLMAX is always faster than tPLHMIN.

Thus this simpli ed the design without having to add any

amount of delay for the input LEDs as shown in Figure 39.

Symbol Min. Typ. Max. Units

tPLH 0.100 0.260 0.350 s

tPHL 0.050 0.145 0.250 s

PDD (tPHL - tPLH) -0.010 -0.100 -0.200 s

Q1 OFF

Q2 ON

ILED1

ILED2

VOUT1

VOUT2

Q1 ON

Q2 OFF

tPHLMAX

tPLHMIN

PDDMIN = -10 ns

= Minimum Dead Time

tPLHMAX

ILED1

ILED2

VOUT1

VOUT2

Q1 ON

Q2 OFF

Q1 OFF

tPHLMIN

tPLHMIN

tPLHMAX Q2 ON

PDDMAX = -200 ns

= Minimum Dead Time

Figure 40. Determining maximum dead time

Dead time is the time period during which both the

high(Q1) and low(Q2) side transistor are o . During this

time, no work is done and this reduces the e ciency of

the inverter or motor drive. The minimum and maximum

dead time is shown in Figure 39 and 40 and is equivalent

to the PDDMIN and PDDMAX . Due to the smaller PDD and

skewed propagation delay con guration, ACPL-H342

shows a smaller maximum dead time as compared to its

predecessor, HCPL-3120 as shown in  gure 41 and hence

an improve in e ciency. Note that the propagation delays

used to calculate PDD and dead time are taken at equal

temperature and test conditions since the optocou-

plers under consideration are typically mounted in close

proximity to each other and are switching identical IGBTs.

Figure 39. Anti-Cross to prevent shoot through

ILED1

ILED2

VOUT1

VOUT2

Q1 OFF

Q2 ON

tPLHMIN

Maximum Dead Time

= (tPHLMAX  tPHLMIN) + (tPLHMAX  tPLHMIN)

= (tPHLMAX  tPLHMIN) + (tPHLMIN  tPLHMAX)

= PDDMAX  PDDMIN

= 350  (-350) = 700 ns

tPLHMAX

Q1 ON

Q2 OFF

tPHLMAX

tPHLMIN

Figure 41. HCPL-3120 maximum dead time

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.

AV02-2526EN - September 5, 2012

LED Input Current Hysteresis

The detector has optical receiver input stage with built in

Schmitt trigger to provide logic compatible waveforms,

eliminating the need for additional wave shaping. The

hysteresis (Figure 12) provides di erential mode noise

immunity and minimizes the potential for output signal

chatter.

Under Voltage Lockout

The ACPL-H342 Under Voltage Lockout (UVLO) feature is

designed to prevent the application of insu cient gate

voltage to the IGBT by forcing the ACPL-H342 output low

during power-up. IGBTs typically require gate voltages of

15 V to achieve their rated VCE(ON) voltage. At gate voltages

below 13 V typically, the VCE(ON) voltage increases dra-

matically, especially at higher currents. At very low gate

voltages (below 10 V), the IGBT may operate in the linear

region and quickly overheat. The UVLO function causes

the output to be clamped whenever insu cient operating

supply (VCC) is applied. Once VCC exceeds VUVLO+ (the pos-

itive-going UVLO threshold), the UVLO clamp is released

to allow the device output to turn on in response to input

signals.

Thermal Model for ACPL-H342/K342 Stretched SO8

Package Optocoupler

De nitions:

R11: Junction to Ambient Thermal Resistance of LED due

to heating of LED

R12: Junction to Ambient Thermal Resistance of LED due

to heating of Detector (Output IC)

R21: Junction to Ambient Thermal Resistance of Detector

(Output IC) due to heating of LED.

R22: Junction to Ambient Thermal Resistance of Detector

(Output IC) due to heating of Detector (Output IC).

P1: Power dissipation of LED (W).

P2: Power dissipation of Detector / Output IC (W).

T1: Junction temperature of LED (°C).

T2: Junction temperature of Detector (°C).

TA: Ambient temperature.

Ambient Temperature: Junction to Ambient Thermal Re-

sistances were measured approximately 1.25cm above

optocoupler at ~23°C in still air

Thermal Resistance °C/W

R11 311

R12, R21 111

R22 168

This thermal model assumes that an 8-pin single-channel

plastic package optocoupler is soldered into a 7.62 cm x

7.62 cm printed circuit board (PCB) per JEDEC standards.

The temperature at the LED and Detector junctions of the

optocoupler can be calculated using the equations below.

T1 = (R11 * P1 + R12 * P2) + TA (1)

T2 = (R21 * P1 + R22 * P2) + TA (2)

Using the given thermal resistances and thermal model

formula in this datasheet, we can calculate the junction

temperature for both LED and the output detector. Both

junction temperature should be within the absolute

maxi mum rating.

For example, given P1 = 45 mW, P2 =210 mW, Ta = 85°C:

LED junction temperature,

T1 = (R11 * P1 + R12 * P2) + TA

= (311 * 0.045 + 111 * 0.210) + 85

= 122°C

Output IC junction temperature,

T2 = (R21 x P1 + R22 x P2) + TA

= (111 *0.045 + 168 * 0.210) + 85

= 125°C

T1 and T2 should be limited to 125°C based on the board

layout and part placement.

Related Application Noted

AN5336 – Gate Drive Optocoupler Basic Design for IGBT/

MOSFET

AN1043 – Common-Mode Noise: Sources and Solutions

AN02-0310EN – Plastics Optocouplers Product ESD and

Moisture Sensitivity