2010 Microchip Technology Inc. DS39592F-page 1
PIC18FX220/X320
1.0 DEVICE OVERVIEW
This docume nt includes the program ming sp ecifications
for the following devices:
• PIC18F1220
• PIC18F1320
• PIC18F2220
• PIC18F2320
• PIC18F4220
• PIC18F4320
2.0 PROGRAMMING OVERVIEW
These devices can be programmed using the high-
voltage In-Circuit Serial ProgrammingTM (ICSPTM)
method, or the low-v ol t age ICSP me tho d, bo th whi le in
the user’s system. The low-voltage ICSP method is
slightly different than the high-voltage method and
these differences are noted where applicable. This
programming specification applies to these devices in
all package types.
2.1 Hardware Requir ements
In High-Voltag e IC SP mode, these dev ices req uire tw o
programmable power supplies: one for VDD and one for
MCLR/VPP. Both supplies should have a minimum
resolution of 0.25V. Refer to Section 6.0 “AC/DC
Characteristics” for additional hardware parameters.
2.1.1 LOW-VOLTAGE ICSP
PROGRAMMING
In Low-Voltage ICSP mode, these devices can be pro-
grammed using a VDD source in the operating range.
This only means that MCLR/VPP does not have to be
broug ht to a di f ferent vol t ag e, b ut c an i ns tead be left at
the normal operating voltage. Refer to Section 6.0
“AC/DC Characteristics” for additional hardware
parameters.
2.1.2 VDD POWER SUPPLY
It is recommended that the power supply decoupling
capacitance be added at the programmer socket.
Capacitance in the range of 0.1 F to 10 F should be
connec ted from VDD to VSS, an d located as close to the
programming socket as possible.
2.2 Pin Diagrams
The programming pin descriptions for these devices
are shown in Table 2-1 and the pin diagrams are shown
in Figure 2-1 through Figure 2-6. The pin descriptions
of these diagrams do not represent the complete func-
tionality of the device types. Refer to the appropriate
device data sheet for complete pin descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
Pin Name During Programming
Function Pin Type Pin Description
MCLR/VPP/RA5(2) VPP P High-Voltage Programming Enable
VDD VDD P Power Supply
VSS VSS PGround
RB5 PGM I Low-Voltage ICSP™ Inpu t whe n LVP Configuration bit equals ‘1’(1)
RB6 PGC I Serial Clock
RB7 PGD I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 “Single-Supply ICSP Programming” for more detail.
2: RA5 is only available on the PIC18F1X20.
Flash Micr ocontr oller Programming Specification
PIC18FX220/X320
DS39592F-page 2 2010 Microchip Technology Inc.
FIGURE 2-1: PIC18F1X20 18-PIN PDIP, SOIC
FIGURE 2-2: PIC18F1X20 20-PIN SSOP
RB3/CCP1A/P1A
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD/AVDD
RB7/PGD/T1OSI/P1D/KBI3
RB6/PGC/T1OSO/T13CKI/P1C/KBI2
RB5/PGM/KBI1
RB4/AN6/RX/DT/KBI0
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
MCLR/VPP/RA5
VSS/AVSS
RA2/AN2/VREF-
RA3/AN3/VREF+
RB0/AN4/INT0
RB1/AN5/TX/CK/INT1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PIC18F1X20
RB3/CCP1A/P1A
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD
RB7/PGD/T1OSI/P1D/KBI3
RB6/PGC/T1OSO/T13CKI/P1C/KBI2
RB5/PGM/KBI1
RB4/AN6/RX/DT/KBI0
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
MCLR/VPP/RA5
VSS
RA2/AN2/VREF-
RA3/AN3/VREF+
RB0/AN4/INT0
RB1/AN5/TX/CK/INT1
1
2
3
4
5
7
8
9
10
20
19
18
17
16
14
13
12
11
PIC18F1X20
AVDD
AVSS 615
2010 Microchip Technology Inc. DS39592F-page 3
PIC18FX220/X320
FIGURE 2-3: PIC18F1X20 28-PIN QFN
FIGURE 2-4: PIC18F2X20 28-PIN SDIP (300 MIL), SOIC
16
2
RA0/AN0
RB2/P1B/INT2
RA4/T0CKI
MCLR/VPP/RA5
NC
AVSS
NC
RA2/AN2/VREF-
RA3/AN3/VREF+
RA1/AN1/LVDIN
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD
NC
AVDD
RB7/PGD/T1OSI/P1D/KBI3
RB6/PGC/T1OSO/T13CKI/P1C/KBI2
RB5/PGM/KBI1
RB4/AN6/RX/DT/KBI0
7
PIC18F1X20
1
3
6
5
4
15
21
19
20
17
18
22
28
26
27
23
24
25
14
8
10
9
13
12
11
VSS
NC
NC
RB3/CCP1A
RB0/AN4/INT0
RB1/AN5/TX/CK/INT1
NC
NC NC
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2
RB1/AN10/INT1
RB0/AN12/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
* Alternate pinout for CCP2 is enabled by a fuse.
PIC18F2X20
PIC18FX220/X320
DS39592F-page 4 2010 Microchip Technology Inc.
FIGURE 2-5: PIC18F4X20 40-PIN PDIP (600 MIL)
FIGURE 2-6: PIC18F4X20 44-PIN TQFP
* Alternate pinout for CCP2 is enabled by a fuse.
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2
RB1/AN10/INT1
RB0/AN12/INT0
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
VDD
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4X20
* Alternate pinout for CCP2 is enabled by a fuse.
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF-
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2*
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
VSS
VDD
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2*
RD7/PSP7/P1D
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4X20
37
5
4
2010 Microchip Technology Inc. DS39592F-page 5
PIC18FX220/X320
2.3 Memory Map
The code memory sp ace extend s from 0000h to 1FFFh
(8 Kbytes) in a s ing le 8 -Kby te panel. Ad dres ses 0000h
through 01FFh, however, define a “Boot Block” region
that is treated separately from Panel 1. All code
memory is on- chip.
A user may sto re ide ntif ic atio n inf orm atio n (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007 h. The ID locations
read out normally , even after code protection is applied.
Locations 300001h through 30000Dh are reserved
for the Configuration Words. These Words may be
set to select various device options and are
described in Section 5.0 “Configuration Word”.
These Configuration Words read out normally, even
after code protection.
Locatio ns 3FFFF Eh and 3FFF FFh are rese rved for th e
Device ID Words. These Words may be used by the
programmer to identify what device type is being
programmed and are described in Section 5.0
“Configuration Word”. These Configuration Words
read out normally, even after code protection.
TABLE 2-2: IMPLEMENTATION OF CODE MEMORY
FIGURE 2-7: MEMORY MAP FOR PIC18FX220/X320
Device Code Memory Size (Bytes) Data EEPROM Size (Bytes)
PIC18F1220 0000h-0FFFh (4K) 000-0FFh (256)
PIC18F2220 0000h-0FFFh (4K) 000-0FFh (256)
PIC18F4220 0000h-0FFFh (4K) 000-0FFh (256)
PIC18F1320 0000h-1FFFh (8K) 000-0FFh (256)
PIC18F2320 0000h-1FFFh (8K) 000-0FFh (256)
PIC18F4320 0000h-1FFFh (8K) 000-0FFh (256)
0000h
200000h
3FFFFFh
Unimplemented
Read as ‘0’s
200h
07FFh
Boot Block
Block 0
8Kbytes
200000h ID Location 1
200001h ID Location 2
200002h ID Location 3
200003h ID Location 4
200004h ID Location 5
200005h ID Location 6
200006h ID Location 7
200007h ID Location 8
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
3FFFFEh Device ID 1
3FFFFFh Device ID 2
4 Kbytes
Block 0
Block 1
Boot Block
Block 1
Block 2
Block 3
0FFFh
17FFh
1FFFh
Unimplemented
Read as ‘0’s
PIC18FX320 PIC18FX220
PIC18FX220/X320
DS39592F-page 6 2010 Microchip Technology Inc.
FIGURE 2-8: MEMORY MAP FOR PIC18F1X20
2.3.1 MEMORY ADDRESS POINTER
Memory in the addres s space, 000 000h to 3FFFFFh, is
addressed via the Table Pointer, which is comprised of
three pointer registers:
• TBLPTRU at address 0FF8h
• TBLPTRH at address 0FF7h
• TBLPTRL at address 0FF6h
0000h
200000h
3FFFFFh
Unimplemented
Read as ‘0’s
200h
07FFh
Boot Block
Block 0
8Kbytes
200000h ID Location 1
200001h ID Location 2
200002h ID Location 3
200003h ID Location 4
200004h ID Location 5
200005h ID Location 6
200006h ID Location 7
200007h ID Location 8
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
3FFFFEh Device ID 1
3FFFFFh Device ID 2
4 Kbytes
Block 0
Block 1
Boot Block
Block 1
0FFFh
17FFh
1FFFh
Unimplemented
Read as ‘0’s
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
2010 Microchip Technology Inc. DS39592F-page 7
PIC18FX220/X320
2.4 High-Level Overview of the
Programming Process
Figure 2-9 shows the high-level overview of the
programming process. The device is first checked to
see if it is blank; if it is not, a Bulk Erase is performed.
Next, the program memory, ID locations and data
EEPROM are written. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
written and verified.
FIGURE 2-9: HIGH-LEVEL PROGRAMMING FLOW
Start
Program Memory
Write ID Locations
Write EEPRO M
Verify Program
Verify IDs
Verify EEPROM
Write
Configuration Bits
Verify
Configuration Bits
Done
Is part
blank? No Perform Bulk
Erase
Yes
Blank Check
Write
PIC18FX220/X320
DS39592F-page 8 2010 Microchip Technology Inc.
2.5 Entering High-Voltage ICSP
Program/Verify Mode
The High-Voltage ICSP Program/Verify mode is
enter ed by holding PGC and PG D low , an d then raising
MCLR/VPP to VIHH (high voltage). Once in this mode,
the code memory, data EEPROM, ID locations and
Config uration bit s can be acces sed and writt en in serial
fashion.
The sequence that enters the device into the
Programming/Verify mode places all unused I/Os in
the high- imp ed anc e state.
FIGUR E 2-10 : ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
2.6 Entering Low-Voltage ICSP
Program/Verify Mode
When the LVP Configuration bit is ‘1’ (see Section 5.3
“Single-Supply ICSP Programming”), the Low-
Voltage ICSP mode is enabled. Low-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low, placing a l ogic h igh on PGM and t hen raisin g
MCLR/VPP to VIH. In this mode, the RB5/PGM pin is
dedicated to the programming function and ceases to
be a general purpose I/O pin.
The sequence that enters the device into the
Programm ing/V erify mo de places al l unused I/Os i n the
high-im pedance sta t e.
FIGUR E 2 -11: ENTERIN G LO W-VOLTAGE
PROGRAM/VERIFY MODE
2.7 Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Comman ds and data a re
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are sent Least Significant bit
(LSb) first.
2.7.1 4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
command, followed by a 16-bit operand which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Table 2-3.
TABLE 2-3: COMMANDS FOR
PROGRAMMING
Depending on the 4-bit command, the 16-bit operand
represents 16 bits or 8 bits of data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-4. The 4-bit com-
mand is shown MSb first. The command operand or
“Data Payload” is shown <MSB:LSB>. Figure 2-12
demonstrates how to serially present a 20-bit
comma nd/ ope rand to the devic e.
TABLE 2-4: SAMPLE COMMAND
SEQUENCE
MCLR/VPP
P12
PGD
PGD = Input
PGC
VDD
D110
P13
MCLR/VPP
P12
PGD
PGD = Input
PGC
PGM
P15
VDD
VIH
VIH
Description 4-Bit
Command
Core Instruction
(Shift in 16-bit instruction) 0000
Shift Out TABL AT Register 0010
Table Read 1000
Table Read , Post-In creme nt 1001
Table Read, Post-D ecrem en t 1010
Table Read , Pre-Inc rem ent 1011
Table Write 1100
Table Write, Post-Increment by 2 1101
Table Write, Post-Decrement by 2 1110
Table Write, Start Programming 1111
4-Bit
Command Data
Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2
2010 Microchip Technology Inc. DS39592F-page 9
PIC18FX220/X320
FIGURE 2-12: TABLE WRITE, POST-INCREMENT TIMING (1101)
2.7.2 CORE INSTRU CTIO N
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
register s, as app ropriate for use with other commands.
If the instruction is a 1-word, 1-cycle instruction, it will
be executed while the next command is clocked in.
If the instruction is a 2-word, 2-cycle instruction,
another core instruction command is required with the
second word of the instruction. The instruction will
complete when a third 4-bit command has been
loaded.
1234
PGC
P5
PGD
PGD = Input
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-Bit Command
1011
1234
nnnn
P3
P2 P2A
000000 010001111 0
04C3
P4
4-Bit Command (LSb first) 16-Bit Data Payload (LSb first)
P2B
PIC18FX220/X320
DS39592F-page 10 2010 Microchip Technology Inc.
3.0 DEVICE PROGRAMMING
3.1 Blank Check
The term “Blank Chec k” me ans to verify that the device
has no p ro gr amm ed m em ory ce l ls. A ll m e mo rie s mu st
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as ‘1’.
So, “Blank Checking” a device merely means to
verify that all bytes read as FFh except the
Configuration bits. Unused (reserved) Configuration
bits will read as ‘0’ (programmed). Refer to Table 5-2
for blank configuration expected data for the various
devices.
If it is determined that the device is not blank, then the
device should be Bulk Erased (s ee Section 3.2 “High-
Voltage ICSP Bulk Erase”) before any attempt to
progra m is ma de.
Given that “Blank Checking” is merely code and data
EEPROM verification, with FFh as the expected data,
refer to Section 4.1 “Read Data EEPROM Memory”
and Section 4.3 “Verify Code Memory and ID
Locations” for implementation details.
FIGURE 3-1: BLANK CHECK FLOW
3.2 High-Voltage ICSP Bulk Erase
Erasing code or data EEPROM is accomplished by
writing an “erase option” to address 3C0004h. Code
memory may be erase d, portions at a time, or the us er
may era se the entire devi ce in one a ction. “Bulk Erase”
operations will also clear any code-protect settings
associated with the memory block erased. Erase
options are detailed in Table 3-1.
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PG C afte r the write com mand), se rial execu tion
will cease until the erase completes (parameter P11).
During thi s time, PGC may c ontinue to tog gle, but PGD
must be held low.
The code s equence to eras e the entire devic e is shown
in Table 3-2 and the flowchart is shown in Figure 3-2.
TABLE 3-2: BULK ERASE COMMAND
SEQUENCE
Is
Yes
No
Start
Blank Check Device
device
blank?
Bulk Erase Device
Blank Check Device
Is
device
blank? Continue
Abort
No
Yes Continue
Description Data
Chip Erase 80h
Erase Data EEPROM 81h
Erase Boot Block 83h
Erase Block 0 88h
Erase Block 1 89h
Erase Block 2 8Ah
Erase Block 3 8Bh
Note: A Bulk Erase is the only way to reprogram
code-protect bits from an ON state to an
OFF sta t e.
4-Bit
Command Data
Payload Core In stru ction
0000
0000
0000
0000
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
00 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTR U
MOVLW 00h
MOVWF TBLPTR H
MOVLW 04h
MOVWF TBLPTR L
Write 80h TO 3C0004h to
erase entire devic e.
NOP
Hold PGD low until
erase comple tes.
2010 Microchip Technology Inc. DS39592F-page 11
PIC18FX220/X320
FIGURE 3-2: BULK ERASE FLOW 3.2.1 LOW-VOLTAGE ICSP BULK ERASE
When using low-voltage ICSP, the part must be
suppli ed by the volta ge specified in para meter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be perform ed at a sup ply vo ltag e below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.3.1 “Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 3.4
“Dat a EEPROM Programming” and w rite zeros to the
array.
FIGURE 3-3: BULK ERASE TIMING
3.3 Code Memory Programming
Programming code memory is accomplished by first
loading dat a int o the appro priate wr ite bu ffe rs an d then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-7 and Figure 2-8)
has an 8-byte deep write buffer that must be loaded
prior to initiating a write sequence. The actual memory
write se que nce t akes the conte nts of the se buf fers an d
programs the associated EEPROM code memory.
The programming duration is externally timed and is
controlled by PGC. After a “Start Programming” com-
mand is issued (4-bit command, ‘1111’), a NOP is
issued , where th e 4 th PGC is he ld high fo r the dur ation
of the programmi ng time, P9 (see F i gure 3-6).
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to program a device is shown in
Table 3-3. The flowchart shown in Figure 3-5 depicts
the logic necessary to completely write a device.
Start
Done
Write 80h
to Erase
Entire Device
Load Address
Pointer to
3C0004h
Delay P11 + P10
Time
n
1234 121516 123
PGC
P5 P5A
PGD
PGD = Input
00011
P11
P10
Erase Time
00 0 000 0 0
12
00
4
0
1 2 15 16
P5
123
P5A
4
0000
n
4-Bit Command 4-Bit Command 4-Bit Command
NOP
16-Bit
Data Payload 16-Bit
Data Payload
Note: The TBLPTR register must contain the
same offset value when initiating the
progra mmin g s equ enc e a s i t di d w he n th e
write buffers were loaded.
PIC18FX220/X320
DS39592F-page 12 2010 Microchip Technology Inc.
FIGURE 3-4: ERASE AND WRITE BOUNDARIES
Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 0
Offset = TBLPTR<12:6>
Panel 1
Erase Region
(64 bytes)
8-Byte Write Buffer
Unimplemented
Read as ‘0’
2010 Microchip Technology Inc. DS39592F-page 13
PIC18FX220/X320
TABLE 3-3: WRITE CODE ME MORY CODE SEQUENCE
FIGURE 3-5: PROGRAM CODE MEMORY FLOW
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Load write buffer for Panel 1.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold PGC high for time P9
To continue writing data, repeat step 2, where the Address Pointer is incremented by 8 at each iteration of the loop.
Start Write Sequence
All
locations
done?
No
Done
Start
Yes
Delay P9 + P10 T ime
for Wr i te to O c cur
Load 8 Bytes
to Panel Write
Buffer at <Addr>
and Hold PGC
High Until Done
LoopCount = 0
LoopCount =
LoopCount + 1
PIC18FX220/X320
DS39592F-page 14 2010 Microchip Technology Inc.
FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
3.3.1 MODIFYING CODE MEMORY
All of th e progra mming exampl es, up to this poi nt, have
assum ed that the device i s blank pr ior to progra mming.
In fact, if the de vice is no t blan k, the direc tion h as been
to completely erase the device via a Bulk Erase
operation (see Section 3.2 “High-Voltage ICSP Bulk
Erase”).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device. In such a situation, erasing the entire device is
not a real istic opt ion.
The minim um am ount of dat a that c an be wri tten to the
device is 8 bytes. This is accomplished by loading the
8-byte write buffer for the panel and then initiating a
write sequence. In this case, however, it is assumed
that the a ddress sp ace to be writ ten already ha s data in
it (i.e., it is not blank).
The minimum amount of code memory that may be
erased at a given time is one row of 64 bytes and it is
select ed us ing the TBLPTR registers . The si xt h LS b of
the TB LPTR add ress i s ignored . The EECON1 regis ter
must then be used to erase the 64-byte target space
prior to writing the data. This is known as a “Row
Erase”.
When using the EECON1 register to act on code mem-
ory, the EEPGD bit must be set (EECO N1<7> = 1) and
the CFGS bit must be cleared (EECON1<6> = 0). The
WREN bit must be set (EECON1<2> = 1) to enable
writes of an y so rt (e.g., erases), and th is mu st be done
prior to initiating a write sequence. The FREE bit must
be set (EECON1<4> = 1) in order to erase the program
spac e bei ng pointed to b y t he Table Pointe r. The er ase
sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is str ongly recomm ended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 is used to “ena ble” the WR
bit. This regi st er mus t be se quentially lo aded with 55h,
and then 0AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The eras e w il l b eg in on th e falling e dg e o f t he 4th PG C
after the WR bit is set.
Aft er the erase sequenc e terminates, PGC mu st still be
held low for the time specified by parameter P10 to
allow high-voltage discharge of the memory array.
1234 1 2 15 16 123 4
PGC P5A
PGD n1111
34 65
P9
P10
Programming Time
nnn nn nn 00
12
000
16-Bit
Data Payload
0
3
0
P5
4-Bit Command 16-Bit Data Payload 4-Bit Command
PGD = Input
2010 Microchip Technology Inc. DS39592F-page 15
PIC18FX220/X320
TABLE 3-4: MODIFYING CODE MEMORY
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 3: Enable memory writes and set up an erase.
0000
0000 84 A6
88 A6 BSF EECON1, WREN
BSF EECON1, FREE
Step 4: Perform Flash unlock sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 0X55
MOVWF EECON2
MOVLW 0XAA
MOVWF EECON2
Step 5: Initiate erase.
0000
0000 82 A6
00 00 BSF EECON1, WR
NOP
Step 6: Wait for P11 + P10 and then disable writes.
0000 94 A6 BCF EECON1, WREN
Step 7: Load write buffer for panel.
1101
1101
1101
1111
0000
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold PGC high for time P9 at the end of 4-bit command
To continue writing data, repeat step 7, where the Address Pointer is incremented by 8 at each iteration of the loop.
PIC18FX220/X320
DS39592F-page 16 2010 Microchip Technology Inc.
3.4 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a Data Latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, loading EEDATA with the
data to be written and initiating a memory write by
appropriately configuring the EECON1 and EECON2
register s. A byte write automatically erases the l ocation
and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to e nab le writ es of an y sort an d this
must be done prior to initiating a write sequence.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 i s used to “enable ” the WR
bit. This reg ister must be sequentially lo aded with 55h,
and then 0AAh, immediately prior to asserting the WR
bit in orde r for the w rite to o ccur. The write s equenc e is
initiated by setting the WR bit (EECON1<1> = 1). It is
strongly recommended that the WREN bit be set only
when absolutely necessary.
The write will begin on the falling edge of the 4th PGC
after the WR bit is set.
After the programm ing sequence terminates, PGC m ust
still be held low for the time specified by parameter P10
to allow high-volt age dis charge of the memory array.
FIGURE 3-7: PROGRAM DATA FLOW
FIGURE 3-8: DATA EEPROM WRITE TIMING
Start
St art Write
Set D a ta
Done
No
Yes
Done?
Delay P11 + P10
Enable Write
Unlock Sequence
55h – EECON2
0AAh – EECON2
Sequence
Set Address
for Write to Occur
n
PGC
PGD
PGD = Input
0000
Data EEPROM
0000
BSF EECON1, WR
4-Bit Comm an d
1234 121516 123
P5 P5A P11
P11 12
41 2 15 16
P5
123
P5A
4
0000 0000
n
4-Bit Command 4-Bit Command16-Bit
Data Payload Write Time 16-Bit
Data Payload
2010 Microchip Technology Inc. DS39592F-page 17
PIC18FX220/X320
TABLE 3-5: PROGRAMMING DATA MEMORY
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM .
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000 0E <Addr>
6E A9 MOVLW <Addr>
MOVWF EEADR
Step 3: Load the data to be written.
0000
0000 0E <Data>
6E A8 MOVLW <Data>
MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 A6 BSF EECON1, WREN
Step 5: Perform data EEPROM unlock sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 0X55
MOVWF EECON2
MOVLW 0XAA
MOVWF EECON2
Step 6: Initiate write.
0000
0000
0000
82 A6
00 00
00 00
BSF EECON1, WR
NOP
NOP
Step 7: Wait for P11 and then disable writes.
0000 94 A6 BCF EECON1, WREN
Repeat steps 2 through 7 to write more data.
PIC18FX220/X320
DS39592F-page 18 2010 Microchip Technology Inc.
3.5 ID Location Programming
The ID locations are programmed much like the code
memory. The single panel that will be written will auto-
matically be enabled, based on the value of the Table
Pointer. The ID registers are mapped in addresses
200000h through 200007h. These locations read out
normally, even after code protection.
Table 3-6 demonst rates the code se quence requ ired to
write the ID locations.
The Table Pointer must be manually set to 200000h
(base ad dres s of th e ID loc ati ons ). T he p os t-in cre me nt
feature of the table read 4-bit command may not be
used to increment the Table Pointer to 200000h. The
post-increment feature may then be used to increment
to 200001h, 200002h, etc.
TABLE 3-6: WRITE ID SEQUENCE
Note: The u ser must fill the 8- byte da ta buf fer for
the panel.
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Load write buffer.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold PGC high for time P9
2010 Microchip Technology Inc. DS39592F-page 19
PIC18FX220/X320
3.6 Boot Block Programming
The Boot Block segment is programmed in exactly the
same ma nner as the ID location s (see Section 3.5 “ID
Location Programming”).
The code sequence detailed in Table 3-6 should be
used, ex cept t hat the addres s dat a use d in “Step 2” will
be in the range of 000000h to 0001FFh.
3.7 Configuration Bit s Programming
Unlike code memory, the Configuration bits are
programmed a byte at a time. The “Table Write, Begin
Programming” 4-bit command (1111) is use d, bu t onl y
8 bits of the follow ing 16-bi t pay load will be writ ten. The
LSB of the payload will be written to even addresses
and the MSB will be written to odd addresses. The
code sequence to program two consecutive
configuration locations is shown in Table 3-7.
TABLE 3-7: SET ADDRESS POINTER TO CONFIGURATION LOCATION
FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to configuration memory.
0000
0000 8E A6
8C A6 BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Position the program counter.(1)
0000
0000 EF 00
F8 00 GOTO 0x100000
Step 3: Set Table Pointer for Configuration Word to be written. Write even/odd addresses.
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table writes. To avoid this situation, move the program count er outside the
code protection area (e.g., GOTO 0x100000).
2: Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration
bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
Load Even
Configuration
Start
Program Program
MSB
Done
Delay P9 Time
for Writ e
Delay P9 Time
for Wr i te
LSB
Load Odd
Configuration
Address Address
Done
Start
PIC18FX220/X320
DS39592F-page 20 2010 Microchip Technology Inc.
4.0 READING THE DEVICE
4.1 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a Data Latch, EEDATA.
Data EEPROM is read by loading EEADR with the
desir ed memor y locat ion and in itiat ing a memor y read
by appro priatel y conf igur ing the EECON1 regist er. The
data will be loaded into EEDATA, where it may be
serially output on PGD via the 4-bit command, ‘0010’
(Shift O ut Data Holdi ng register). A de lay of P6 must b e
introduced after the falling edge of the 8th PGC of the
oper an d t o al lo w PG D t o tr a n si t io n f ro m an i npu t t o an
output. During this time, PGC must be held low (see
Figure 4-2).
The command sequence to read a single byte of data
is shown in Table 4-1.
FIGURE 4-1: READ DATA EEPROM
FLOW
TABLE 4-1: READ DATA EEPROM MEMORY
FIGURE 4-2: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
Start
Set
Address
Read
Byte
Done
No
Yes
Done?
Move to TABLAT
Shift Out Data
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM .
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000 0E <Addr>
6E A9 MOVLW <Addr>
MOVWF EEADR
Step 3: Initiate a memory read.
0000 80 A6 BSF EECON1, RD
Step 4: Load data into the Serial Data Holding register.
0000
0000
0010
50 A8
6E F5
<LSB><MSB>
MOVF EEDATA, W, 0
MOVWF TABLAT
Shift Out Data(1)
Note 1: The <LSB> is undefined. The <MSB> is the data.
1234
PGC P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
91011 13 15161412
Fetch Next 4-Bi t Command
0100
PGD = Input
LSb
MSb
123456
1234
nnnn
P14
2010 Microchip Technology Inc. DS39592F-page 21
PIC18FX220/X320
4.2 Read Code Memory, ID Locations
and Configurati on Bits
Code memo ry is accesse d one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The contents of memory pointed to by the Table
Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are loaded
into the Table Latc h an d then se ri all y out pu t on PGD.
The 4-bit command is shifted in LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks , LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
PGC of the ope ran d to a llow PGD to trans iti on fr om an
input to an output. During this time, PGC must be held
low (see Table 4-2). This ope ration als o incremen ts the
Table Pointer by one, pointing to the next byte in code
memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address s p a ce, s o i t also appl ie s
to the reading of the ID and Configuration registers.
TABLE 4-2: READ CODE MEMORY SEQUENCE
FIGURE 4-3: TABLE READ, POST-INCREMENT INSTRUCTION TIMING (1001)
4-Bit
Command Data Payload Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory into Table Latch and then shift out on PGD, LSb to MSb.
1001 00 00 TBLRD *+
1234
PGC P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-Bit Command
1001
PGD = Input
LSb
MSb
123456
1234
nnnn
P14
PIC18FX220/X320
DS39592F-page 22 2010 Microchip Technology Inc.
4.3 Verify Code Memory and
ID Locations
The veri fy step in volves read ing back the code memo ry
space and comparing it against the copy held in the
programmer’s buffer. Memory reads occur a single byte
at a time, so two bytes must be read to compare
against the word in the programmer’s buffer. Refer to
Section 4.2 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading co de mem ory.
The Table Pointer must be manually set to 200000h
(base ad dres s of th e ID loc ati ons ). T he p os t-in cre me nt
feature of the table read 4-bit command may not be
used to increment the Table Pointer to 200000h. The
post-increment feature may then be used to increment
to 200001h, 200002h, etc.
FIGURE 4-4: VERIFY CODE MEMORY FLOW
4.4 Verify Configuration Bits
A configuration address may be read and output on
PGD via th e 4-bit co mmand, ‘1001’. Config uration dat a
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.2 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading configuration data.
4.5 Verify Data EEPROM
A data EEPROM add res s may b e re ad vi a a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (Shif t Out
Data Holding register). The result may then be
immediately compared to the appropriate data in the
programmer’s memory for verification. Refer to
Section 4.1 “Read Data EEPROM Memory” for
implementation details of reading data EEPROM.
Read Low Byte
Read High Byte
Does
word = expect
data? Failure,
Report
Error
All
code memory
verified?
No
Yes
No
Set Pointer = 0
Start
Set Pointer = 200000h
Yes
Read Low Byte
Read High Byte
Does
word = expect
data? Failure,
Report
Error
All
ID locations
verified?
No
Yes
Done
Yes
No
2010 Microchip Technology Inc. DS39592F-page 23
PIC18FX220/X320
5.0 CONFIGURATION WORD
The devices have several Configuration Words. Bits in
these registers can be set or cleared to select various
device configurations. All other memory areas should
be programmed and verified prior to sett ing Co nfigura-
tion Words. These bits ma y be read out normally, eve n
after read or code-protected. Tables 5-2, 5-3 and 5-4
provide information on various Configuration bits.
5.1 ID Locations
A user may sto re ide ntif ic atio n inf orm atio n (ID) in eight
ID locations mapped in 200000h:200007h. It is recom-
mended that the most significant nibble of each ID be
0Fh. In doing so, if the user code inadvertently tries to
execute from the ID space, the ID data will execute as
a NOP.
5.2 Device ID W ord
The Device ID Word for the devices is located at
3FFFFEh:3FFFFFh. These bits may be used by the
programmer to identify what device type is being
progra mmed an d re ad out normal ly, even after code or
read protect ion .
5.3 Single-Supply ICSP Programming
The LVP bit in Configuration register, CONFIG4L,
enables Single-Supply (Low-Voltage) ICSP Program-
ming mode. The LVP bit defaults to a ‘1’ (enabled)
following an erase.
If Single-Supply Programming mode is not used, the
LVP bit can be programmed to a ‘0’ and RB5/PGM
becomes a digital I/O pin . However, the LVP bit may only
be programmed by entering the High-Voltage ICSP
mode, where MCLR/VPP is raised to V IHH. Once the L VP
bit is programmed to a ‘0’, only the High-Voltage ICSP
mode is ava ilable and only the High-Voltage ICSP mode
can be used to program the devic e.
TABLE 5-1: DEVICE ID VALUE
Note 1: The normal High-Voltage ICSP mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR/VPP pin.
2: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purp os e I/O.
Device Device ID Value
DEVID2 DEVID1
PIC18F1220 07 111x xxxx
PIC18F2220 05 100x xxxx
PIC18F4220 05 101x xxxx
PIC18F1320 07 110x xxxx
PIC18F2320 05 000x xxxx
PIC18F4320 05 001x xxxx
PIC18FX220/X320
DS39592F-page 24 2010 Microchip Technology Inc.
TABLE 5-2: PIC18F2X20/4X20 CONFIGURATION BITS AND DEVICE IDs
TABLE 5-3: PIC18F1X20 CONFIGURATION BITS AND DEVICE IDs
File N a m e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0 Erased or
“Bla nk” Value
300000h CONFIG1L — — — — — — — — ---- ----
300001h CONFIG1H IESO FSCM —— FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111
300002h CONFIG2L — — — — BORV1 BORV0 BOR PWRT ---- 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDT ---1 1111
300004h CONFIG3L — — — — — — — — ---- ----
300005h CONFIG3H MCLRE — — — — — PBAD CCP2MX 1--- --11
300006h CONFIG4L DEBUG — — — —LVP—STVR1--- -1-1
300007h CONFIG4H — — — — — — — — ---- ----
300008h CONFIG5L — — — —CP3
(1) CP2(1) CP1 CP0 ---- 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — —WRT3
(1) WRT2(1) WRT1 WRT0 ---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC ———— —111- ----
30000Ch CONFIG7L — — — —EBTR3
(1) EBTR2(1) EBTR1 EBTR0 ---- 1111
30000Dh CONFIG7H —EBTRB— — — — — — -1-- ----
3FFFFEh DEVID1 DEV 2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1
Legend: - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplem ented in PIC18F2220 and PIC18F4220 devices, read as ‘0’.
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Erased or
“Bla nk” Value
300000h CONFIG1L — — — — — — — — ---- ----
300001h CONFIG1H IESO FSCM —— FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111
300002h CONFIG2L ——— — BORV1 BORV0 BOR PWRTEN ---- 1111
300003h CONFIG2H ——— WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDT ---1 1111
300004h CONFIG3L — — — — — — — — ---- ----
300005h CONFIG3H MCLRE — — — — — — — 1--- ----
300006h CONFIG4L DEBUG — — — —LVP—STVR1--- -1-1
300007h CONFIG4H — — — — — — — — ---- ----
300008h CONFIG5L — — — — — —CP1CP0---- --11
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — — — — WRT1 WRT0 ---- --11
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 ---- --11
30000Dh CONFIG7H —EBTRB— — — — — — -1-- ----
3FFFFEh DEVID1 DEV2 DEV1 DEV 0 REV4 RE V3 R E V2 REV1 REV0 Table 5- 1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DE V6 DE V5 D EV 4 DEV3 Table 5-1
Legend: - = Unimplemented. Shaded cells are unimplemented, read as ‘0’.
2010 Microchip Technology Inc. DS39592F-page 25
PIC18FX220/X320
TABLE 5-4: PIC18FX220/X320 BIT DESCRIPTIONS
Bit Name Conf iguration
Words Description
IESO CONFIG1H Interna l Ext ern al Sw itc ho ver bi t
1 = Interna l Ex tern al Sw itc hover mode enabled
0 = Interna l Ex tern al Sw itc hover mode di sabled
FSCM CONFIG1H Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
FOSC3:FO SC 0 C ON FIG 1H Oscillator Se lect ion bi ts
11xx = External RC oscillator, CLKO function on RA6
101x = External RC oscillator, CLKO function on RA6
1001 = Internal RC oscillato r, CLK O fun ct ion on RA6, por t fun cti on on RA7
1000 = Internal RC oscillato r, port fu nct i on on RA6, po rt funct i on on RA7
0111 = External RC oscillator, port function on RA6
0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FO SC1)
0101 = EC oscillat or, port function on RA6
0100 = EC oscillator, CLKO function on RA6
0011 = External RC oscillator, CLKO function on RA6
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
BORV1:BORV0 CONFIG2L Bro wn-ou t Reset Voltage bits
11 =Reserved
10 =V
BOR set to 2.7V
01 =V
BOR set to 4.2V
00 =V
BOR set to 4.5V
BOR CONFIG2L Brown-out Reset Enable bit
1 = Brown-out Re set enab led
0 = Brown-out Reset disabl ed
PWRT CONFIG2L Power- up Timer Enable bit for PIC18F2 X20/4X20
1 = PWRT disa bled
0 = PWRT enabled
PWRTEN CONFIG2L Power - up Timer Enable bit for PIC18F1X20
1 = PWRT disa bled
0 = PWRT enabled
WDTPS3:WDTP
S0 CONFIG2H Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
WDT CONF I G 2H Watch dog T imer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
PIC18FX220/X320
DS39592F-page 26 2010 Microchip Technology Inc.
MCLRE CONFIG3H MCLR Pin Enable bit for PIC18F2X20/4X20
1 =MCLR
pin enabled, RE3 input pin disabl ed
0 = RE3 input pin enab le d, M C LR pin di sabled
MCLRE CONFIG3H MCLR Pin Enable bit for PIC18F1X20
1 = MC LR pin enabled, RA5 in put pin disabled
0 = RA5 input pin enabled, M CLR pin dis abled
PBAD CONFIG3H PORTB A/D Enable bit for PIC18F2X20/4X20
1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2MX CONFIG3H CCP2 MUX bit for PIC18F2X20/4X20
1 = CCP2 i nput/output is m ul tiplexed with R C 1
0 = CCP2 i nput/output is m ul tiplexed with R B3
DEBUG CON FI G 4 L In- C ir cuit Debugger Enabl e b it
1 = In-Circ ui t De bugger disa bl ed (RB6, RB 7 have I/O port fu nction)
0 = In-Circ ui t De bugger en ab le d (RB6, RB7 have ICSP™ se rial communi c at io n
function)
LVP CONFIG4L Low-Voltage Programming E nab l e bi t
1 = Low-Voltage Programming enabled, RB5 is the PGM pin
0 = Low-Voltage Programming disabled, RB5 is an I/O pin
STVR CONFIG 4 L Stack Overflow/Und er flow Reset En abl e b it
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
CP3 CONFIG5L Code Protection bit for PIC18F2320/4320
(Bloc k 3 co de m em ory area: 001800h- 00 1FFFh, unim pl emented in PIC18F222 0/ 4220)
1 = Block 3 is not code -p ro te ct ed
0 = Block 3 is code-protected
CP2 CONFIG5L Code Protection bit for PIC18F2320/4320
(Bloc k 2 co de m em ory area: 001000h- 00 17FFh, unim plemented in P IC1 8F2220/4220)
1 = Block 2 is not code -p ro te ct ed
0 = Block 2 is code-protected
CP1 CONFIG5L Code Protection bit for PIC18F1220
(Block 1 code memory area: 000800h-000FFFh)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
CP1 CONFIG5L Code Protection bit for PI C18F1320 ( Bl ock 1 code memory area: 0010 00h-001 FFFh)
1 = Block 1 is not code -p ro te ct ed
0 = Block 1 is code-protected
CP1 CONFIG5L Code Protection bit for PIC18F2X20/4X20
(Bloc k 1 co de m emory are a: 000800h- 000FFFh)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
CP0 CONFIG5L Code Protection bit for PI C 18F1220 (B lock 0 code mem or y area: 0002 00h-0007FFh)
1 = Block 0 is not code -p ro te ct ed
0 = Block 0 is code-protected
CP0 CONFIG5L Code Protection bit for PI C18F1320 ( Bl ock 0 code memory area: 0002 00h-000 FFFh)
1 = Block 0 is not code -p ro te ct ed
0 = Block 0 is code-protected
CP0 CONFIG5L Code Protection bit for PIC18F2X20/4X20
(Bloc k 0 co de m emory are a: 000200h- 0007FFh)
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
TABLE 5-4: PIC18FX220/X320 BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
2010 Microchip Technology Inc. DS39592F-page 27
PIC18FX220/X320
CPD CONFIG5H Code Protection bit (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
CPB CONFIG 5 H Code Prote ct ion bi t (Bo ot B lock m emory ar ea: 000 000h-00 01FFh)
1 = Boot Block is not code-protected
0 = Boot Block is code- pro t ect ed
WRT3 CONFIG6 L Write Prot ec tion bi t for P IC1 8F2320/4320
(Bloc k 3 co de m em ory area: 001800h- 00 1FFFh, unim pl emented in PIC18F222 0/ 4220)
1 = Block 3 is not write-protected
0 = Bloc k 3 is wri t e-protected
WRT2 CONFIG6 L Write Protection bit for PIC18F232 0/4320
(Bloc k 2 co de m em ory area: 001000h- 00 17FFh, unim plemented in PIC18F2220/ 422 0)
1 = Block 2 is not write-protected
0 = Bloc k 2 is wri t e-protected
WRT1 CONFIG6L Wr i te Prote ction bit for PIC 18F1 22 0
(Block 1 code memory area: 000800h-000FFFh)
1 = Block 1 is not write-protected
0 = Bloc k 1 is wri t e-protected
WRT1 CONFIG6 L Write Prot ection bit for P IC1 8F1320 (Blo ck 1 code me m or y area: 001000h-001F FFh)
1 = Block 1 is not write-protected
0 = Bloc k 1 is wri t e-protected
WRT1 CONFIG6L Write Prot ec tion bi t for PIC1 8F2X20/ 4X2 0
(Bloc k 1 co de m emory are a: 000800h- 000FFFh)
1 = Block 1 is not write-protected
0 = Bloc k 1 is wri t e-protected
WRT0 CONFIG6 L Write Prot ection bit for P IC1 8F1220 (Blo ck 0 code me m or y area: 000200h-0007 FFh)
1 = Block 0 is not write-protected
0 = Bloc k 0 is wri t e-protected
WRT0 CONFIG6 L Write Prot ection bit for P IC1 8F1320 (Blo ck 0 code me m or y area: 000200h-000F FFh)
1 = Block 0 is not write-protected
0 = Bloc k 0 is wri t e-protected
WRT0 CONFIG6L Write Prot ec tion bi t for PIC1 8F2X20/ 4X2 0
(Bloc k 0 co de m emory are a: 000200h- 0007FFh)
1 = Block 0 is not write-protected
0 = Bloc k 0 is wri t e-protected
WRTD CONFIG6H Write Protection bi t (Data EEP R OM )
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
WRTB CONFIG6H Write Protec tion bit (B oo t Block memo ry are a: 000 000h-0001FFh)
1 = Boot Block is not writ e- pr ot ected
0 = Boot Block is write-pro t ect ed
WRTC CONFIG6H Write Protection bit (Configuration registers: 300000h-3000FFh)
1 = Configuration registers are not write-protected
0 = Configuration registers are write-protected
EBTR3 CONFIG7L Table Read Protection bit for PIC18F2320/4320
(Bloc k 3 co de m em ory area: 001800h- 00 1FFFh, unim pl emented in PIC18F222 0/ 4220)
1 = Block 3 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Bloc k 3 is prot ected from table reads executed i n other bl ocks
EBTR2 CONFIG7L Table Read Protection bit for PIC18F2320/4320
(Bloc k 2 co de m em ory area: 001000h- 00 17FFh, unim plemented in PIC18F2220/ 422 0)
1 = Block 2 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Bloc k 2 is prot ected from table reads executed i n other bl ocks
TABLE 5-4: PIC18FX220/X320 BIT DESCRIPTIONS (CONTINUED)
Bit Name Conf iguration
Words Description
PIC18FX220/X320
DS39592F-page 28 2010 Microchip Technology Inc.
EBTR1 CONFIG7L Table Read Protection bit for PIC18F1220
(Bloc k 1 co de m emory are a: 000800h- 000FFFh)
1 = Block 1 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Block 1 is protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit for PIC18F1320
(Bloc k 1 co de m emory are a: 001000h- 001FFFh)
1 = Block 1 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Block 1 is protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit for PIC18F2X20/4X20
(Bloc k 1 co de m emory are a: 000800h- 000FFFh)
1 = Block 1 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Block 1 is protected from table reads executed in other blocks
EBTR0 CONFIG7L Table Read Protection bit for PIC18F1220
(Bloc k 0 co de m emory are a: 000200h- 0007FFh)
1 = Block 0 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Block 0 is protected from table reads executed in other blocks
EBTR0 CONFIG7L Table Read Protection bit for PIC18F1320
(Bloc k 0 co de m emory are a: 000200h- 000FFFh)
1 = Block 0 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Block 0 is protected from table reads executed in other blocks
EBTR0 CONFIG7L Table Read Protection bit for PIC18F2X20/4X20
(Bloc k 0 co de m emory are a: 000200h- 0007FFh)
1 = Block 0 is not prote ct ed f ro m table re ads execu te d in ot her bl oc ks
0 = Block 0 is protected from table reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area: 000000h-0001FFh)
1 = Boot Bl ock is not pro t ect ed fr om table r ead s executed i n ot her blocks
0 = Boot Bl ock is pro te ct ed fr om table r ead s execute d in ot her blocks
DEV10:DEV3 DEVID2 Device ID bits
These bi ts are used with the D EV2:DEV0 b its in the DEVID1 regist er to identify
the p art num ber.
DEV2:DEV0 DEVID1 Device ID bits
These bi ts are us ed w i th th e D EV1 0: D EV3 bi ts in the DEVI D 2 re gist er to ident i fy
the p art num ber.
REV4:REV0 DEVID1 Revision ID bits
Thes e bits are used to indicate the re vi si on of the device.
TABLE 5-4: PIC18FX220/X320 BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
2010 Microchip Technology Inc. DS39592F-page 29
PIC18FX220/X320
5.4 Embedding Configuration Word
Info rmatio n in th e H EX Fi le
To allow portability of code, a device programmer is
required t o rea d the C onf igu r ati on Word locati ons fro m
the hex file. If Configuration Word information is not
pres ent i n th e he x fi le, then a simp le w a rnin g m es sag e
shoul d be issued . Si milarly, whil e saving a hex fil e, all
Configuration Word information must be included. An
option to not include the Configuration Word informa-
tion may be provided. When embedding Configuration
Word information in the hex file, it should start at
address 300000h.
Microchip Technology Inc. feels strongly that this
featur e is imp orta nt for th e bene fit of t he end cu stome r.
5.5 Embedding Data EEPROM
Info rmatio n in th e H EX Fi le
To allow portability of code, a device programmer is
required to read the data EEPROM information from
the hex file. If data EEPROM information is not present,
a sim ple w ar nin g m es s age s hou ld be iss ued . Si milarly,
when saving a hex file, all data EEPROM information
must be included. An option to not include the data
EEPROM information may be provided. When embed-
ding dat a EEPROM inf ormation in th e hex file , it should
start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
5.6 Checksum Comput ation
The check s um is cal cu lat ed by sum mi ng the foll owing:
• The contents of all code memory locations
• The Configuration Word, appropriately masked
• ID locations
The Least Significant 16 bits of this sum are the
checksum.
Table 5-5 describes how to calculate the checksum for
each device.
Note: The checksum calculation differs depend-
ing on the code-protect setting. Since the
code me mory locations read out differently
dependi ng on the code-pro tect setting, th e
table describes how to manipulate the
actual code memory values to simulate
the values that would be read from a
protected device. When calculating a
checksum by reading a device, the entire
code memory can simply be read and
summed. The Configuration Word and ID
locations can always be read.
PIC18FX220/X320
DS39592F-page 30 2010 Microchip Technology Inc.
TABLE 5-5: CHECKSUM COMPUTATION – PIC18FX220/X320
Device Code-Protect Checksum Blank
Value
0xAA at 0
and Max
Address
PIC18F1220
None SUM (0000:01FFh) + SUM (0200: 0FFF h) + SU M (1000:1FFF h) +
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) +
(CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) +
(CONFIG7L & 03h) + (CONFIG7H & 040h)
F3EB F341
Boot Block SUM (0200:0FFFh) + SUM (1000:1FFFh) + (CONFIG1H & 0CFh) +
(CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) +
(CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) +
(CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) +
(CONFIG7H & 040h) + SUM (IDs)
F5D6 F56D
Boot/
Panel 1/
Panel 2
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) +
(CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) +
(CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs)
03D3 03BF
All (CONFIG1H & 0CFh ) + (CONFIG2L & 0Fh) + (CONFIG2H & 1F h) +
(CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) +
(CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) +
(CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs)
03D3 03BF
PIC18F1320
None SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800: 0FFFh) +
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) +
(CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) +
(CONFIG7L & 03h) + (CONFIG7H & 040h)
E3EB E341
Boot Block SUM (0200:07FFh) + SUM (0800:0FFF h) + (CONF IG1H & 0CFh) +
(CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) +
(CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) +
(CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) +
(CONFIG7H & 040h) + SUM (IDs)
E5D5 E56C
Boot/
Panel 1/
Panel 2
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) +
(CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) +
(CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs)
03D2 03BE
All (CONFIG1H & 0CFh ) + (CONFIG2L & 0Fh) + (CONFIG2H & 1F h) +
(CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) +
(CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) +
(CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs)
03D2 03BE
Legend: Item Description
CONFIG = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM (IDs) = Byte-wise sum of lower four bits of all ID locations
+ = Addition
& = Bit-wise AND
2010 Microchip Technology Inc. DS39592F-page 31
PIC18FX220/X320
PIC18F2220/
PIC18F4220
None SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800: 0FFFh) +
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) +
(CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) +
(CONFIG7L & 0Fh) + (CONFIG7H & 040h)
0F412h 0F368h
Boot Block SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONF IG1H & 0CFh ) +
(CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) +
(CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) +
(CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) +
(CONFIG7H & 040h) + SUM (IDs)
0F5E8h 0F59Dh
Boot Block/
Block 0 SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) +
(CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) +
(CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) +
(CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) +
SUM (IDs)
0FBE7h 0FB9Ch
Boot Block/
Block 0/
Block 1
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) +
(CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) +
(CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs)
03E5h 03EFh
All (CONFIG1H & 0CFh ) + (CONFIG2L & 0Fh) + (CONFIG2H & 1F h) +
(CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) +
(CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) +
(CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs)
03E5h 03EFh
TABLE 5-5: CHECKSUM COMPUTATION – PIC18FX220/X320 (CONTINUED)
Device Code-Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CONFIG = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM (IDs) = Byte-wise sum of lower four bits of all ID locations
+ = Addition
& = Bit-wise AND
PIC18FX220/X320
DS39592F-page 32 2010 Microchip Technology Inc.
PIC18F2320/
PIC18F4320
None SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800: 0FFFh) +
SUM (1000:17FFh) + SUM (1800:1FFF h) + (CONFIG1H & 0CF h) +
(CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) +
(CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) +
(CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) +
(CONFIG7H & 040h)
0E412h 0E368h
Boot Block SUM (0200:07FFh) + SUM (0800:0FFF h) + SUM (1000:1 7FFh) +
SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) +
(CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) +
(CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) +
(CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) +
SUM (IDs)
0E5E7h 0E59Ch
Boot Block/
Block 0 SUM (0800:0FFFh) + SUM (1000:17FFh) + SUM (1800:1FFFh) +
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) +
(CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) +
(CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs)
0EBE6h 0EB9Bh
Boot Block/
Block 0/
Block 1
SUM (1000:17FFh) + SUM (1800:1FFF h) + (CONFIG1H & 0CF h) +
(CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) +
(CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) +
(CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) +
(CONFIG7H & 040h) + SUM (IDs)
0F3E4h 0F399h
Boot Block/
Block 0/
Block 1/
Block 2
SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) +
(CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) +
(CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) +
(CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) +
SUM (IDs)
0FBE0h 0FB95h
Boot Block/
Block 0/
Block 1/
Block 2/
Block 3
(CONFIG1H & 0CFh) + (CONFIG2L & 0F h) + (CONFIG2H & 1F h) +
(CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) +
(CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) +
(CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs)
03D8h 03E2h
All (CONFIG1H & 0CFh ) + (CONFIG2L & 0Fh) + (CONFIG2H & 1F h) +
(CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) +
(CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) +
(CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs)
03D8h 03E2h
TABLE 5-5: CHECKSUM COMPUTATION – PIC18FX220/X320 (CONTINUED)
Device Code-Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CONFIG = Configuration Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM (IDs) = Byte-wise sum of lower four bits of all ID locations
+ = Addition
& = Bit-wise AND
2010 Microchip Technology Inc. DS39592F-page 33
PIC18FX220/X320
6.0 AC/DC CHARACTERISTICS
TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operati ng Temperature: 25C is recommended
Param
No. Sym Characteristic Min Max Units Conditions
D110 VIHH High-Vo ltage Programming Voltage on
MCLR/VPP 9.00 13.25 V
D110A VIHL Low-Voltage Programming Voltage on
MCLR/VPP 2.00 5.50 V
D111 VDD Supply Voltage during Programming 2.00 5.50 V Externally timed;
row erase and all
writes
4.50 5.50 V Self-timed; all
bulk erases
D112 IPP Programming Current on MCLR/VPP — 300 A
D113 IDDP Supply Current during Programming — 1 mA
D031 VIL Input Low Voltage VSS 0.2 VSS V
D041 VIH Input High Voltag e 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA
D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC
specifications
P2 Tsclk Seri al Clock (Program Clock, PG C)
Period 100 — ns VDD = 5.0V
1—sVDD = 2.0V
P2A TsclkL Serial Clock (Program Clock, PGC)
Low Time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P2B TsclkH Serial Clock (Program Clock, PGC)
High Time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P3 Tset1 Input Data Setup Time to Serial Clock 15 — ns
P4 Thld1 Input Data Hold Time from SCK 15 — ns
P5 Tdly1 Delay between 4-bit Command and
Command Operand 20 — ns
P5A Tdly1a Delay between 4-bit Command
Operand and Next 4-bit Command 20 — ns
P6 Tdly2 Delay between Last SCK of
Command Byte to First SCK of Read
of Data Word
20 — ns
P9 Tdly5 SCK High Time
(minimum programming time) 1—ms
P10 Tdly6 SCK Low Time after Programming
(high-voltage discharge time) 5—s
P11 Tdly7 Delay to allow Self-Timed Data Write or
Bulk Erase to Occur 10 — ms
P12 Thld2 Input Data Hold Time from
MCLR/VPP 2—s
P13 Tset2 VDD Setup Time to MCLR/VPP 100 — ns
P14 Tvalid Data Out Valid from SCK 10 — ns
P15 Tset3 PGM Setup Ti me to MCLR/VPP 2—s
PIC18FX220/X320
DS39592F-page 34 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39592F-page 35
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLA B, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In - Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLA B Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Tec hnology Inc orporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporat ed, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® co de hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39592F-page 36 2010 Microchip Technology Inc.
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