71V3556SA150BG8 - IDT, Integrated Device Technology Inc

JANUARY 2015

DSC-5281/12

Pin Description Summary

Description

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-

bit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBTTM, or

Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be

it read or write.

The IDT71V3556/58 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be

used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V3556/58

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three are

not asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed. The data bus will tri-state two cycles after chip is deselected

or a write is initiated.

Features

◆◆

◆128K x 36, 256K x 18 memory configurations

◆◆

◆Supports high performance system speed - 200 MHz (x18)

(3.2 ns Clock-to-Data Access)

◆◆

◆Supports high performance system speed - 166 MHz (x36)

(3.5 ns Clock-to-Data Access)

◆◆

◆ZBTTM Feature - No dead cycles between write and read

cycles

◆◆

◆Internally synchronized output buffer enable eliminates the

need to control OE

◆◆

◆Single R/W (READ/WRITE) control pin

◆◆

◆Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

◆◆

◆4-word burst capability (interleaved or linear)

◆◆

◆Individual byte write (BW1 - BW4) control (May tie active)

◆◆

◆Three chip enables for simple depth expansion

◆◆

◆3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)

◆◆

◆Optional- Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

◆◆

◆Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

-A

A d dre s s Inp uts Inp ut S yn chro no us

, CE

Chip Enab le s Input S ync hro no us

OE Output Enab le Input Asy nchro no us

R/WRead /Write Sig nal Input Sy nchro no us

CEN Clock Enable Input Synchronous

, BW

Indiv id ual By te Write Se le cts Input S ync hro no us

CLK Clock Input N/A

ADV/LD Advance b urst address / Load new address Input Synchronous

LBO Linear / Inte rle ave d Burs t Ord er Input Static

TMS Te s t Mo d e S e le c t Inp ut S y nc hro no us

TDI Te st Data Input Input S ync hro no us

TCK Test Clock Input N/A

TDO Te s t Data Outp ut Outp ut S ync hro no us

TRST JTAG Reset (Optional) Input Asynchronous

ZZ Sleep Mode Input Synchronous

I/O

-I/O

, I/O

-I/O

Data Inp ut / Outp ut I/ O S yn chro no us

, V

DDQ

Co re P o we r, I/ O Po we r Sup p l y S tatic

Ground Supply Static

5281 tbl 01

IDT71V3556S/XS

IDT71V3558S/XS

IDT71V3556SA/XSA

IDT71V3558SA/XSA

128K x 36, 256K x 18

3.3V Synchronous ZBT SRAMs

3.3V I/O, Burst Counter

Pipelined Outputs

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definition(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol Pin Function I/O Active Description

-A

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,

ADV/LD lo w, CEN lo w, and true chi p enab le s.

ADV/LD Ad vanc e / Load I N/A

ADV/LD is a synchro no us inp ut that is us ed to lo ad the internal re g isters with new ad d res s and co ntro l when it

is sampled low at the rising edge of clock with the chip selected. When ADV/LD is lo w with the chip

deselected, any burst in progress is terminated. When ADV/LD i s s am p le d hi g h the n the i nte rna l b u rs t c o unte r

is ad vanc ed for any burst that was in p rog ress . The e xte rna l ad d resse s are ig no red when A DV/LD is s amp led

high.

R/WRe ad / Wri te I N/ A R/W sig nal is a synchro nous inp ut that id entifie s whe ther the c urrent load cy cle initiated is a Re ad or Write

access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.

CEN Clock Enable I LOW Sync hronous Clock Enable Input. When CEN is samp le d hig h, all o ther synchrono us inp uts , includ ing c lo ck are

ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low

to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.

-BW

Ind iv id ual Byte

Write Enables ILOW

Sync hro nous byte write e nable s. Eac h 9-bit by te has its o wn ac tive lo w b y te write e nab le . On load wri te cyc le s

(Whe n R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW

-BW

) must be valid. The byte

write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is

sampled high. The appro priate byte(s) of data are written into the de vice two cycles later. BW

-BW

can all be

tied low if always doing write to the entire 36-bit word.

, CE

Chip Enab le s I LOW Synchronous active low chip enab le . CE

and CE

are used with CE

to e nable the IDT71V 3556/58. (CE

sampled high or CE

sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.

The ZB T

has a two cycle de select, i.e., the data bus will tri-state two clo ck cycles after deselect is initiate d.

Chip Enable I HIGH Sy nc hro no us activ e hig h c hip enab le . CE

is used with CE

and CE

to enable the chip. CE

has inv e rte d

polarity but otherwise identical to CE

and CE

CLK Clock I N/A This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with

respect to the rising edge of CLK.

I/O

-I/O

I/O

-I/O

Data Inp ut/ Outp ut I/O N/ A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and

triggered by the rising edge of CLK.

LBO Li near Burs t Orde r I LOW Burst order selection input. When LBO is high the Interleaved burst sequenc e is selected. When LBO is low

the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.

OE Output Enab le I LOW Asy nchro nous o utp ut e nab le . OE mus t b e lo w to re ad d ata fro m the 71V3556/58. When OE is high the I/O pins

are in a hig h-imp edance state. OE does not need to be actively controlled for read and write cycles. In normal

operation, OE can be tied low.

TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

TDI Te s t Data Inp ut I N/ A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal

pullup.

TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TDO Te s t Data Outp ut O N/ A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP

controller.

TRST JTAG Reset

(Optional) ILOW

Optional Asynchronous JTAG reset. Can be used to reset the TAP co ntroller, but not required. JTAG reset

o cc urs auto matic ally at po we r up and als o re se ts usi ng TMS and TCK p er IEEE 1149. 1. If no t use d TRST can

b e l eft flo ating. This p in has an inte rnal p ul lup . Onl y av ailab le in BGA p ac kag e .

ZZ Sleep Mode I HIGH Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to

its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal

pulldown.

Po we r Sup p ly N/ A N/A 3. 3V c o re p owe r s up ply.

DDQ

Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N/A Ground.

5281 tbl 02

The IDT71V3556/58 has an on-chip burst counter. In the burst

mode, the IDT71V3556/58 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst

counter (ADV/LD = HIGH).

The IDT71V3556/58 SRAMs utilize IDT's latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x

20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball

grid array (BGA) and a 165 fine pitch ball grid array (fBGA).

Description continued

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Recommended DC Operating

Conditions

NOTES:

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

Symbol Parameter Min. Typ. Max. Unit

Co re Sup p ly Vo ltag e 3.135 3. 3 3. 465 V

DDQ

I/O S up pl y Vo ltage 3. 135 3. 3 3.465 V

Supply Voltage 0 0 0 V

Input High Voltage - Inputs 2.0

____

+0.3 V

Input High Voltage - I/O 2.0

____

DDQ

+0.3

(2)

Inp u t Lo w Vo l tag e -0. 3

(1)

____

0.8 V

5281 tbl 04

Functional Block Diagram

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Recommended Oper ating

Temperature and Supply Voltage

Pin Configuration - 128K x 36

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin

supports ZZ (sleep mode).

Top View

100

TQFP

10099989796959493929190 8786858483828189 88

CLK

R/W

CEN

ADV/LD

(2)

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

LBO

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

5281 drw 02

(1)

I/O

(1)

I/O

(1)

I/O

/ZZ

(3)

Grade Temperature

(1)

DDQ

Comme rcial 0°C to +70°C 0V 3.3V±5% 3.3V ±5%

Industrial -40°C to +85°C 0V 3.3V±5% 3.3V±5%

5 281 t bl 05

NOTES:

1. TA is the "instant on" case temperature.

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings (1)

Pin Configuration - 256K x 18

100 Pin TQFP Capacitance(1)

(TA = +25° C, f = 1.0MHz)

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the

input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input

voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).

Top V iew

100 TQFP

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary; however,

the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp

up.

7. TA is the "instant on" case temperature.

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

Symbol Rating Commercial &

Industrial Values Unit

TERM

(2)

Terminal Voltage with

Re s p e c t to GND -0.5 to +4.6 V

TERM

(3,6)

Terminal Voltage with

Re s p e c t to GND -0.5 to V

TERM

(4,6)

Terminal Voltage with

Re s p e c t to GND -0. 5 to V

+0.5 V

TERM

(5,6)

Terminal Voltage with

Re s p e c t to GND -0.5 to V

DDQ

+0.5 V

(7)

Commercial

Operating Temperature -0 to +70 oC

Industrial

Operating Temperature -40 to +85 oC

BIAS

Temperature

Under Bias -55 to +125 oC

STG

Storage

Temperature -55 to +125 oC

Po we r Dis s ip atio n 2. 0 W

OUT

DC Outp ut Curre nt 50 mA

5281 t bl 06

10099989796959493929190 8786858483828189 88

CLK

R/W

CEN

ADV/LD

(2)

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

LBO

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

5281 drw 02a

(1)

/ZZ

(3)

Symbol Parameter

(1)

Conditions Max. Unit

Inp ut Cap ac itanc e V

= 3dV 5 pF

I/O

I/O Capacitance V

OUT

= 3dV 7 p F

5281 tbl 07

119 BGA Capacitance(1)

(TA = +25° C, f = 1.0MHz)

Symbol Parameter

(1)

Conditions Max. Unit

CIN Inp ut Cap ac itanc e V IN = 3dV 7 pF

CI/O I/ O Cap ac itanc e V OUT = 3dV 7 pF

5281 tbl 07a

165 fBGA Capacitance(1)

(TA = +25° C, f = 1.0MHz)

Symbol Parameter

(1)

Conditions Max. Unit

Inp ut Cap ac itanc e V

= 3dV TBD pF

I/O

I/O Cap ac itanc e V

OUT

= 3dV TBD pF

5281 tb l 07b

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

1234567

DDQ

BNC CE

ADV/LD A

DI/O

I/O

NC V

I/O

EI/O

I/O

DDQ

I/O

OE V

I/O

DDQ

GI/O

I/O

HI/O

I/O

R/WV

I/O

DDQ

KI/O

I/O

CLK V

I/O

LI/O

I/O

NC BW

I/O

DDQ

I/O

CEN V

I/O

DDQ

NI/O

I/O

PI/O

I/O

RNC A

LBO V

TNC NC A

NC NC/ZZ(5)

DDQ

5281 drw 13A

DD(1)

NC(2)

DD(1)

NC/TMS

(3)

NC/TDI

(3)

NC/TCK

(3)

NC/TDO

(3)

NC/TRST

(3,4)

1234567

AVDDQ A6A4NC(2) A8A16 VDDQ

BNC CE2 A3ADV/LD A9CE2NC

CA7A2VDD A13 A17 NC

DI/O8NC VSS NC VSS I/OP1 NC

ENC I/O9VSS VSS NC I/O7

FVDDQ NC VSS OE VSS I/O6VDDQ

GNC I/O10 BW2NC I/O5

HI/O11 NC VSS R/WVSS I/O4NC

JVDDQ VDD VDD VDD VDDQ

KNC I/O12 VSS CLK VSS NC I/O3

LI/O13 NC NC BW1I/O2NC

MVDDQ I/O14 VSS CEN VSS NC VDDQ

NI/O15 NC VSS A1VSS I/O1NC

PNC I/OP2 VSS A0VSS NC I/O0

RNC A5LBO VDD A12

TNC A10 A15 NC A14 A11 NC/ZZ(5)

UVDDQ VDDQ

5281drw 13B

DD(1)V

VSS

CE1

NC(2)

VDD(1) VDD(1)

NC/TMS(3) NC/TRST(3,4)

NC/TDO(3)

NC/TCK(3)

NC/TDI(3)

Pin Configuration - 128K x 36, 119 BGA

Pin Configuration - 256K x 18, 119 BGA

Top View

NOTES:

1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. G4 and A4 are reserved for future 8M and 16M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin T7 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Configuration - 128K x 36, 165 fBGA

Pin Configuration - 256K x 18, 165 fBGA

1234567891011

ANC

(2)

CE1 BW

CEN ADV/LD NC

(2)

BNC A

CLK R/WOE NC

(2)

CI/O

NC V

DDQ

NC I/O

DI/O

I/O

DDQ

I/O

EI/O

I/O

DDQ

I/O

FI/O

I/O

DDQ

I/O

GI/O

I/O

DDQ

I/O

(1)

NC V

NC NC NC/ZZ

(5)

JI/O

I/O

DDQ

I/O

KI/O

I/O

DDQ

I/O

LI/O

I/O

DDQ

I/O

MI/O

I/O

DDQ

I/O

NI/O

NC V

DDQ

SS NC/TRST

(3,4)

NC V

(1)

DDQ

NC I/O

PNCNC

(2)

NC/TDI

(3)

NC/TDO

(3)

RLBO NC

(2)

NC/TMS

(3)

NC/TCK

(3)

5281 tb l 25

1234567891011

ANC

(2)

NC CE

CEN ADV/LD NC

(2)

BNC A

NC BW

CLK R/WOE NC

(2)

CNC NCV

DDQ

NC I/O

DNC I/O

DDQ

NC I/O

ENC I/O

DDQ

NC I/O

FNCI/O

DDQ

NC I/O

GNC I/O

DDQ

NC I/O

(1)

NC V

NC NC NC/ZZ

(5)

JI/O

NC V

DDQ

I/O

KI/O

NC V

DDQ

I/O

LI/O

NC V

DDQ

I/O

MI/O

NC V

DDQ

I/O

NI/O

NC V

DDQ

SS NC/TRST

(3,4)

NC V

(1)

DDQ

NC NC

PNC NC

(2)

NC/TDI

(3)

NC/TDO

(3)

RLBO NC

(2)

NC/TMS

(3)

NC/TCK

(3)

5281 tb l 25a

NOTES:

1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Synchronous Truth Table (1)

Partial Truth Table for Writes (1)

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst

cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state

two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os remains

unchanged.

5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

CEN R/WChip

(5)

Enable ADV/LD BWxADDRESS

USED PRE VI OUS CYCLE CURRENT CYCLE I /O

(2 cycles l ater)

L L Select L Valid Exte rnal X LOAD WRITE D

(7)

L H Select L X External X LOAD READ Q

(7)

L X X H Valid Internal LOA D WRITE /

BURST WRITE BURST WRITE

(Advance burst counter)

(2)

(7)

L X X H X Internal LOA D READ /

BURS T RE AD BURST READ

(Advance burst counter)

(2)

(7)

L X Deselect L X X X DESELECT or STOP

(3)

HiZ

L X X H X X DE SE LE CT / NOOP NOOP HiZ

H X X X X X X SUSPEND

(4)

Pre vious Value

5 281 t b l 08

OPERATION R/WBW1BW2BW3

(3)

BW4

(3)

READ HXXXX

WRITE ALL BYTES LLLLL

WRITE BYTE 1 (I/O[0:7], I/OP1)

(2)

LLHHH

WRITE BYTE 2 (I/O[8:15], I/OP2)

(2)

LHLHH

WRITE BYTE 3 (I/O[16:23], I/OP3)

(2,3)

LHHLH

WRITE BYTE 4 (I/O[24:31], I/OP4)

(2,3)

LHHHL

NO WRITE L HHHH

5 281 t bl 09

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Linear Burst Sequence Table (LBO=VSS)

Interleaved Burst Sequence Table (LBO=VDD)

Functional Timing Diagram (1)

NOTES:

1. This assumes CEN, CE1, CE2, CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay

from the rising edge of clock.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Sequence 1 Sequence 2 Sequence 3 Sequence 4

A1 A0 A1 A0 A1 A0 A1 A0

First Address 000 110 11

Second Address 0 1 1 0 1 1 0 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address(1) 11000110

5281 tbl 11

Sequence 1 Sequence 2 Sequence 3 Sequence 4

A1 A0 A1 A0 A1 A0 A1 A0

First Address 000 110 11

Second Address 0 1 0 0 1 1 1 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address(1) 11100100

5 281 t b l 10

n+29

A29

C29

D/Q27

ADDRESS

(2)

(A0 - A16)

CONTROL

(2)

(R/W,ADV/LD,BWx)

DATA

(2)

I/O [0:31], I/O P[1:4]

CYCLE

CLOCK

n+30

A30

C30

D/Q28

n+31

A31

C31

D/Q29

n+32

A32

C32

D/Q30

n+33

A33

C33

D/Q31

n+34

A34

C34

D/Q32

n+35

A35

C35

D/Q33

n+36

A36

C36

D/Q34

n+37

A37

C37

D/Q35

5281 drw 03 ,

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Read Operation (1)

Device Operation - Showing Mixed Load, Burst,

Deselect and NOOP Cycles (2)

NOTES:

1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

2. H = High; L = Low; X = Don’t Care; Z = High Impedance.

Cycle Address R/WADV/LD CE

(1)

CEN BWxOE I/O Comments

0HL LLXXXLoad read

n+1 X X H X L X X X Burst read

n+2 A1HL LLXLQ0Lo ad re ad

n+3 X X L H L X L Q0+1 Deselect or STOP

n+4 X X H XLXLQ

1NOOP

n+5 A2HL LLXXZLoad read

n+6 X X H X L X X Z Burst read

n+7 X X L H L X L Q2Deselect or STOP

n+8 A3L L LLLLQ2+1 Load write

n+9 X X H X L L X Z B urst write

n+10 A4L L LLLXD3Load write

n+11 X X L H L X X D3+1 Deselect or STOP

n+12 X X H X L X X D4NOOP

n+13 A5L L L L L X Z Lo ad write

n+14 A6HL LLXXZLoad read

n+15 A7L L LLLXD5Load write

n+16 X X H XLLLQ

6Burst write

n+17 A8HL LLXXD7Load read

n+18 X X H X L X X D7+1 Burs t re ad

n+19 A9L L LLLLQ8Load write

5 281 t b l 12

Cycle Address R/WADV/LD CE

(2)

CEN BWxOE I/O Comments

0H L L L X X X Address and Control meet setup

n+1 X X X X L X X X Clock Setup Valid

n+2 X X X XXXLQ

0Contents of Address A0 Re ad Out

5 281 t b l 13

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Burst Write Operation (1)

Burst Read Operation (1)

Write Operation (1)

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance..

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Cycle Address R/WADV/LD CE

(2)

CEN BWxOE I/O Comments

H L L L X X X Address and Control meet setup

n+1 X X H X L X X X Clock Setup Valid , Ad vanc e Counter

n+2 X X H XLXLQ

Address A

Re ad Out, Inc . Co unt

n+3 X X H XLXLQ

0+1

Address A

0+1

Re ad Out, Inc . Co unt

n+4 X X H XLXLQ

0+2

Address A

0+2

Re ad Out, Inc . Co unt

n+5 A

HL LLXLQ

0+3

Address A

0+3

Read Out, Load A

n+6 X X H XLXLQ

Address A

Re ad Out, Inc . Co unt

n+7 X X H XLXLQ

Address A

Re ad Out, Inc . Co unt

n+8 A

HL LLXLQ

1+1

Address A

1+1

Read Out, Lo ad A

5281 tbl 14

Cycle Address R/WADV/LD CE

(2)

CEN BWxOE I/O Comments

0L L L L L X X Address and Control meet setup

n+1 X X X X L X X X Clock Setup Valid

n+2 X X X X L X X D0Write to Address A0

5 281 t b l 15

Cycle Address R/WADV/LD CE

(2)

CEN BWxOE I/O Comments

L L L L L X X Address and Control meet setup

n+1 X X H X L L X X Clock Setup Valid, Inc. Count

n+2 X X H X L L X D

Address A

Write , Inc. Count

n+3 X X H X L L X D

0+1

Address A

0+1

Write, Inc . Co unt

n+4 X X H X L L X D

0+2

Address A

0+2

Write , Inc. Count

n+5 A1 L L LLLXD

0+3

Address A

0+3

Write, Lo ad A

n+6 X X H X L L X D

Address A

Write, Inc . Co unt

n+7 X X H X L L X D

Address A

Write , Inc . Co unt

n+8 A

L L LLLXD

1+1

Address A

1+1

Write , Lo ad A

5281 tbl 16

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used (1)

Write Operation with Clock Enable Used (1)

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Cycle Address R/WADV/LD CE

(2)

CEN BWxOE I/O Comments

H L L L X X X Address and Control meet setup

n+1 X X X X H X X X Clo ck n+1 Ig nore d

n+2 A

HL LLXXXClock Valid

n+3 X X X X H X L Q

Cl o ck Igno re d . Data Q

is on the bus.

n+4 X X X X H X L Q

Cl o ck Igno re d . Data Q

is on the bus.

n+5 A

HL LLXLQ

Address A

Read out (bus trans. )

n+6 A

HL LLXLQ

Address A

Read out (b us trans. )

n+7 A

HL LLXLQ

Address A

Read out (bus trans. )

5 281 t b l 17

Cycle Address R/WADV/LD CE

(2)

CEN BWxOE I/O Comments

L L L L L X X Address and Control meet setup.

n+1 X X X X H X X X Clo ck n+1 Ig nored .

n+2 A

L L LLLXXClock Valid.

n+3 X X X X H X X X Clo ck Igno red .

n+4 X X X X H X X X Clo ck Igno red .

n+5 A

L L LLLXD

Write Data D

n+6 A

L L LLLXD

Write Data D

n+7 A

L L LLLXD

Write Data D

5 281 t b l 18

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

Read Operation with CHIP Enable Used (1)

Write Operation with Chip Enable Used (1)

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O(3) Comments

n X X L H L X X ? Deselected.

n+1 X X L H L X X ? Deselected.

n+2 A0H L L L X X Z Address and Control meet setup

n+3 X X L H L X X Z Deselected or STOP.

n+4 A1HL LLXLQ0Address A0 Re ad out. Lo ad A 1.

n+5 X X L H L X X Z Deselected or STOP.

n+6 X X L H L X L Q1Address A1 Read out. Deselected.

n+7 A2H L L L X X Z Address and control meet setup.

n+8 X X L H L X X Z Deselected or STOP.

n+9 X X L H L X L Q2Address A2 Re ad o ut. De se le c te d .

5281 tbl 19

Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O(3) Comments

n X X L H L X X ? Deselected.

n+1 X X L H L X X ? Deselected.

n+2 A

L L L L L X Z Address and Control meet setup

n+3 X X L H L X X Z Deselected or STOP.

n+4 A

L L LLLXD

Address D

Write in. Load A

n+5 X X L H L X X Z Deselected or STOP.

n+6 X X L H L X X D

Address D

Write in. Deselected.

n+7 A

L L L L L X Z Address and control meet setup.

n+8 X X L H L X X Z Deselected or STOP.

n+9 X X L H L X X D

Address D

Write in. Deselected.

5281 tbl 20

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)

Figure 2. Lumped Capacitive Load, Typical Derating

AC Test Conditions

(VDDQ = 3.3V)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)

Figure 1. AC Test Load

AC Test Loads

NOTE:

1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled if they are not actively driven in the application.

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.

4. Only available in 256K x 18 configuration.

DDQ

50

I/O Z

=50

5281 drw 04 ,

20 30 50 100 200

tCD

(Typical, ns)

Capacitance (pF)

5281 drw 05

Symbol Parameter Test Conditions Min. Max. Unit

| Input Leak age Current V

= Max., V

= 0V to V

DD ___

5µA

|L BO, J TAG and ZZ Inp ut Le akag e Current

(1)

= Max., V

= 0V to V

DD ___

30 µA

| Output Leakage Current V

OUT

= 0V to V

DDQ

, Device Deselected

___

5µA

Output Lo w Vo ltage I

= +8mA, V

= Min.

___

0.4 V

Outp ut Hig h Vo ltag e I

= -8mA, V

= Min. 2.4

___

5281 tbl 21

Input Pulse Levels

Inp ut Ris e /Fall Tim e s

Inp ut Tim ing Re fe re nc e Le v e ls

Output Timing Re fe renc e Leve ls

AC Test Lo ad

0 to 3V

2ns

1.5V

See Figure 1

5 281 t bl 23

Symbol Parameter Test Conditions

200MHz

(4)

166MHz 133MHz 100MHz

UnitCom'l Only Com'l Ind Com'l Ind Com'l Ind

Operating Power

Supply Current Device Selected, Outputs Open,

ADV/LD = X, V

= Max.,

> V

or < V

, f = f

MAX

(2)

400 350 360 300 310 250 255 mA

SB1

CMOS Stand by

Po wer Sup p ly Current Device Deselected, Outputs Open,

= Max., V

> V

or < V

, f

= 0

(2,3)

40 40 45 40 45 40 45 mA

SB2

Clo ck Running Po we r

Supply Current Device Deselected, Outputs Open,

= Max., V

> V

or < V

, f

= f

MAX

(2.3)

130 120 130 110 120 100 110 mA

SB3

Id l e P o wer

Supply Current Device Selected, Outputs Open,

CEN > V

, V

= Max.,

> V

or < V

, f = f

MAX

(2,3)

40 40 45 40 45 40 45 mA

5281 tb l 22

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)

NOTES:

1. tF = 1/tCYC.

2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.

3. Transition is measured ±200mV from steady-state.

4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.

5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The

specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a

Max. parameter (worse case at 70 deg. C, 3.135V).

6. Commercial temperature range only. Only available in 256K x 18 configuration.

200MHz

(6)

166MHz 133MHz 100MHz

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

CYC

Clock Cycle Time 5

____

7.5

____

(1)

Clo ck Fre que nce

____

200

____

166

____

133

____

100 MHz

(2)

Clock High Pulse Width 1.8

____

1.8

____

2.2

____

3.2

____

(2)

Clock Low Pulse Width 1.8

____

1.8

____

2.2

____

3.2

____

Output Parameters

C lo c k Hig h to Valid Data

____

3.2

____

3.5

____

4.2

____

5ns

CDC

Clo ck Hig h to Data Chang e 1

____

CLZ

(3,4,5)

Clo ck Hi gh to Outp ut Ac tiv e 1

____

CHZ

(3,4,5)

Clock High to Data High-Z 13131313.3ns

Output Enable Access Time

____

3.2

____

3.5

____

4.2

____

5ns

OLZ

(3,4)

Outp ut E na b l e Lo w to Data A ctiv e 0

____

OHZ

(3,4)

Output Enable High to Data High-Z

____

3.5

____

3.5

____

4.2

____

5ns

Set Up Times

Clo ck Enable Se tup Time 1.5

____

1.5

____

1.7

____

2.0

____

Address Setup Time 1.5

____

1.5

____

1.7

____

2.0

____

Data In Se tup Ti me 1. 5

____

1.5

____

1.7

____

2.0

____

Re ad /Write (R/ W) Se tup Time 1.5

____

1.5

____

1.7

____

2.0

____

SADV

Ad vanc e /Lo ad (ADV/ LD) Se tup Time 1. 5

____

1.5

____

1.7

____

2.0

____

Chip Enable/Select Setup Time 1.5

____

1.5

____

1.7

____

2.0

____

Byte Write Enable (BWx) Setup Time 1.5

____

1.5

____

1.7

____

2.0

____

Hold Times

Clo ck Enable Hold Time 0.5

____

0.5

____

0.5

____

0.5

____

Address Hold Time 0.5

____

0.5

____

0.5

____

0.5

____

Data In Ho l d Tim e 0. 5

____

0.5

____

0.5

____

0.5

____

Re ad /Write (R/ W) Hold Time 0.5

____

0.5

____

0.5

____

0.5

____

HADV

Ad vanc e /Lo ad (ADV/ LD) Hold Time 0.5

____

0.5

____

0.5

____

0.5

____

Chip Enab le/Se lec t Hold Time 0.5

____

0.5

____

0.5

____

0.5

____

Byte Write Enable (BWx) Hold Time 0.5

____

0.5

____

0.5

____

0.5

____

5281 tbl 24

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle (1,2,3,4)

NOTES:

1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence

of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.

4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control

are loaded into the SRAM.

ADV/LD

(CENhigh,eliminates

currentL-Hclockedge)

HADV

Pipeline

Read

(BurstWrapsaround

toinitialstate)

CDC

CLZ

CHZ

CDC

R/W

CLK

CEN

ADDRESS

DATA

OUT

A1A2

CYC

SADV

BurstPipelineRead

Pipeline

Read

-BW

5281drw06

(2)

Q(A

2+3

)Q(A

)

Q(A

2+2

)

Q(A

2+2

)

Q(A

2+1

)

Q(A

)

Q(A

)

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

1. D (A 1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence

of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.

4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address

and control are loaded into the SRAM.

5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information

comes in two cycles before the actual data is presented to the SRAM.

Timing Wa veform of Write Cycles (1,2,3,4,5)

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two

cycles before the actual data is presented to the SRAM.

Timing Waveform of Combined Read and Write Cycles (1,2,3)

R/W

CLK

CEN

ADV/LD

ADDRESS

,CE

2(2)

-BW

DATA

OUT

Q(A

)

Q(A

)Q(A

)

Read

CHZ

5281drw08

Write

CLZ

D(A

)D(A

)

CDC

D(A

)

Write

CYC

HADV

SADV

DATA

Read

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition

did not occur. All internal registers in the SRAM will retain their previous state.

4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information

comes in two cycles before the actual data is presented to the SRAM.

Timing Waveform of CEN Operation (1,2,3,4)

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of CS Operation (1,2,3,4)

NOTES:

1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not

occur. All internal registers in the SRAM will retain their previous state.

4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two

cycles before the actual data is presented to the SRAM.

R/W

CLK

ADV/LD

ADDRESS

DATA

OUT

Q(A

)

CLZ

CHZ

CDC

CYC

DATA

CEN

HADV

SADV

5281drw10

Q(A

)Q(A

)

D(A

)

BW1-BW4

CE1,CE2

(2)

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST(3)

JCD

JDC

tJRST

JCYC

tJRSR

tJF tJCL tJR tJCH

M5281 drw 01

Symbol Parameter Min. Max. Units

JCYC

JTAG Clock Input Period 100

____

JCH

JTAG Clock HIGH 40

____

JCL

JTAG Clock Low 40

____

JTAG Clock Rise Time

____

(1)

JTAG Clo ck Fall Time

____

(1)

JRST

JTAG Reset 50

____

JRSR

J TAG Re s e t Re co ve ry 50

____

JCD

J TA G Data O utp ut

____

20 ns

JDC

J TAG Data Outp ut Ho ld 0

____

JTAG Setup 25

____

JTAG Hold 25

____

I5281 tbl 01

Regi ster Name Bit S ize

Instruc ti o n (IR) 4

Bypass (BYR) 1

J TA G Id e nti fic ati o n (J IDR) 32

Boundary Scan (BSR) Note (1)

I5 2 81 tbl 03

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

JTAG AC Electrical

Characteristics(1,2,3,4)

Scan Register Sizes

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

Instruction Field Value Descripti on

Revision Numbe r (31: 28) 0x2 Rese rve d for ve rsio n numb er.

IDT De vice ID (27: 12) 0x208, 0x20A De fine s IDT p art numb e r 71V3556SA and 71V3558S A, re sp e ctive ly.

IDT JEDEC ID (11:1) 0x33 Allows unique identifi cation of de vice vendor as IDT.

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.

I5281 tbl 02

JTAG Identification Register Definitions (SA Version only)

Instruction Description OPCODE

EXTEST Forces contents of the bound ary scan cells onto the device outputs

(1)

Places the boundary scan registe r (BSR) between TDI and TDO. 0000

SAMPLE/PRELOAD

Places the boundary scan registe r (BSR) between TDI and TDO.

SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be captured

in the b oundary sc an c e lls and shifte d se rially thro ug h TDO. PRELOAD

al lo w s d ata to b e inp ut s e ri all y into the b ound ary s can c e lls via the TDI.

0001

DEVICE_ID Loads the JTAG ID register (JIDR) with the vendor ID code and places

the register between TDI and TDO. 0010

HIGHZ Places the bypass register (BYR) be tween TDI and TDO. Forces all

device o utput drivers to a High-Z state. 0011

RESERVED

Several combinations are reserved. Do not use codes other than those

ide ntified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,

VALIDATE and BYPASS instructions.

0100

RESERVED 0101

RESERVED 0110

RESERVED 0111

CLAMP Uses BYR. Forces contents of the bound ary scan cells onto the device

outputs. Places the bypass registe r (BYR) between TDI and TDO. 1000

RESERVED

Same as ab ove .

1001

RESERVED 1010

RESERVED 1011

RESERVED 1100

VALIDATE Automatically loaded into the instruction register whenever the TAP

co ntro lle r passe s thro ug h the CAPTURE-IR s tate. The lo we r two b its '01'

are mandate d b y the IEEE std. 1149. 1 sp e cific ation. 1101

RESERVED Same as above. 1110

BYPASS The BYPASS instruction is used to truncate the boundary scan register

as a s ing le bit in le ngth. 1111

I5281 tbl 04

Available JTAG Instructions

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of OE Operation (1)

NOTE:

1. A read operation is assumed to be in progress.

Ordering Information

DATA

OUT

OHZ

OLZ

Valid

5281 drw 11

6.42

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™™

™™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Datasheet Document History

6/30/99 Updated to new format

8/23/99 Added Smart ZBT functionality

Pg. 4, 5 Added Note 4 and changed Pins 38, 42, and 43 to DNU

Pg. 6 Changed U2–U6 to DNU

Pg. 14 Added Smart ZBT AC Electrical Characteristics

Pg. 15 Improved tCD and tOE(MAX) at 166MHz

Revised tCHZ(MIN) for f ≤ 133 MHz

Revised tOHZ (MAX) for f ≤ 133 MHz

Improved tCH, tCL for f ≤ 166 MHz

Improved setup times for 100–200 MHz

Pg. 22 Added BGA package diagrams

Pg. 24 Added Datasheet Document History

10/4/99 Pg. 14 Revised AC Electrical Characteristics table

Pg. 15 Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz

12/31/99 Removed Smart functionality

Added Industrial Temperature range offerings at the 100 to 166MHz speed grades.

04/30/00 Pg. 5, 6 Insert clarification note to Recommended Operating Temperature and Absolute Max

Ratings tables

Pg. 6 Add BGA capacitance table

Pg. 5,6, 7 Add note to TQFP and BGA Pin Configurations; corrected typo in pinout

Pg. 21 Add 100pinTQFP package Diagram Outline

05/26/00 Add new package offering, 13 x 15mm 165 fBGA

Pg. 23 Correct 119BGA Package Diagram Outline

07/26/00 Pg. 5-8 Add ZZ sleep mode reference note to BG119, PK100 and BQ165 pinouts

Pg. 8 Update BQ165 pinout

Pg. 23 Update BG119 package diagram outline dimensions

10/25/00 Remove Preliminary status

Pg. 8 Add note to pin N5 on BQ165, reserved for JTAG TRST

1/24/02 Pg. 1-8, 15,22,23,27 Added JTAG "SA" version functionality

9/30 /04 Pg. 7 Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)

and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).

Pg. 27 Adding "Restricted hazardous substance device" to ordering information.

10/18/06 Pg. 1, 26 Added X generation die step to data sheet.

08/11/08 Pg. 1, 15, 16, 27 Remove 200MHz on 128K x 36 configuration.

10/14/10 Pg. 28 Removed IDT from the ordering information

01/20/15 Pg 24 -26 Removed PSC Package Diagram Outlines. See idt.com for PSC details

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com

San Jose, CA 95138 fax: 408-284-2775 408-284-4532