NJW1109 Headphone Amplifier with Electronic Volume PACKAGE OUTLINE GENERAL DESCRIPTION The NJW1109 is a headphone amplifier with electronic volume. It includes widely gain adjustable volume, +20 to -80 dB, and mute 2 function. These are controlled by I C bus. The NJW1109 is suitable for headphone output on TV set. NJW1109D FEATURES Operating Voltage Electronic Volume 2 I C Bus Interface Bi-CMOS Technology Package Outline NJW1109M NJW1109V 7.5 to 10 V +20dB to -80dB / 0.5dB step, Mute DIP14, DMP14, SSOP14 BLOCK DIAGRAM CAPa SDA SCL 2 IC Interface ADR IN a VOL OUTa IN b VOL OUTb Bias CAPb Vref V+ GND PIN FUNCTION 1 7 14 8 No. 1 SYMBOL No. 8 SYMBOL 2 OUTb Bch Output 9 Vref Reference voltage stabilized capacitor connect terminal 3 N.C. No Connect 10 INa Ach Input 4 CAPb 11 CAPa 5 INb Balance control click noise absorbing capacitor connect terminal Bch Input 12 N.C. Volume control click noise absorbing capacitor connect terminal No Connect 6 ADR I2C Bus Slave Address Select 13 OUTa Ach Output 7 SDA I2C Bus Data Input 14 GND Ground V+ FUNCTION Power Supply SCL FUNCTION I2C Bus Clock Input -1- NJW1109 ABSOLUTE MAXIMUM RATING (Ta=25C) PARAMETER SYMBOL + Supply Voltage V Power Dissipation PD RATING UNIT V mW C Operating Temperature Range Topr 12 500 (DIP14) 500* (DMP14) 440* (SSOP14) -20 to +75 Storage Temperature Range Tstg -40 to +125 C *(Note) EIA/JEDEC STANDARD Test board(76.2 x 114.3 x 1.6mm, 2layers, FR-4)mounting ELECTRICAL CHARACTERISTICS (V =9V, VIN=-20dBV, f=1kHz, RL=100, VOL = 0dB , Ta=25C) POWER SUPPLY + PARAMETER SYMBOL TEST CONDITION + Operating Voltage V Operating Current ICC Reference Voltage VREF No Signal MIN. TYP. MAX. UNIT 7.5 9 10 V - 5 8 mA 4.0 4.5 5.0 V MIN. TYP. MAX. UNIT 18 20 22 dB AMPLIFIER PARAMETER SYMBOL TEST CONDITION Volume Maximum Gain GVMAX VOL = +20dB setting Volume Minimum Gain GVMIN VOL = -80dB setting Voltage Gain Channel Balance Gv VOL = 0dB setting Maximum Input Voltage VIM Output Power PO Total Harmonic Distortion Channel Separation THD CS VOL = -10dB setting THD=3% VOL = 10dB, THD=10% VOL = 0dB setting Rg=600, Vin = 0dBV -80 -1.5 8.9 (2.8) 70 0 9.5 (3.0) 100 1.5 - dB dBV (Vrms) mW - 0.1 1 % 70 80 - dB -90 -85 (56) -95 (18) - dB dBV - -100 -95 (18) -105 (5.6) 70 MIN. TYP. MAX. UNIT + Mute Level Mute VOL = Mute, Vin = 0dBV - Output Noise Voltage 1 VNO1 Rg=0, A-Weighted - Output Noise Voltage 2 Power Supply Ripple Rejection VNO2 PSRR VOL = Mute Rg=0, A-Weighted Vripple=-20dBV, Rg=0 - - (Vrms) dBV (Vrms) dB CONTROL PARAMETER SYMBOL TEST CONDITION High Level Input Voltage VADRH High : Slave Address 84H V /2 - - V Low Level Input Voltage VADRL Low : Slave Address 80H - - 1.0 V -2- NJW1109 2 !TIMING ON THE I C BUS (SDA,SCL) SDA tf tr tHD:STA tf tSU:DAT tSP tBUF tr SCL tHD:STA tSU:STA S tLOW tHD:DAT tSU:STO tHIGH Sr P S 2 !CHARACTERISTICS OF I/O STAGES FOR I C BUS (SDA,SCL) 2 I C BUS Load Conditions STANDARD MODE : FAST MODE : Pull up resistance 4k (Connected to +5V), Load capacitance 200pF (Connected to GND) Pull up resistance 4k (Connected to +5V), Load capacitance 50pF (Connected to GND) PARAMETER SYMBOL Standard mode Fast mode MIN. TYP. MAX. MIN. TYP. MAX. UNIT Low Level Input Voltage VIL 0.0 - 1.5 0.0 - 1.5 V High Level Input Voltage VIH 2.5 - 5.0 2.5 - 5.0 V Low level output voltage (3mA at SDA pin) VOL 0 - 0.4 0 - 0.4 V Ii -10 - 10 -10 - 10 A Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax -3- NJW1109 2 !CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I C-BUS DEVICES PARAMETER Standard mode SYMBOL Fast mode UNIT MIN. TYP. MAX. MIN. TYP. MAX. fSCL - - 100 - - 400 kHz tHD:STA 4.0 - - 0.6 - - s Low period of the SCL clock tLOW 4.7 - - 1.3 - - s High period of the SCL clock tHIGH 4.0 - - 0.6 - - s tSU:STA 4.7 - - 0.6 - - s tHD:DAT 0 - - 0 - - s tSU:DAT 250 - - 100 - - ns Rise time of both SDA and SCL signals tr - - 1000 - - 300 ns Fall time of both SDA and SCL signals tf - - 300 - - 300 ns tSU:STO 4.0 - - 0.6 - - s Bus free time between a STOP and START condition tBUF 4.7 - - 1.3 - - s Capacitive load for each bus line Cb - - 400 - - 400 pF Noise margin at the Low level VnL 0.5 - - 0.5 - - V Noise margin at the High level VnH 1 - - 1 - - V SCL clock frequency Hold time (repeated) START condition. Set-up time for a repeated START condition Data hold time NOTE) Data set-up time Set-up time for STOP condition Cb ; total capacitance of one bus line in pF. NOTE). Data hold time : tHD:DAT Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge. The SDA block in the NJW1109 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not providing a hold time of at least 300nsec for the SDA in the master device. The time-consists of the data-delay-circuit of the SDA terminal are as follows. TLH RP*CD THL RD*CD (a) Low level ! High level : (b) High level ! Low level : In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward voltage (Vf) as much as possible. VDD RP RP SCL MASTER SBD SDA RD -4- CD NJW1109 NJW1109 TERMINAL DESCRIPTION No. SYMBOL FUNCTION 5 INb Bch Input 10 INa Ach Input EQUIVALENT CIRCUIT VOLTAGE V+/2 17k 2 OUTb Bch Output 13 OUTa Ach Output V+/2 12k 4 11 CAPb Balance control click noise absorbing capacitor connect terminal CAPa Volume control click noise absorbing capacitor connect terminal 8k 3.8V 8k 3.1V -5- NJW1109 TERMINAL DESCRIPTION No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE 4k 2 6 ADR I C Bus Slave Address Select - 12k 4k 2 7 SDA I C Bus Data Input 8 SCL I C Bus Clock Input - 2 12k 200k 9 Vref 1.3k Reference voltage stabilized capacitor connect terminal V+/2 200k 1 V+ Power Supply - - 14 GND Ground - - -6- NJW1109 TEST CIRCUIT TEST CIRCUIT 1 (GVMAX, GVMIN, Gv, VIM, PO, THD, Mute) Input B Output B 100 VADRL VADRH BPF:400Hz to 30KHz 100F 0.47F V+ 1F 7 6 5 4 3 2 1 SDA ADR INb CAPb NC OUTb V+ OUTa GND 10F VOL 2 I C Bus Interface VOL Bias SCL Vref INa CAPa NC 8 9 10 11 12 10F 13 14 100F 0.47F Output A 1F 100 Input A BPF:400Hz to 30KHz -7- NJW1109 TEST CIRCUIT 2 (Icc, VREF, VNO1,VNO2) Input B Output B 100 VADRL VADRH A-Weighted 100F 0.47F V+ 1F [Icc] 7 6 5 4 3 2 1 SDA ADR INb CAPb NC OUTb V+ OUTa GND 10F VOL 2 I C Bus Interface VOL Bias SCL Vref INa CAPa NC 8 9 10 11 12 [VREF] 13 14 100F 10F 0.47F Output A 1F 100 Input A -8- A-Weighted NJW1109 TEST CIRCUIT 3 (CS) Output B Input B Rg=600 VADRL VADRH 100 BPF:400Hz to 30KHz 100F 1F V+ 0.47F 7 6 5 4 3 2 1 SDA ADR INb CAPb NC OUTb V+ OUTa GND 10F VOL Rg=600 2 I C Bus Interface VOL Bias SCL Vref INa CAPa NC 8 9 10 11 12 0.47F 13 14 100F 10F Output A 1F BPF:400Hz to 30KHz Rg=600 Input A 100 -9- NJW1109 TEST CIRCUIT 4 (PSRR) Input B VADRL VADRH Output B 100 Rg=0 BPF:400Hz to 30KHz 100F 1F 0.47F 7 6 5 4 3 2 1 SDA ADR INb CAPb NC OUTb V+ OUTa GND 10F V+ VOL 2 I C Bus Interface VOL Bias SCL Vref INa CAPa NC 8 9 10 11 12 0.47F 10F 13 14 100F Output A Rg=0 1F 100 Input A - 10 - BPF:400Hz to 30KHz NJW1109 APPLICATION CIRCUIT Input B 30 30 Output B 100F 0.47F 1F V+ 7 6 5 4 3 2 1 SDA ADR INb CAPb NC OUTb V+ OUTa GND 10F VOL 2 I C Bus Interface VOL Bias SCL Vref INa CAPa NC 8 9 10 11 12 10F 13 14 100F 0.47F 30 30 Output A 1F Input A Mute Mute - 11 - NJW1109 2 DEFINITION OF I C REGISTER 2 I C BUS FORMAT MSB S LSB Slave Address 1bit 8bit MSB LSB A Select Address 1bit 8bit MSB A 1bit LSB Data A P 8bit 1bit 1bit S: Starting Term A: Acknowledge Bit P: Ending Term SLAVE ADDRESS MSB LSB 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 80H (ADR = Low) 84H (ADR = High) SELECT ADDRESS The auto-increment function cycles the select address as follows. 00H01H00H Select Address BIT D7 D6 D5 D4 00H 01H D3 D2 D1 D0 VOL CHS BAL Don't Care !CONTROL REGISTER DEFAULT VALUE Control register default value is all "0". Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 00H 0 0 0 0 0 0 0 0 01H 0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0 D2 D1 D0 !CONTROL COMMAND TABLE a) Master Volume Select Address BIT D7 D6 00H VOL *VOL : Master Volume Attenuation level : +20 to -80dB(0.5dB/step), MUTE b) Balance BIT Select Address D7 01H CHS D6 D5 D4 BAL *CHS : Balance channel select "0" : Ach "Bch is attenuated" "1" : Bch "Ach is attenuated" *BAL : Ach and Bch Ach and Bch Balance Balance Level : 0 to -30dB (1dB/Step) , MUTE - 12 - D3 Don't Care NJW1109 !CONTROL COMMAND TABLE a) Master Volume (Select Address: 00H) Volume level : +20 to -80dB(0.5dB/step), MUTE VOL Gain(dB) HEX D7 D6 D5 D4 D3 D2 D1 D0 20 FF 1 1 1 1 1 1 1 1 19.5 FE 1 1 1 1 1 1 1 0 19 FD 1 1 1 1 1 1 0 1 18.5 FC 1 1 1 1 1 1 0 0 18 FB 1 1 1 1 1 0 1 1 17.5 FA 1 1 1 1 1 0 1 0 17 F9 1 1 1 1 1 0 0 1 16.5 F8 1 1 1 1 1 0 0 0 16 F7 1 1 1 1 0 1 1 1 15.5 F6 1 1 1 1 0 1 1 0 15 F5 1 1 1 1 0 1 0 1 14.5 F4 1 1 1 1 0 1 0 0 14 F3 1 1 1 1 0 0 1 1 13.5 F2 1 1 1 1 0 0 1 0 13 F1 1 1 1 1 0 0 0 1 12.5 F0 1 1 1 1 0 0 0 0 12 EF 1 1 1 0 1 1 1 1 11.5 EE 1 1 1 0 1 1 1 0 11 ED 1 1 1 0 1 1 0 1 10.5 EC 1 1 1 0 1 1 0 0 10 EB 1 1 1 0 1 0 1 1 9.5 EA 1 1 1 0 1 0 1 0 9 E9 1 1 1 0 1 0 0 1 8.5 E8 1 1 1 0 1 0 0 0 8 E7 1 1 1 0 0 1 1 1 7.5 E6 1 1 1 0 0 1 1 0 7 E5 1 1 1 0 0 1 0 1 6.5 E4 1 1 1 0 0 1 0 0 6 E3 1 1 1 0 0 0 1 1 5.5 E2 1 1 1 0 0 0 1 0 5 E1 1 1 1 0 0 0 0 1 4.5 E0 1 1 1 0 0 0 0 0 4 DF 1 1 0 1 1 1 1 1 3.5 DE 1 1 0 1 1 1 1 0 3 DD 1 1 0 1 1 1 0 1 -79.5 38 0 0 1 1 1 0 0 0 -80 37 0 0 1 1 0 1 1 1 Mute 00 0 0 0 0 0 0 0 0 - 13 - NJW1109 b) Balance (Select Address: 01H) Channel Setting (CHS) D7 Attenuated Bch Gain Attenuated Ach Gain 0 1 D6 D5 BAL D4 D3 D2 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 -23 -24 1 1 0 1 1 0 1 0 1 0 -25 -26 -27 -28 -29 -30 MUTE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Gain(dB) - 14 - Balance level : 0 to -30dB(1dB/step), MUTE NJW1109 [CAUTION] The specifications on this data book are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 15 - Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NJR: NJW1109V-TE1 NJW1109M-TE2 NJW1109D NJW1109M NJW1109M-TE1