IS61SP12832
IS61SP12836 ISSI®
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
02/11/04
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA packages
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
DESCRIPTION
The ISSI IS61SP12832 and IS61SP12836 are high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 131,072
words by 32 bits and 36 bits, fabricated with ISSI's ad-
vanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All syn-
chronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls
DQc, BW4 controls DQd, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be
written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FEBRUARY 2004
FAST ACCESS TIME
Symbol Parameter -166 -133 -5 Units
tKQ Clock Access Time 3.5 4 5 ns
tKC Cycle Time 6 7. 5 1 0 ns
Frequency 166 133 100 MHz
128K x 32, 128K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
IS61SP12832
IS61SP12836 ISSI
®
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/11/04
BLOCK DIAGRAM
17
BINARY
COUNTER
A16-A0
BW1
GW
CLR
CE
CLK Q0
Q1
MODE
A0'
A0
A1 A1'
CLK
ADV
ADSC
ADSP
15 17
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW4
CE
CE2
CE2
BW2
BW3
128K x 32/128K x 36
MEMORY ARRAY
32 or 36
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32 or 36
OE
432 or 36
OE DQ[31:0]
or
DQ[35:0]
IS61SP12832
IS61SP12836 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
02/11/04
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BW1-BW4 Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ Isolated Output Buffer Supply: +3.3V
ZZ Snooze Enable
NC
DQb8
DQb7
VDDQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VDDQ
DQb2
DQb1
GND
NC
VDD
ZZ
DQa8
DQa7
VDDQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VDDQ
DQa2
DQa1
NC
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADS
C
ADSP
ADV
A8
A9
NC
DQc1
DQc2
VDDQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VDDQ
DQc7
DQc8
NC
VDD
NC
GND
DQd1
DQd2
VDDQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VDDQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
128K x 32
100-Pin TQFP
IS61SP12832
IS61SP12836 ISSI
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/11/04
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2
-
A16 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BW1-BW4 Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
GND Ground
VDDQ
Isolated Output Buffer Supply:
+3.3V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQc1
DQc2
VDDQ
DQc5
DQc7
VDDQ
DQd1
DQd4
VDDQ
DQd6
DQd8
NC
NC
VDDQ
A6
CE2
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VDD
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
NC
A4
A3
A2
GND
GND
GND
BW3
GND
NC
GND
BW4
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
A11
NC
A8
A9
A12
GND
GND
GND
BW2
GND
NC
GND
BW1
GND
GND
GND
NC
A14
NC
A16
CE2
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VDD
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VDDQ
NC
NC
DQb8
DQb7
VDDQ
DQb3
DQb1
VDDQ
DQa8
DQa6
VDDQ
DQa2
DQa1
NC
ZZ
VDDQ
1 2 3 4 5 6 7
DQPb
DQb8
DQb7
VDDQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VDDQ
DQb2
DQb1
GND
NC
VDD
ZZ
DQa8
DQa7
VDDQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VDDQ
DQa2
DQa1
DQPa
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADS
C
ADSP
ADV
A8
A9
DQPc
DQc1
DQc2
VDDQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VDDQ
DQc7
DQc8
NC
VDD
NC
GND
DQd1
DQd2
VDDQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VDDQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
128K x 36
119-pin PBGA (Top View) 100-Pin TQFP
IS61SP12832
IS61SP12836 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
02/11/04
TRUTH TABLE
Address
Operation Used CECE
CECE
CE CE2 CE2CE2
CE2CE2
CE2 ADSPADSP
ADSPADSP
ADSP ADSCADSC
ADSCADSC
ADSC ADVADV
ADVADV
ADV WRITEWRITE
WRITEWRITE
WRITE OEOE
OEOE
OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None X X H H L X X X High-Z
Deselected, Power-down None X L X H L X X X High-Z
Read Cycle, Begin Burst External L H L L XXXXQ
Read Cycle, Begin Burst External L H L H L X Read X Q
Write Cycle, Begin Burst External L H L H L X Write X D
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X D
Write Cycle, Continue Burst Next H X X X H L Write X D
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X D
Write Cycle, Suspend Burst Current H X X X H H Write X D
PARTIAL TRUTH TABLE
Function GWGW
GWGW
GW BWEBWE
BWEBWE
BWE BW1BW1
BW1BW1
BW1 BW2BW2
BW2BW2
BW2 BW3BW3
BW3BW3
BW3 BW4BW4
BW4BW4
BW4
Read H H XXXX
Read H L HHHH
Write Byte 1 H L L H H H
Write All Bytes H LLLLL
Write All Bytes L XXXXX
IS61SP12832
IS61SP12836 ISSI
®
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/11/04
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
TSTG Storage Temperature –55 to +150 ° C
PDPower Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VDDQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to VDD + 0.5 V
for Address and Control Inputs
VDD Voltage on VDD Supply Relative to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
IS61SP12832
IS61SP12836 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
02/11/04
OPERATING RANGE
Range Ambient Temperature VDD
Commercial 0°C to +70°C 3.3V, +10%, –5%
Industrial –40°C to +85°C 3.3V, +10%, –5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VDDQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Leakage Current GND ≤ VIN ≤ VDDQ(2) Com. –2 2 µA
Ind. –5 5
ILO Output Leakage Current GND ≤ VOUT ≤ VDDQ, OE = VIH Com. –2 2 µA
Ind. –5 5
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-166 -
133
-5
Symbol Parameter Test Conditions
Max. Max Max. Uni
t
ICC AC Operating Device Selected, Com. 290 230
—
mA
Supply Current All Inputs = VIL or VIH Ind. 300
—
220 mA
OE = VIH, VDD = Max.
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, Com. 70 70
—
mA
VDD = Max., Ind. 80
—
75 mA
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
IZZ Power-down Mode ZZ = VDD Com. 15 15
—
mA
Current Clock Running Ind. 20
—
20 mA
All Inputs ≤ GND + 0.2V
or ≥ VDD – 0.2V
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VDD.
2. The MODE pin should be tied to VDD or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V
or ≥ VDD – 0.2V.
IS61SP12832
IS61SP12836 ISSI
®
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/11/04
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 p F
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Output
Buffer
ZO
= 50Ω
1.5V
50Ω
30 pF
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 1 Figure 2
IS61SP12832
IS61SP12836 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
02/11/04
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fMAX
(3)
Clock Frequency — 166 — 133 — 100 MHz
tKC
(3)
Cycle Time 6 — 7.5 — 10 — ns
tKH Clock High Time 2.4 — 2.8 — 3 — ns
tKL
(3)
Clock Low Time 2.4 — 2.8 — 3 — ns
tKQ
(3)
Clock Access Time — 3.5 — 4 — 5 ns
tKQX
(1)
Clock High to Output Invalid 3 — 3 — 3 — n s
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ
(1,2)
Clock High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5 n s
tOEQ
(3)
Output Enable to Output Valid — 3.5 — 3. 8 — 5 n s
tOEQX
(1)
Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ
(1,2)
Output Disable to Output High-Z 2 3.5 2 3.8 2 5 n s
tAS
(3)
Address Setup Time 1.5 — 1.5 — 2 — ns
tSS
(3)
Address Status Setup Time 1.5 — 1.5 — 2 — ns
tWS
(3)
Write Setup Time 1. 5 — 1. 5 — 2 — ns
tCES
(3)
Chip Enable Setup Time 1.5 — 1.5 — 2 — ns
tAVS
(3)
Address Advance Setup Time 1.5 — 1.5 — 2 — n s
tAH
(3)
Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH
(3)
Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH
(3)
Write Hold Time 0.5 — 0.5 — 0. 5 — ns
tCEH
(3)
Chip Enable Hold Time 0.5 — 0.5 — 0. 5 — ns
tAVH
(3)
Address Advance Hold Time 0.5 — 0.5 — 0.5 — n s
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IS61SP12832
IS61SP12836 ISSI
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/11/04
READ/WRITE CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A16-A0
ADV
ADSC
ADSP
CLK
RD1 RD2
1a 2c 2d 3a
Unselected
Burst Read
tKQX
tKC
tKLtKH
tSS tSH
tSS tSH
tAS tAH
tWS tWH
tWS tWH
RD3
tCES tCEH
tCES tCEH
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
tOEQ
tOEQX
tOELZ
tKQLZ
tKQ
tOEHZ
tKQHZ
ADSC initiate read
ADSP is blocked by CE inactive
tAVH
tAVS
Suspend Burst
Pipelined Read
2a 2b
IS61SP12832
IS61SP12836 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. B
02/11/04
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC
(1)
Cycle Time 6 — 7.5 — 10 — ns
tKH
(1)
Clock High Time 2.4 — 2.8 — 4 — n s
tKL
(1)
Clock Low Time 2.4 — 2.8 — 4 — n s
tAS
(1)
Address Setup Time 1.5 — 1.5 — 2 — ns
tSS
(1)
Address Status Setup Time 1.5 — 1.5 — 2 — n s
tWS
(1)
Write Setup Time 1.5 — 1. 5 — 2 — ns
tDS
(1)
Data In Setup Time 1.5 — 1 .5 — 2 — ns
tCES
(1)
Chip Enable Setup Time 1.5 — 1. 5 — 2 — ns
tAVS
(1)
Address Advance Setup Time 1.5 — 1.5 — 2 — ns
tAH
(1)
Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH
(1)
Address Status Hold Time 0.5 — 0.5 — 0.5 — n s
tDH
(1)
Data In Hold Time 0.5 — 0. 5 — 0.5 — ns
tWH
(1)
Write Hold Time 0.5 — 0. 5 — 0.5 — ns
tCEH
(1)
Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH
(1)
Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
Note:
1. Tested with load in Figure 1.
IS61SP12832
IS61SP12836 ISSI
®
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/11/04
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A16-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z 1a 3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IS61SP12832
IS61SP12836 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. B
02/11/04
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC
(3)
Cycle Time 6 — 7.5 — 10 — ns
tKH
(3)
Clock High Time 2.4 — 2.8 — 4 — n s
tKL
(3)
Clock Low Time 2.4 — 2.8 — 4 — n s
tKQ
(3)
Clock Access Time — 3.5 — 4 — 5 ns
tKQX
(1)
Clock High to Output Invalid 1.5 — 1.5 — 2.5 — n s
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — n s
tKQHZ
(1,2)
Clock High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5 ns
tOEQ
(3)
Output Enable to Output Valid — 3. 5 — 3. 9 — 5 ns
tOEQX
(1)
Output Disable to Output Invalid 0 — 0 — 0 — n s
tOELZ
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — n s
tOEHZ
(1,2)
Output Disable to Output High-Z 2 3.5 2 3.8 2 5 n s
tAS
(3)
Address Setup Time 1.5 — 1.5 — 2 — ns
tSS
(3)
Address Status Setup Time 1.5 — 1.5 — 2 — n s
tCES
(3)
Chip Enable Setup Time 1.5 — 1. 5 — 2 — ns
tAH
(3)
Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH
(3)
Address Status Hold Time 0.5 — 0.5 — 0.5 — n s
tCEH
(3)
Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby 2 — 2 — 2 — cyc
tZZREC ZZ Recovery 2 — 2 — 2 — cyc
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IS61SP12832
IS61SP12836 ISSI
®
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/11/04
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATAOUT
DATAIN
ZZ
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A16-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
tKC
tKLtKH
tSS tSH
tAS tAH
RD2
tCES tCEH
tCES tCEH
tCES tCEH
tOEQ
tOEQX
tOELZ
tKQLZ
tKQ
tOEHZ
tKQX
tKQHZ
tZZS tZZREC
IS61SP12832
IS61SP12836 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. B
02/11/04
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61SP12836-166TQ TQFP
IS61SP12836-166B PBGA
133 MHz IS61SP12836-133TQ TQFP
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
166 MHz IS61SP12836-166TQI TQFP
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
133 MHz IS61SP12832-133TQ TQFP
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
166 MHz IS61SP12832-166TQI TQFP
5 ns IS61SP12832-5TQI TQFP
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
02/12/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic Ball Grid Array
Package Code: B (119-pin)
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusion and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
MILLIMETERS INCHES
Sym. Min. Max. Min. Max.
N0.
Leads 119
A — 2.41 — 0.095
A1 0.50 0.70 0.020 0.028
A2 0.80 1.00 0.032 0.039
A3 1.30 1.70 0.051 0.067
A4 0.56 BSC 0.022 BSC
b 0.60 0.90 0.024 0.035
D 21.80 22.20 0.858 0.874
D1 20.32 BSC 0.800 BSC
D2 19.40 19.60 0.764 0.772
E 13.80 14.20 0.543 0.559
E1 7.62 BSC 0.300 BSC
E2 11.90 12.10 0.469 0.476
e 1.27 BSC 0.050 BSC
E1
A1
D1
7654321
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
E2
E
A2
SEATING PLANE
e
D2D
A
30ϒ
A3
A4
φ
b (119X)
Integrated Silicon Solution, Inc. — 1-800-379-4774
PACKAGING INFORMATION ISSI
®
PK13197LQ Rev. D 05/08/03
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
Thin Quad Flat Pack (TQ)
Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 100 128
A — 1.60 — 0.063 — 1.60 — 0.063
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057
b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011
D 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874
D1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791
E 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638
E1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555
e 0.65 BSC 0.026 BSC 0.50 BSC 0.020 BSC
L 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030
L1 1.00 REF. 0.039 REF. 1.00 REF. 0.039 REF.
C0
o
7
o
0
o
7
o
0
o
7
o
0
o
7
o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.
D
D1
EE1
1
N
A2 A
A1
e
b
SEATING
PLANE
CL1
L
