Freescale Semiconductor Data Sheet: Technical Data K40 Sub-Family Data Sheet Document Number: K40P100M100SF2 Rev. 7, 02/2013 K40P100M100SF2 Supports the following: MK40DN512ZVLL10 Features * Operating Characteristics - Voltage range: 1.71 to 3.6 V - Flash write voltage range: 1.71 to 3.6 V - Temperature range (ambient): -40 to 105C * Performance - Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz * Memories and memory interfaces - Up to 512 KB program flash memory on nonFlexMemory devices - Up to 128 KB RAM - Serial programming interface (EzPort) * Clocks - 3 to 32 MHz crystal oscillator - 32 kHz crystal oscillator - Multi-purpose clock generator * System peripherals - Multiple low-power modes to provide power optimization based on application requirements - Memory protection unit with multi-master protection - 16-channel DMA controller, supporting up to 63 request sources - External watchdog monitor - Software watchdog - Low-leakage wakeup unit * Security and integrity modules - Hardware CRC module to support fast cyclic redundancy checks - 128-bit unique identification (ID) number per chip * Human-machine interface - Segment LCD controller supporting up to 40 frontplanes and 8 backplanes, or 44 frontplanes and 4 backplanes, depending on the package size - Low-power hardware touch sensor interface (TSI) - General-purpose input/output * Analog modules - Two 16-bit SAR ADCs - Programmable gain amplifier (PGA) (up to x64) integrated into each ADC - 12-bit DAC - Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input - Voltage reference * Timers - Programmable delay block - Eight-channel motor control/general purpose/PWM timer - Two 2-channel quadrature decoder/general purpose timers - Periodic interrupt timers - 16-bit low-power timer - Carrier modulator transmitter - Real-time clock * Communication interfaces - USB full-/low-speed On-the-Go controller with onchip transceiver - Two Controller Area Network (CAN) modules - Three SPI modules - Two I2C modules - Five UART modules - Secure Digital host controller (SDHC) - I2S module Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) 2011-2013 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................4 6 Peripheral operating requirements and behaviors....................23 1.1 Determining valid orderable parts......................................4 6.1 Core modules....................................................................23 2 Part identification......................................................................4 6.1.1 Debug trace timing specifications.......................23 2.1 Description.........................................................................4 6.1.2 JTAG electricals..................................................23 2.2 Format...............................................................................4 6.2 System modules................................................................26 2.3 Fields.................................................................................4 6.3 Clock modules...................................................................26 2.4 Example............................................................................5 6.3.1 MCG specifications.............................................26 3 Terminology and guidelines......................................................5 6.3.2 Oscillator electrical specifications.......................28 3.1 Definition: Operating requirement......................................5 6.3.3 32 kHz Oscillator Electrical Characteristics........31 3.2 Definition: Operating behavior...........................................6 6.4 Memories and memory interfaces.....................................31 3.3 Definition: Attribute............................................................6 6.4.1 Flash electrical specifications.............................31 3.4 Definition: Rating...............................................................7 6.4.2 EzPort Switching Specifications.........................33 3.5 Result of exceeding a rating..............................................7 6.5 Security and integrity modules..........................................34 3.6 Relationship between ratings and operating 6.6 Analog...............................................................................34 requirements......................................................................7 6.6.1 ADC electrical specifications..............................34 3.7 Guidelines for ratings and operating requirements............8 6.6.2 CMP and 6-bit DAC electrical specifications......42 3.8 Definition: Typical value.....................................................8 6.6.3 12-bit DAC electrical characteristics...................44 3.9 Typical value conditions....................................................9 6.6.4 Voltage reference electrical specifications..........47 4 Ratings......................................................................................10 6.7 Timers................................................................................48 4.1 Thermal handling ratings...................................................10 6.8 Communication interfaces.................................................48 4.2 Moisture handling ratings..................................................10 6.8.1 USB electrical specifications...............................48 4.3 ESD handling ratings.........................................................10 6.8.2 USB DCD electrical specifications......................49 4.4 Voltage and current operating ratings...............................10 6.8.3 USB VREG electrical specifications...................49 5 General.....................................................................................11 6.8.4 CAN switching specifications..............................50 5.1 AC electrical characteristics..............................................11 6.8.5 DSPI switching specifications (limited voltage 5.2 Nonswitching electrical specifications...............................11 range).................................................................50 5.2.1 Voltage and current operating requirements......12 6.8.6 DSPI switching specifications (full voltage 5.2.2 LVD and POR operating requirements...............13 5.2.3 Voltage and current operating behaviors............13 6.8.7 Inter-Integrated Circuit Interface (I2C) timing..... 53 5.2.4 Power mode transition operating behaviors.......15 6.8.8 UART switching specifications............................54 5.2.5 Power consumption operating behaviors............16 6.8.9 SDHC specifications...........................................54 5.2.6 EMC radiated emissions operating behaviors....19 6.8.10 I2S switching specifications................................55 5.2.7 Designing with radiated emissions in mind.........20 5.2.8 Capacitance attributes........................................20 6.9.1 TSI electrical specifications................................58 5.3 Switching specifications.....................................................20 6.9.2 LCD electrical characteristics.............................59 range).................................................................51 6.9 Human-machine interfaces (HMI)......................................58 5.3.1 Device clock specifications.................................20 7 Dimensions...............................................................................60 5.3.2 General switching specifications.........................20 7.1 Obtaining package dimensions.........................................60 5.4 Thermal specifications.......................................................21 8 Pinout........................................................................................60 5.4.1 Thermal operating requirements.........................21 8.1 K40 Signal Multiplexing and Pin Assignments..................60 5.4.2 Thermal attributes...............................................22 8.2 K40 Pinouts.......................................................................64 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 2 Freescale Semiconductor, Inc. 9 Revision History........................................................................65 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 3 Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK40 and MK40 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status * M = Fully qualified, general market flow * P = Prequalification K## Kinetis family * K40 A Key attribute * D = Cortex-M4 w/ DSP * F = Cortex-M4 w/ DSP and FPU M Flash memory type * N = Program flash only * X = Program flash and FlexMemory Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 4 Freescale Semiconductor, Inc. Terminology and guidelines Field Description Values FFF Program flash memory size * * * * * * * 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB 2M0 = 2 MB R Silicon revision * Z = Initial * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 * C = -40 to 85 PP Package identifier * * * * * * * * * * * FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (12 mm x 12 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) * * * * * 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz N Packaging type * R = Tape and reel * (Blank) = Trays 2.4 Example This is an example part number: MK40DN512ZVMD10 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 5 Terminology and guidelines 3.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. Unit 1.1 V 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. Unit 130 A 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. -- Max. Unit 7 pF K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. -0.3 Max. 1.2 Unit V 3.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 7 Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .) r Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) g lin nd Ha in rat n.) mi g( nd Ha g lin ing rat ax (m .) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 8 Freescale Semiconductor, Inc. Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit A 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (A) 3500 150 C 3000 105 C 2500 25 C 2000 -40 C 1500 1000 500 0 0.95 0.90 1.00 1.05 1.10 VDD (V) 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 C VDD 3.3 V supply voltage 3.3 V K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 9 Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 Solder temperature, leaded -- 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.4 Voltage and current operating ratings K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 10 Freescale Semiconductor, Inc. General Symbol Description Min. Max. Unit VDD Digital supply voltage -0.3 3.8 V IDD Digital supply current -- 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) -0.3 5.5 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage -0.3 VDD + 0.3 V Maximum current single pin limit (applies to all digital pins) -25 25 mA ID VDDA Analog supply voltage VDD - 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage -0.3 3.63 V VUSB_DM USB_DM input voltage -0.3 3.63 V VREGIN USB regulator input -0.3 6.0 V RTC battery supply voltage -0.3 3.8 V VBAT 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins * have CL=30pF loads, * are configured for fast slew rate (PORTx_PCRn[SRE]=0), and * are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins * have their passive filter disabled (PORTx_PCRn[PFE]=0) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 11 General 5.2 Nonswitching electrical specifications 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V 1.71 3.6 V * 2.7 V VDD 3.6 V 0.7 x VDD -- V * 1.7 V VDD 2.7 V 0.75 x VDD -- V * 2.7 V VDD 3.6 V -- 0.35 x VDD V * 1.7 V VDD 2.7 V -- 0.3 x VDD V 0.06 x VDD -- V -5 -- mA VBAT VIH VIL RTC battery supply voltage Input high voltage Input low voltage VHYS Input hysteresis IICDIO Digital pin negative DC injection current -- single pin * VIN < VSS-0.3V IICAIO IICcont 1 Analog2, EXTAL, and XTAL pin DC injection current -- single pin 3 mA * VIN < VSS-0.3V (Negative current injection) -5 -- * VIN > VDD+0.3V (Positive current injection) -- +5 -25 -- -- +25 Contiguous pin DC injection current --regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins * Negative current injection * Positive current injection mA VODPU Open drain pullup voltage level VDD VDD V VRAM VDD voltage required to retain RAM 1.2 -- V VPOR_VBAT -- V VRFVBAT Notes VBAT voltage required to retain the VBAT register file 4 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 12 Freescale Semiconductor, Inc. General 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold -- high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds -- high range 1 VLVW1H * Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H * Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV=11) 2.92 3.00 3.08 V -- 80 -- mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range 1 VLVW1L * Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L * Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L * Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L * Level 4 falling (LVWV=11) 2.04 2.10 2.16 V -- 60 -- mV VHYSL Low-voltage inhibit reset/recover hysteresis -- low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 13 General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Min. Typ.1 Max. Unit * 2.7 V VDD 3.6 V, IOH = -9mA VDD - 0.5 -- -- V * 1.71 V VDD 2.7 V, IOH = -3mA VDD - 0.5 -- -- V * 2.7 V VDD 3.6 V, IOH = -2mA VDD - 0.5 -- -- V * 1.71 V VDD 2.7 V, IOH = -0.6mA VDD - 0.5 -- -- V -- -- 100 mA Description Notes Output high voltage -- high drive strength Output high voltage -- low drive strength IOHT Output high current total for all ports VOL Output low voltage -- high drive strength 2 * 2.7 V VDD 3.6 V, IOL = 9mA -- -- 0.5 V * 1.71 V VDD 2.7 V, IOL = 3mA -- -- 0.5 V * 2.7 V VDD 3.6 V, IOL = 2mA -- -- 0.5 V * 1.71 V VDD 2.7 V, IOL = 0.6mA -- -- 0.5 V -- -- 100 mA Output low voltage -- low drive strength IOLT Output low current total for all ports IINA Input leakage current, analog pins and digital pins configured as analog inputs 3, 4 * VSS VIN VDD * All pins except EXTAL32, XTAL32, EXTAL, XTAL * EXTAL (PTA18) and XTAL (PTA19) * EXTAL32, XTAL32 IIND -- 0.002 0.5 A -- 0.004 1.5 A -- 0.075 10 A Input leakage current, digital pins 4, 5 * VSS VIN VIL * All digital pins -- 0.002 0.5 A -- 0.002 0.5 A -- 0.004 1 A * VIN = VDD * All digital pins except PTD7 * PTD7 IIND Input leakage current, digital pins 4, 5, 6 * VIL < VIN < VDD * VDD = 3.6 V -- 18 26 A * VDD = 3.0 V -- 12 49 A * VDD = 2.5 V -- 8 13 A * VDD = 1.7 V -- 3 6 A Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 14 Freescale Semiconductor, Inc. General Table 4. Voltage and current operating behaviors (continued) Symbol IIND Description Min. Max. Unit Input leakage current, digital pins * VDD < VIN < 5.5 V ZIND Typ.1 Notes 4, 5 -- 1 50 A Input impedance examples, digital pins 4, 7 * VDD = 3.6 V -- -- 48 k * VDD = 3.0 V -- -- 55 k * VDD = 2.5 V -- -- 57 k * VDD = 1.7 V -- -- 85 k RPU Internal pullup resistors 20 35 50 k 8 RPD Internal pulldown resistors 20 35 50 k 9 1. 2. 3. 4. 5. 6. 7. Typical values characterized at 25C and VDD = 3.6 V unless otherwise noted. Open drain outputs must be pulled to VDD. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. Internal pull-up/pull-down resistors disabled. Characterized, not tested in production. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. 8. Measured at VDD supply voltage = VDD min and Vinput = VSS 9. Measured at VDD supply voltage = VDD min and Vinput = VDD I IND Digital input Source + - Z IND 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSxRUN recovery times in the following table assume this clock configuration: * * * * CPU and system clocks = 100 MHz Bus clock = 50 MHz Flash clock = 25 MHz MCG mode: FEI K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 15 General Table 5. Power mode transition operating behaviors Symbol tPOR Description Min. Max. After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. * VDD slew rate 5.7 kV/s * VDD slew rate < 5.7 kV/s * VLLS1 RUN * VLLS2 RUN * VLLS3 RUN * LLS RUN * VLPS RUN * STOP RUN Unit Notes s 1 -- 300 -- 1.7 V / (VDD slew rate) -- 134 s -- 96 s -- 96 s -- 6.2 s -- 5.9 s -- 5.9 s 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Typ. Max. Unit Notes -- -- See note mA 1 Run mode current -- all peripheral clocks disabled, code executing from flash * @ 1.8V * @ 3.0V IDD_RUN Min. 2 -- 45 70 mA -- 47 72 mA Run mode current -- all peripheral clocks enabled, code executing from flash * @ 1.8V 3, 4 -- 61 85 mA -- 63 71 mA -- 72 87 mA * @ 3.0V * @ 25C * @ 125C IDD_WAIT Wait mode high frequency current at 3.0 V -- all peripheral clocks disabled -- 35 -- mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V -- all peripheral clocks disabled -- 15 -- mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled -- N/A -- mA 6 Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 16 Freescale Semiconductor, Inc. General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled -- N/A -- mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V -- all peripheral clocks disabled -- N/A -- mA 8 IDD_STOP Stop mode current at 3.0 V * @ -40 to 25C -- 0.59 1.4 mA * @ 70C -- 2.26 7.9 mA * @ 105C -- 5.94 19.2 mA * @ -40 to 25C -- 93 435 A * @ 70C -- 520 2000 A * @ 105C -- 1350 4000 A IDD_VLPS IDD_LLS IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VBAT Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V 9 * @ -40 to 25C -- 4.8 20 A * @ 70C -- 28 68 A * @ 105C -- 126 270 A Very low-leakage stop mode 3 current at 3.0 V 9 * @ -40 to 25C -- 3.1 8.9 A * @ 70C -- 17 35 A * @ 105C -- 82 148 A * @ -40 to 25C -- 2.2 5.4 A * @ 70C -- 7.1 12.5 A * @ 105C -- 41 125 A * @ -40 to 25C -- 2.1 7.6 A * @ 70C -- 6.2 13.5 A * @ 105C -- 30 46 A -- 0.33 0.39 A -- 0.60 0.78 A -- 1.97 2.9 A Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current with RTC and 32kHz disabled at 3.0 V * @ -40 to 25C * @ 70C * @ 105C Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 17 General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. IDD_VBAT Average current when CPU is not accessing RTC registers Typ. Max. Unit Notes 10 * @ 1.8V * @ -40 to 25C * @ 70C * @ 105C -- 0.71 0.81 A -- 1.01 1.3 A -- 2.82 4.3 A -- 0.84 0.94 A -- 1.17 1.5 A -- 3.16 4.6 A * @ 3.0V * @ -40 to 25C * @ 70C * @ 105C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode. 6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. 10. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. * USB regulator disabled * No GPIOs toggled * Code execution from flash with cache enabled * For the ALLOFF curve, all peripheral clocks are disabled except FTFL K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 18 Freescale Semiconductor, Inc. General Figure 2. Run mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors as measured on 144LQFP and 144MAPBGA packages Symbol Description Frequency band (MHz) 144LQFP 144MAPBGA Unit Notes 1,2 VRE1 Radiated emissions voltage, band 1 0.15-50 23 12 dBV VRE2 Radiated emissions voltage, band 2 50-150 27 24 dBV VRE3 Radiated emissions voltage, band 3 150-500 28 27 dBV VRE4 Radiated emissions voltage, band 4 500-1000 14 11 dBV IEC level 0.15-1000 K K -- VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 19 General 2. VDD = 3.3 V, TA = 25 C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for "EMC design." 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins -- 7 pF CIN_D Input capacitance: digital pins -- 7 pF 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit System and core clock -- 100 MHz System and core clock when Full Speed USB in operation 20 -- MHz Bus clock -- 50 MHz fFLASH Flash clock -- 25 MHz fLPTMR LPTMR clock -- 25 MHz Notes Normal run mode fSYS fSYS_USB fBUS 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, and I2C signals. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 20 Freescale Semiconductor, Inc. General Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) -- Asynchronous path 100 -- ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) -- Asynchronous path 16 -- ns 3 External reset pulse width (digital glitch filter disabled) 100 -- ns 3 2 -- Bus clock cycles Mode select (EZP_CS) hold time after reset deassertion Port rise and fall time (high drive strength) 4 * Slew disabled * 1.71 VDD 2.7V -- 12 ns * 2.7 VDD 3.6V -- 6 ns * 1.71 VDD 2.7V -- 36 ns * 2.7 VDD 3.6V -- 24 ns * Slew enabled Port rise and fall time (low drive strength) 5 * Slew disabled * 1.71 VDD 2.7V -- 12 ns * 2.7 VDD 3.6V -- 6 ns * 1.71 VDD 2.7V -- 36 ns * 2.7 VDD 3.6V -- 24 ns * Slew enabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 5.4 Thermal specifications K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 21 General 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C 5.4.2 Thermal attributes Board type Symbol Description Unit Notes Single-layer (1s) RJA Thermal 47 resistance, junction to ambient (natural convection) C/W 1 Four-layer (2s2p) RJA Thermal 35 resistance, junction to ambient (natural convection) C/W 1 Single-layer (1s) RJMA Thermal 37 resistance, junction to ambient (200 ft./ min. air speed) C/W 1 Four-layer (2s2p) RJMA Thermal 29 resistance, junction to ambient (200 ft./ min. air speed) C/W 1 -- RJB Thermal 20 resistance, junction to board C/W 2 -- RJC Thermal 9 resistance, junction to case C/W 3 -- JT Thermal 2 characterization parameter, junction to package top outside center (natural convection) C/W 4 1. 2. 3. 4. 100 LQFP Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air). Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 22 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max. Unit Tcyc Clock period Frequency dependent MHz Twl Low pulse width 2 -- ns Twh High pulse width 2 -- ns Tr Clock and data rise time -- 3 ns Tf Clock and data fall time -- 3 ns Ts Data setup 3 -- ns Th Data hold 2 -- ns Figure 3. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 4. Trace data specifications K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 25 * Serial Wire Debug 0 50 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 20 -- ns * Serial Wire Debug 10 -- ns J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 0 -- ns J7 TCLK low to boundary scan output data valid -- 25 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1 -- ns J11 TCLK low to TDO data valid -- 17 ns J12 TCLK low to TDO high-Z -- 17 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns J2 TCLK cycle period J3 TCLK clock pulse width Table 14. JTAG full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V TCLK frequency of operation * Boundary Scan 0 10 * JTAG and CJTAG 0 20 * Serial Wire Debug 0 40 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 25 -- ns * Serial Wire Debug 12.5 -- ns -- 3 ns J2 TCLK cycle period J3 TCLK clock pulse width J4 MHz TCLK rise and fall times Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 0 -- ns J7 TCLK low to boundary scan output data valid -- 25 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1.4 -- ns J11 TCLK low to TDO data valid -- 22.1 ns J12 TCLK low to TDO high-Z J13 TRST assert time J14 TRST setup time (negation) to TCLK high -- 22.1 ns 100 -- ns 8 -- ns J2 J3 J3 TCLK (input) J4 J4 Figure 5. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 6. Boundary scan (JTAG) timing K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 7. Test Access Port timing TCLK J14 J13 TRST Figure 8. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit -- 32.768 -- kHz 31.25 -- 38.2 kHz -- 0.3 0.6 %fdco 1 Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C -- 1.5 4.5 %fdco 1 fintf_ft Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C -- 4 -- MHz fintf_t Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C fints_t Internal reference frequency (slow clock) -- user trimmed -- over fixed voltage and temperature range of 0-70C fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM fdco_t floc_low Loss of external clock minimum frequency -- RANGE = 00 (3/5) x fints_t -- -- kHz floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t -- -- kHz 31.25 -- 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz -- 23.99 -- MHz -- 47.97 -- MHz -- 71.99 -- MHz -- 95.98 -- MHz -- 180 -- -- 150 -- -- -- 1 Notes FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 2, 3 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref fdco_t_DMX32 DCO output frequency Low range (DRS=00) 4, 5 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll FLL period jitter * fVCO = 48 MHz * fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time ps ms 6 Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit 48.0 -- 100 MHz -- 1060 -- A -- 600 -- A 2.0 -- 4.0 MHz Notes PLL fvco VCO operating frequency Ipll PLL operating current * PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) Ipll PLL operating current * PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) Jacc_pll 7 7 8 * fvco = 48 MHz -- 120 -- ps * fvco = 100 MHz -- 50 -- ps PLL accumulated jitter over 1s (RMS) 8 * fvco = 48 MHz -- 1350 -- ps * fvco = 100 MHz -- 600 -- ps 2.98 % Dlock Lock entry frequency tolerance 1.49 -- Dunl Lock exit frequency tolerance 4.47 -- 5.97 % tpll_lock Lock detector detection time -- -- 150 x 10-6 + 1075(1/ fpll_ref) s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC IDDOSC Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 500 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Supply current -- high gain mode (HGO=1) 1 * 32 kHz -- 25 -- A * 4 MHz -- 400 -- A * 8 MHz (RANGE=01) -- 500 -- A * 16 MHz -- 2.5 -- mA * 24 MHz -- 3 -- mA * 32 MHz -- 4 -- mA Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol Vpp5 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V Notes VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Symbol Oscillator frequency specifications Table 17. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency -- low frequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- high frequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- 750 -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- 250 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 18. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 -- 3.6 V Internal feedback resistor -- 100 -- M Cpara Parasitical capacitance of EXTAL32 and XTAL32 -- 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation -- 0.6 -- V RF 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 Symbol fosc_lo tstart fec_extal32 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal -- 32.768 -- kHz Crystal start-up time -- 1000 -- ms 1 Externally provided input clock frequency -- 32.768 -- kHz 2 700 -- VBAT mV 2, 3 vec_extal32 Externally provided input clock amplitude Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 6.4 Memories and memory interfaces K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors 6.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 thversscr Longword Program high-voltage time -- 7.5 18 s Sector Erase high-voltage time -- 13 113 ms 1 -- 416 3616 ms 1 Notes thversblk256k Erase Block high-voltage time for 256 KB Notes 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Symbol Flash timing specifications -- commands Table 21. Flash command timing specifications Description Min. Typ. Max. Unit -- -- 1.7 ms Read 1s Block execution time trd1blk256k * 256 KB program/data flash trd1sec2k Read 1s Section execution time (flash sector) -- -- 60 s 1 tpgmchk Program Check execution time -- -- 45 s 1 trdrsrc Read Resource execution time -- -- 30 s 1 tpgm4 Program Longword execution time -- 65 145 s Erase Flash Block execution time tersblk256k tersscr * 256 KB program/data flash Erase Flash Sector execution time 2 -- 435 3700 ms -- 14 114 ms 2 Program Section execution time tpgmsec512 * 512 bytes flash -- 2.4 -- ms tpgmsec1k * 1 KB flash -- 4.7 -- ms tpgmsec2k * 2 KB flash -- 9.3 -- ms trd1all Read 1s All Blocks execution time -- -- 1.8 ms trdonce Read Once execution time -- -- 25 s Program Once execution time -- 65 -- s tersall Erase All Blocks execution time -- 870 7400 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 tpgmonce 1 Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Swap Control execution time tswapx01 * control code 0x01 -- 200 -- s tswapx02 * control code 0x02 -- 70 150 s tswapx04 * control code 0x04 -- 70 150 s tswapx08 * control code 0x08 -- -- 30 s 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation -- 2.5 6.0 mA Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Reliability specifications Table 23. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years nnvmcycp Cycling endurance 10 K 50 K -- cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40C Tj 125C. 6.4.2 EzPort Switching Specifications Table 24. EzPort switching specifications Num EP1 Description Min. Max. Unit Operating voltage 1.71 3.6 V -- fSYS/2 MHz EZP_CK frequency of operation (all commands except READ) Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors Table 24. EzPort switching specifications (continued) Num Description Min. Max. Unit EP1a EZP_CK frequency of operation (READ command) -- fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK -- ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 -- ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 -- ns EP5 EZP_D input valid to EZP_CK high (setup) 2 -- ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 -- ns EP7 EZP_CK low to EZP_Q output valid -- 16 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 -- ns EP9 EZP_CS negation to EZP_Q tri-state -- 12 ns EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 9. EzPort Timing Diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DM3. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 27 and Table 28. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 25. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage * 16-bit differential mode VREFL -- 31/32 * VREFH V * All other modes VREFL -- * 16-bit mode -- 8 10 * 8-bit / 10-bit / 12-bit modes -- 4 5 -- 2 5 CADIN RADIN RAS Input capacitance Input resistance Notes VREFH pF k Analog source resistance 13-bit / 12-bit modes fADCK < 4 MHz -- -- 5 k fADCK ADC conversion clock frequency 13-bit mode 1.0 -- 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 -- 12.0 MHz 4 Crate ADC conversion rate 13-bit modes No ADC hardware averaging 3 5 20.000 -- 818.330 Ksps Continuous conversions enabled, subsequent conversion time Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors Table 25. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16-bit mode Min. Typ.1 Max. Unit Notes 5 No ADC hardware averaging 37.037 -- 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection Z AS R AS ADC SAR ENGINE R ADIN V ADIN C AS V AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 10. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current Conditions1 Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Conditions1 Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Min. Typ.2 Max. Unit Notes * ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz * ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK * ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz * ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 Differential nonlinearity * 12-bit modes -- 0.7 -1.1 to +1.9 -0.3 to 0.5 Integral nonlinearity * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 -2.7 to +1.9 -0.7 to +0.5 Full-scale error * <12-bit modes -- 0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 5 EQ ENOB Quantization error * 16-bit modes -- -1 to 0 -- * 13-bit modes -- -- 0.5 Effective number 16-bit differential mode of bits * Avg = 32 * Avg = 4 LSB4 6 12.8 14.5 -- bits 11.9 13.8 -- bits 12.2 13.9 -- bits 11.4 13.1 -- bits 16-bit single-ended mode * Avg = 32 * Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode 6.02 x ENOB + 1.76 * Avg = 32 16-bit single-ended mode * Avg = 32 SFDR Spurious free dynamic range dB 7 -- -94 -- dB -- -85 -- dB 16-bit differential mode * Avg = 32 16-bit single-ended mode * Avg = 32 7 82 95 -- dB 78 90 -- dB Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EIL Input leakage error Conditions1 Min. Typ.2 Max. IIn x RAS Unit Notes mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/C Temp sensor voltage 25 C 706 716 726 mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Figure 11. Typical ENOB vs. ADC_CLK for 16-bit differential mode K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 38 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 12. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 27. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VREFPGA PGA ref voltage VADIN VCM RPGAD VREF_OU VREF_OU VREF_OU T T T V Notes 2, 3 Input voltage VSSA -- VDDA V Input Common Mode range VSSA -- VDDA V Gain = 1, 2, 4, 8 -- 128 -- k IN+ to IN-4 Gain = 16, 32 -- 64 -- Gain = 64 -- 32 -- Differential input impedance RAS Analog source resistance -- 100 -- 5 TS ADC sampling time 1.25 -- -- s 6 Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 39 Peripheral operating requirements and behaviors Table 27. 16-bit ADC with PGA operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 13 bit modes Min. Typ.1 Max. Unit Notes 18.484 -- 450 Ksps 7 37.037 -- 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREF_OUT) 3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other than the output of the VREF module, the VREF module must be disabled. 4. For single ended configurations the input impedance of the driven input is RPGAD/2 5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at 8 MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 6.6.1.4 16-bit ADC with PGA characteristics Table 28. 16-bit ADC with PGA characteristics Symbol Description Conditions IDDA_PGA Supply current Low power (ADC_PGA[PGALPb]=0) IDC_PGA Input DC current Min. Typ.1 Max. Unit Notes -- 420 644 A 2 A 3 Gain =1, VREFPGA=1.2V, VCM=0.5V -- 1.54 -- A Gain =64, VREFPGA=1.2V, VCM=0.1V -- 0.57 -- A Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 40 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 28. 16-bit ADC with PGA characteristics (continued) Symbol G BW Description Gain4 Input signal bandwidth PSRR Power supply rejection ratio CMRR Common mode rejection ratio Min. Typ.1 Max. * PGAG=0 0.95 1 1.05 * PGAG=1 1.9 2 2.1 * PGAG=2 3.8 4 4.2 * PGAG=3 7.6 8 8.4 * PGAG=4 15.2 16 16.6 * PGAG=5 30.0 31.6 33.2 * PGAG=6 58.8 63.3 67.8 -- -- 4 kHz -- -- 40 kHz -- -84 -- dB VDDA= 3V 100mV, fVDDA= 50Hz, 60Hz * Gain=1 -- -84 -- dB * Gain=64 -- -85 -- dB VCM= 500mVpp, fVCM= 50Hz, 100Hz Conditions * 16-bit modes * < 16-bit modes Gain=1 Unit Notes RAS < 100 VOFS Input offset voltage -- 0.2 -- mV Output offset = VOFS*(Gain+1) TGSW Gain switching settling time -- -- 10 s 5 EIL Input leakage error mV IIn = leakage current All modes IIn x RAS (refer to the MCU's voltage and current operating ratings) VPP,DIFF SNR THD SFDR Maximum differential input signal swing V 6 16-bit differential mode, Average=32 where VX = VREFPGA x 0.583 Signal-to-noise ratio * Gain=1 80 90 -- dB * Gain=64 52 66 -- dB Total harmonic distortion * Gain=1 85 100 -- dB * Gain=64 49 95 -- dB Spurious free dynamic range * Gain=1 85 105 -- dB * Gain=64 53 88 -- dB 16-bit differential mode, Average=32, fin=100Hz 16-bit differential mode, Average=32, fin=100Hz Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 41 Peripheral operating requirements and behaviors Table 28. 16-bit ADC with PGA characteristics (continued) Symbol Description ENOB Effective number of bits SINAD Signal-to-noise plus distortion ratio Min. Typ.1 Max. Unit Notes * Gain=1, Average=4 11.6 13.4 -- bits * Gain=64, Average=4 7.2 9.6 -- bits * Gain=1, Average=32 12.8 14.5 -- bits 16-bit differential mode,fin=100Hz * Gain=2, Average=32 11.0 14.3 -- bits * Gain=4, Average=32 7.9 13.8 -- bits * Gain=8, Average=32 7.3 13.1 -- bits * Gain=16, Average=32 6.8 12.5 -- bits * Gain=32, Average=32 6.8 11.5 -- bits * Gain=64, Average=32 7.5 10.6 -- bits Conditions See ENOB 6.02 x ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. 6.6.2 CMP and 6-bit DAC electrical specifications Table 29. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VH Analog comparator hysteresis1 VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDHS Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 42 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 29. Comparator and 6-bit DAC electrical specifications (continued) Symbol tDLS IDAC6b Description Min. Typ. Max. Unit Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 -- -- 40 s 6-bit DAC current adder (enabled) -- 7 -- A INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 0.06 HYSTCTR Setting CM P Hystereris (V) 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 43 Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 30. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage 1.13 3.6 V TA Temperature Operating temperature range of the device CL Output load capacitance -- 100 pF IL Output load current -- 1 mA Notes 1 C 2 1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 44 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 31. 12-bit DAC operating behaviors Description IDDA_DACL Supply current -- low-power mode Min. Typ. Max. Unit -- -- 150 A -- -- 700 A Notes P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode -- 100 200 s 1 tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode -- 15 30 s 1 -- 0.7 1 s 1 -- -- 100 mV tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and high-speed mode Vdacoutl DAC output voltage range low -- high-speed mode, no load, DAC set to 0x000 Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF VDACR -100 -- VDACR mV INL Integral non-linearity error -- high speed mode -- -- 8 LSB 2 DNL Differential non-linearity error -- VDACR > 2 V -- -- 1 LSB 3 DNL Differential non-linearity error -- VDACR = VREF_OUT -- -- 1 LSB 4 -- 0.4 0.8 %FSR 5 Gain error -- 0.1 0.6 %FSR 5 Power supply rejection ratio, VDDA 2.4 V 60 -- 90 dB TCO Temperature coefficient offset voltage -- 3.7 -- V/C TGE Temperature coefficient gain error -- 0.000421 -- %FSR/C Rop Output resistance load = 3 k -- -- 250 SR Slew rate -80h F7Fh 80h VOFFSET Offset error EG PSRR 1. 2. 3. 4. 5. 6. V/s * High power (SPHP) 1.2 1.7 -- * Low power (SPLP) 0.05 0.12 -- -- -- -80 CT Channel to channel cross talk BW 3dB bandwidth 6 dB kHz * High power (SPHP) 550 -- -- * Low power (SPLP) 40 -- -- Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 45 Peripheral operating requirements and behaviors Figure 15. Typical INL error vs. digital code K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 46 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 16. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 32. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 47 Peripheral operating requirements and behaviors Table 33. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V Vout Voltage reference output -- factory trim 1.1584 -- 1.2376 V Vstep Voltage reference trim step -- 0.5 -- mV Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) -- -- 80 mV Ibg Bandgap only current -- -- 80 A 1 Ilp Low-power buffer current -- -- 360 uA 1 Ihp High-power buffer current -- -- 1 mA 1 mV 1, 2 VLOAD Load regulation * current = + 1.0 mA -- 2 -- * current = - 1.0 mA -- 5 -- Tstup Buffer startup time -- -- 100 s Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) -- 2 -- mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 34. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 50 C Notes Table 35. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. Max. Unit 1.173 1.225 V Notes 6.7 Timers See General switching specifications. 6.8 Communication interfaces K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 48 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org. 6.8.2 USB DCD electrical specifications Table 36. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 A) 0.5 -- 0.7 V Threshold voltage for logic high 0.8 -- 2.0 V VLGC IDP_SRC USB_DP source current 7 10 13 A IDM_SINK USB_DM sink current 50 100 150 A RDM_DWN D- pulldown resistance for data pin contact detect 14.25 -- 24.8 k VDAT_REF Data detect voltage 0.25 0.33 0.4 V 6.8.3 USB VREG electrical specifications Table 37. USB VREG electrical specifications Symbol Description Min. VREGIN Typ.1 Max. Unit Input supply voltage 2.7 -- 5.5 V IDDon Quiescent current -- Run mode, load current equal zero, input supply (VREGIN) > 3.6 V -- 120 186 A IDDstby Quiescent current -- Standby mode, load current equal zero -- 1.27 30 A IDDoff Quiescent current -- Shutdown mode -- 650 -- nA -- -- 4 A * VREGIN = 5.0 V and temperature=25 C * Across operating voltage and temperature ILOADrun Maximum load current -- Run mode -- -- 120 mA ILOADstby Maximum load current -- Standby mode -- -- 1 mA VReg33out Regulator output voltage -- Input supply (VREGIN) > 3.6 V 3 3.3 3.6 V 2.1 2.8 3.6 V Regulator output voltage -- Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 -- 3.6 V COUT External output capacitor 1.76 2.2 8.16 F ESR External output capacitor equivalent series resistance 1 -- 100 m * Run mode * Standby mode VReg33out Notes 2 Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 49 Peripheral operating requirements and behaviors Table 37. USB VREG electrical specifications (continued) Symbol ILIM Description Short circuit current Min. Typ.1 Max. Unit -- 290 -- mA Notes 1. Typical values assume VREGIN = 5.0 V, Temp = 25 C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. 6.8.4 CAN switching specifications See General switching specifications. 6.8.5 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 38. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 25 MHz 2 x tBUS -- ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 2 -- ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 2 -- ns 2 DS5 DSPI_SCK to DSPI_SOUT valid -- 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -2 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 15 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 50 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS8 DS7 (CPOL=0) DSPI_SIN Data First data Last data DS5 DSPI_SOUT DS6 First data Data Last data Figure 17. DSPI classic SPI timing -- master mode Table 39. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 12.5 MHz 4 x tBUS -- ns (tSCK/2) - 2 (tSCK/2) + 2 ns Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 10 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 14 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Data Last data DS14 First data Data Last data Figure 18. DSPI classic SPI timing -- slave mode K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 51 Peripheral operating requirements and behaviors 6.8.6 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 40. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit Notes 1.71 3.6 V 1 -- 12.5 MHz 4 x tBUS -- ns DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 4 -- ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 4 -- ns 3 DS5 DSPI_SCK to DSPI_SOUT valid -- 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 20.5 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns DS1 DSPI_SCK output cycle time DS2 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS7 (CPOL=0) DSPI_SIN DS8 Data First data Last data DS5 DSPI_SOUT First data DS6 Data Last data Figure 19. DSPI classic SPI timing -- master mode Table 41. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V -- 6.25 MHz Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 52 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 41. Slave mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit 8 x tBUS -- ns (tSCK/2) - 4 (tSCK/2) + 4 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 19 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 20. DSPI classic SPI timing -- slave mode 6.8.7 Inter-Integrated Circuit Interface (I2C) timing Table 42. I 2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.3 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Data hold time for I2C bus devices tHD; DAT 01 3.452 03 0.91 s Data set-up time tSU; DAT 2504 -- 1002, 5 -- ns Rise time of SDA and SCL signals tr -- 1000 20 +0.1Cb6 300 ns Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 53 Peripheral operating requirements and behaviors Table 42. I 2C timing (continued) Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit ns Fall time of SDA and SCL signals tf -- 300 20 +0.1Cb5 300 Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Input signal Slew = 10ns and Output Load = 50pf 4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 6. Cb = total capacitance of the one bus line in pF. SDA tf tLOW tSU; DAT tr tf tHD; STA tr tSP tBUF SCL S tHD; STA tHD; DAT tHIGH tSU; STA SR tSU; STO P S Figure 21. Timing definition for fast and standard mode devices on the I2C bus 6.8.8 UART switching specifications See General switching specifications. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 54 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.8.9 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 43. SDHC switching specifications Num Symbol Description Min. Max. Unit Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz fOD Clock frequency (identification mode) 0 400 kHz SD2 tWL Clock low time 7 -- ns SD3 tWH Clock high time 7 -- ns SD4 tTLH Clock rise time -- 3 ns SD5 tTHL Clock fall time -- 3 ns SD6 tOD SDHC output delay (output valid) SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) -5 8.3 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 -- ns SD8 tIH SDHC input hold time 0 -- ns SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 22. SDHC timing K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 55 Peripheral operating requirements and behaviors 6.8.10 I2S switching specifications This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync (I2S_FS) shown in the figures below. Table 44. I2S master mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V 45% 55% MCLK period 5 x tSYS -- ns 45% 55% BCLK period -- 15 ns -2.5 -- ns S1 I2S_MCLK cycle time S2 I2S_MCLK pulse width high/low 2 x tSYS S3 I2S_BCLK cycle time S4 I2S_BCLK pulse width high/low S5 I2S_BCLK to I2S_FS output valid S6 I2S_BCLK to I2S_FS output invalid S7 I2S_BCLK to I2S_TXD valid -- 15 ns S8 I2S_BCLK to I2S_TXD invalid -3 -- ns S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 20 -- ns S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 -- ns S1 S2 ns S2 I2S_MCLK (output) S3 I2S_BCLK (output) S4 S4 S6 S5 I2S_FS (output) S10 S9 I2S_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 23. I2S timing -- master mode K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 56 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 45. I2S slave mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V 8 x tSYS -- ns S11 I2S_BCLK cycle time (input) S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 10 -- ns S14 I2S_FS input hold after I2S_BCLK 3 -- ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid -- 20 ns S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_BCLK 10 -- ns S18 I2S_RXD hold after I2S_BCLK 2 -- ns S11 S12 I2S_BCLK (input) S12 S15 S16 I2S_FS (output) S13 S14 I2S_FS (input) S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 24. I2S timing -- slave modes Table 46. I2S master mode timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time S2 I2S_MCLK pulse width high/low S3 I2S_BCLK cycle time S4 I2S_BCLK pulse width high/low S5 I2S_BCLK to I2S_FS output valid S6 I2S_BCLK to I2S_FS output invalid S7 I2S_BCLK to I2S_TXD valid S8 2 x tSYS 45% ns 55% MCLK period 5 x tSYS -- ns 45% 55% BCLK period -- 15 ns -4.3 -- ns -- 15 ns I2S_BCLK to I2S_TXD invalid -4.6 -- ns S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 23.9 -- ns S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 -- ns K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 57 Peripheral operating requirements and behaviors Table 47. I2S slave mode timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V 8 x tSYS -- ns S11 I2S_BCLK cycle time (input) S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 10 -- ns S14 I2S_FS input hold after I2S_BCLK 3.5 -- ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid -- 28.6 ns S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_BCLK 10 -- ns S18 I2S_RXD hold after I2S_BCLK 2 -- ns 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 48. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 -- 3.6 V Target electrode capacitance range 1 20 500 pF 1 fREFmax Reference oscillator frequency -- 5.5 12.7 MHz 2 fELEmax Electrode oscillator frequency -- 0.5 4.0 MHz 3 Internal reference capacitor 0.5 1 1.2 pF Oscillator delta voltage 100 600 760 mV 4 -- 1.133 1.5 A 3,5 -- 36 50 -- 1.133 1.5 A 3,6 -- 36 50 CELE CREF VDELTA IREF IELE Reference oscillator current source base current * 1uA setting (REFCHRG=0) * 32uA setting (REFCHRG=31) Electrode oscillator current source base current * 1uA setting (EXTCHRG=0) * 32uA setting (EXTCHRG=31) Notes Pres5 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 7 Pres20 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 8 Pres100 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 9 0.003 12.5 -- fF/count 10 Resolution -- -- 16 bits Response time @ 20 pF 8 15 25 s Current added in run mode -- 55 -- A Low power mode current adder -- 1.3 2.5 A MaxSens Maximum sensitivity Res TCon20 ITSI_RUN ITSI_LP 11 12 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 58 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF. 4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF. 5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 6. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 7. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 10. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref * Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following configuration: Iext = 5 A, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 A, REFCHRG = 15, Cref = 1.0 pF. The minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity but is described as a minimum because it's the smallest number). The minimum sensitivity parameter is based on the following configuration: Iext = 1 A, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 A, REFCHRG = 31, Cref= 0.5 pF 11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, DELVOL = 2, EXTCHRG = 15. 12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. 6.9.2 LCD electrical characteristics Table 49. LCD electricals Symbol Description Min. Typ. Max. Unit Notes fFrame LCD frame frequency 28 30 58 Hz CLCD LCD charge pump capacitance -- nominal value -- 100 -- nF 1 CBYLCD LCD bypass capacitance -- nominal value -- 100 -- nF 1 CGlass LCD glass capacitance -- 2000 8000 pF 2 VIREG VIREG 3 * HREFSEL=0, RVTRIM=1111 -- 1.11 -- V * HREFSEL=0, RVTRIM=1000 -- 1.01 -- V * HREFSEL=0, RVTRIM=0000 -- 0.91 -- V -- 1.84 -- V -- 1.69 -- V -- 1.54 -- V -- -- 3.0 % VIREG * HREFSEL = 0 -- -- 30 mV * HREFSEL = 1 -- -- 50 mV -- 1 -- A -- 10 -- A -- 1 -- A * HREFSEL=1, RVTRIM=1111 * HREFSEL=1, RVTRIM=1000 * HREFSEL=1, RVTRIM=0000 RTRIM -- VIREG TRIM resolution VIREG ripple IVIREG VIREG current adder -- RVEN = 1 IRBIAS RBIAS current adder * LADJ = 10 or 11 -- High load (LCD glass capacitance 8000 pF) 4 * LADJ = 00 or 01 -- Low load (LCD glass capacitance 2000 pF) Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 59 Dimensions Table 49. LCD electricals (continued) Symbol Description Min. Typ. Max. Unit RRBIAS RBIAS resistor values -- 0.28 -- M -- 2.98 -- M * HREFSEL = 0 2.0 - 5% 2.0 -- V * HREFSEL = 1 3.3 - 5% 3.3 -- V * HREFSEL = 0 3.0 - 5% 3.0 -- V * HREFSEL = 1 5 - 5% 5 -- V * LADJ = 10 or 11 -- High load (LCD glass capacitance 8000 pF) * LADJ = 00 or 01 -- Low load (LCD glass capacitance 2000 pF) VLL2 VLL3 Notes VLL2 voltage VLL3 voltage 1. The actual value used could vary with tolerance. 2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter within the device's reference manual. 3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V 4. 2000 pF load LCD, 32 Hz frame frequency 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing's document number: If you want the drawing for this package 100-pin LQFP Then use this document number 98ASS23308W 8 Pinout K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 60 Freescale Semiconductor, Inc. Pinout 8.1 K40 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 100 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 1 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA 2 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL 3 PTE2/ LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_b SDHC0_DCLK 4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD 5 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 6 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 7 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_b I2S0_MCLK 8 VDD VDD VDD 9 VSS VSS VSS 10 USB0_DP USB0_DP USB0_DP 11 USB0_DM USB0_DM USB0_DM 12 VOUT33 VOUT33 VOUT33 13 VREGIN VREGIN VREGIN 14 ADC0_DP1 ADC0_DP1 ADC0_DP1 15 ADC0_DM1 ADC0_DM1 ADC0_DM1 16 ADC1_DP1 ADC1_DP1 ADC1_DP1 17 ADC1_DM1 ADC1_DM1 ADC1_DM1 18 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 19 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 20 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 21 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 22 VDDA VDDA VDDA 23 VREFH VREFH VREFH 24 VREFL VREFL VREFL 25 VSSA VSSA VSSA 26 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 ALT7 EzPort I2S0_CLKIN K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 61 Pinout 100 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 27 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 28 XTAL32 XTAL32 XTAL32 29 EXTAL32 EXTAL32 EXTAL32 30 VBAT VBAT VBAT 31 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b 32 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN 33 PTE26 DISABLED UART4_CTS_b RTC_CLKOUT 34 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK 35 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI 36 PTA2 JTAG_TDO/ TRACE_SWO/ EZP_DO TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO 37 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 38 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 FTM0_CH1 39 PTA5 DISABLED PTA5 FTM0_CH2 40 VDD VDD VDD 41 VSS VSS VSS 42 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_ PHA 43 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_ PHB 44 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_TX_BCLK 45 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD 46 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_b I2S0_RX_FS 47 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_b I2S0_MCLK 48 VDD VDD VDD 49 VSS VSS VSS 50 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0 51 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN1 52 RESET_b RESET_b RESET_b 53 PTB0/ LLWU_P5 LCD_P0/ ADC0_SE8/ ADC1_SE8/ TSI0_CH0 LCD_P0/ ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA LCD_P0 54 PTB1 LCD_P1/ ADC0_SE9/ ADC1_SE9/ TSI0_CH6 LCD_P1/ ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_ PHB LCD_P1 PTE26 ALT4 ALT5 ALT6 ALT7 EzPort USB_CLKIN JTAG_TMS/ SWD_DIO NMI_b CMP2_OUT EZP_CS_b I2S0_RX_BCLK JTAG_TRST I2S0_CLKIN LPT0_ALT1 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 62 Freescale Semiconductor, Inc. Pinout 100 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 55 PTB2 LCD_P2/ ADC0_SE12/ TSI0_CH7 LCD_P2/ ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_b FTM0_FLT3 LCD_P2 56 PTB3 LCD_P3/ ADC0_SE13/ TSI0_CH8 LCD_P3/ ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_b FTM0_FLT0 LCD_P3 57 PTB7 LCD_P7/ ADC1_SE13 LCD_P7/ ADC1_SE13 PTB7 58 PTB8 LCD_P8 LCD_P8 PTB8 UART3_RTS_b LCD_P8 59 PTB9 LCD_P9 LCD_P9 PTB9 SPI1_PCS1 UART3_CTS_b LCD_P9 60 PTB10 LCD_P10/ ADC1_SE14 LCD_P10/ ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FTM0_FLT1 LCD_P10 61 PTB11 LCD_P11/ ADC1_SE15 LCD_P11/ ADC1_SE15 PTB11 SPI1_SCK UART3_TX FTM0_FLT2 LCD_P11 62 PTB16 LCD_P12/ TSI0_CH9 LCD_P12/ TSI0_CH9 PTB16 SPI1_SOUT UART0_RX EWM_IN LCD_P12 63 PTB17 LCD_P13/ TSI0_CH10 LCD_P13/ TSI0_CH10 PTB17 SPI1_SIN UART0_TX EWM_OUT_b LCD_P13 64 PTB18 LCD_P14/ TSI0_CH11 LCD_P14/ TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_BCLK FTM2_QD_ PHA LCD_P14 65 PTB19 LCD_P15/ TSI0_CH12 LCD_P15/ TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FTM2_QD_ PHB LCD_P15 66 PTB20 LCD_P16 LCD_P16 PTB20 SPI2_PCS0 CMP0_OUT LCD_P16 67 PTB21 LCD_P17 LCD_P17 PTB21 SPI2_SCK CMP1_OUT LCD_P17 68 PTB22 LCD_P18 LCD_P18 PTB22 SPI2_SOUT CMP2_OUT LCD_P18 69 PTB23 LCD_P19 LCD_P19 PTB23 SPI2_SIN SPI0_PCS5 70 PTC0 LCD_P20/ ADC0_SE14/ TSI0_CH13 LCD_P20/ ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4 PDB0_EXTRG 71 PTC1/ LLWU_P6 LCD_P21/ ADC0_SE15/ TSI0_CH14 LCD_P21/ ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_b FTM0_CH0 LCD_P21 72 PTC2 LCD_P22/ ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 LCD_P22/ ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_b FTM0_CH1 LCD_P22 73 PTC3/ LLWU_P7 LCD_P23/ CMP1_IN1 LCD_P23/ CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 LCD_P23 74 VSS VSS VSS 75 VLL3 VLL3 VLL3 76 VLL2 VLL2 VLL2 77 VLL1 VLL1 VLL1 78 VCAP2 VCAP2 VCAP2 79 VCAP1 VCAP1 VCAP1 80 PTC4/ LLWU_P8 LCD_P24 LCD_P24 PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 EzPort LCD_P7 LCD_P19 I2S0_TXD LCD_P20 CMP1_OUT LCD_P24 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 63 Pinout 100 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 LPT0_ALT2 ALT5 ALT6 CMP0_OUT ALT7 81 PTC5/ LLWU_P9 LCD_P25 LCD_P25 PTC5/ LLWU_P9 SPI0_SCK 82 PTC6/ LLWU_P10 LCD_P26/ CMP0_IN0 LCD_P26/ CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT 83 PTC7 LCD_P27/ CMP0_IN1 LCD_P27/ CMP0_IN1 PTC7 SPI0_SIN 84 PTC8 LCD_P28/ ADC1_SE4b/ CMP0_IN2 LCD_P28/ ADC1_SE4b/ CMP0_IN2 PTC8 85 PTC9 LCD_P29/ ADC1_SE5b/ CMP0_IN3 LCD_P29/ ADC1_SE5b/ CMP0_IN3 PTC9 86 PTC10 LCD_P30/ ADC1_SE6b/ CMP0_IN4 LCD_P30/ ADC1_SE6b/ CMP0_IN4 PTC10 I2C1_SCL I2S0_RX_FS LCD_P30 87 PTC11/ LLWU_P11 LCD_P31/ ADC1_SE7b LCD_P31/ ADC1_SE7b PTC11/ LLWU_P11 I2C1_SDA I2S0_RXD LCD_P31 88 VSS VSS VSS 89 VDD VDD VDD 90 PTC16 LCD_P36 LCD_P36 PTC16 CAN1_RX UART3_RX LCD_P36 91 PTC17 LCD_P37 LCD_P37 PTC17 CAN1_TX UART3_TX LCD_P37 92 PTC18 LCD_P38 LCD_P38 PTC18 UART3_RTS_b LCD_P38 93 PTD0/ LLWU_P12 LCD_P40 LCD_P40 PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_b LCD_P40 94 PTD1 LCD_P41/ ADC0_SE5b LCD_P41/ ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_b LCD_P41 95 PTD2/ LLWU_P13 LCD_P42 LCD_P42 PTD2/ LLWU_P13 SPI0_SOUT UART2_RX LCD_P42 96 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_SIN UART2_TX LCD_P43 97 PTD4/ LLWU_P14 LCD_P44 LCD_P44 PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_b FTM0_CH4 EWM_IN LCD_P44 98 PTD5 LCD_P45/ ADC0_SE6b LCD_P45/ ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_b FTM0_CH5 EWM_OUT_b LCD_P45 99 PTD6/ LLWU_P15 LCD_P46/ ADC0_SE7b LCD_P46/ ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0 LCD_P46 100 PTD7 LCD_P47 LCD_P47 PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 LCD_P47 PDB0_EXTRG EzPort LCD_P25 LCD_P26 LCD_P27 I2S0_MCLK I2S0_CLKIN I2S0_RX_BCLK LCD_P28 FTM2_FLT0 LCD_P29 8.2 K40 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 64 Freescale Semiconductor, Inc. PTC18 PTC17 PTC16 VDD VSS PTC11 PTC10 PTC9 PTC8 PTC7 PTC6 PTC5 PTC4 92 91 90 89 88 87 86 85 84 83 82 81 80 VLL2 PTD0 93 VLL1 PTD1 94 76 PTD2 95 77 PTD3 96 VCAP1 PTD4 97 VCAP2 PTD5 98 78 PTD6 99 79 PTD7 100 Revision History PTE0 1 75 VLL3 PTE1 2 74 VSS PTE2 3 73 PTC3 PTE3 4 72 PTC2 PTE4 5 71 PTC1 PTE5 6 70 PTC0 PTE6 7 69 PTB23 VDD 8 68 PTB22 VSS 9 67 PTB21 PTB20 USB0_DP 10 66 USB0_DM 11 65 PTB19 VOUT33 12 64 PTB18 VREGIN 13 63 PTB17 ADC0_DP1 14 62 PTB16 ADC0_DM1 15 61 PTB11 PTB10 ADC1_DP1 16 60 ADC1_DM1 17 59 PTB9 PGA0_DP/ADC0_DP0/ADC1_DP3 18 58 PTB8 PGA0_DM/ADC0_DM0/ADC1_DM3 19 57 PTB7 PGA1_DP/ADC1_DP0/ADC0_DP3 20 56 PTB3 PGA1_DM/ADC1_DM0/ADC0_DM3 21 55 PTB2 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PTE26 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 VDD VSS PTA12 PTA13 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 VREF_OUT/CMP1_IN5/ CMP0_IN5/ADC1_SE18 31 PTA19 PTE25 51 PTE24 25 VBAT VSSA 30 RESET_b 29 52 EXTAL32 24 28 PTB0 VREFL 27 PTB1 53 XTAL32 54 DAC0_OUT/CMP1_IN3/ADC0_SE23 22 23 26 VDDA VREFH Figure 25. K40 100 LQFP Pinout Diagram 9 Revision History The following table provides a revision history for this document. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 65 Revision History Table 50. Revision History Rev. No. Date Substantial Changes 1 11/2010 Initial public revision 2 3/2011 Many updates throughout 3 3/2011 Added sections that were inadvertently removed in previous revision 4 3/2011 Reworded IIC footnote in "Voltage and Current Operating Requirements" table. Added paragraph to "Peripheral operating requirements and behaviors" section. Added "JTAG full voltage range electricals" table to the "JTAG electricals" section. 5 6/2011 * Changed supported part numbers per new part number scheme * Changed DC injection current specs in "Voltage and current operating requirements" table * Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage and current operating behaviors" table * Split Low power stop mode current specs by temperature range in "Power consumption operating behaviors" table * Changed typical IDD_VBAT spec in "Power consumption operating behaviors" table * Added LPTMR clock specs to "Device clock specifications" table * Changed Minimum external reset pulse width in "General switching specifications" table * Changed PLL operating current in "MCG specifications" table * Added footnote to PLL period jitter in "MCG specifications" table * Changed Supply current in "Oscillator DC electrical specifications" table * Changed Crystal startup time in "Oscillator frequency specifications" table * Changed Operating voltage in "EzPort switching specifications" table * Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table * Changed Gain spec in "16-bit ADC with PGA characteristics" table * Added typical Input DC current to "16-bit ADC with PGA characteristics" table * Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA characteristics" table * Changed Analog comparator initialization delay in "Comparator and 6-bit DAC electrical specifications" * Changed Code-to-code settling time, DAC output voltage range low, and Temperature coefficient offset voltage in "12-bit DAC operating behaviors" table * Changed Temperature drift and Load regulation in "VREF full-range operating behaviors" table * Changed Regulator output voltage in "USB VREG electrical specifications" table * Changed ILIM description and specs in "USB VREG electrical specifications" table * Changed DSPI_SCK cycle time specs in "DSPI timing" tables * Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table * Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (highspeed mode)" table * Changed Reference oscillator current source base current spec and added Low-power current adder footer in "TSI electrical specifications" table * Added LCD glass capacitance footnote Table continues on the next page... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 66 Freescale Semiconductor, Inc. Revision History Table 50. Revision History (continued) Rev. No. Date 6 01/2012 Substantial Changes * * * * * * * * * * * 7 02/2013 Added AC electrical specifications. Replaced TBDs with silicon data throughout. In "Power mode transition operating behaviors" table, removed entry times. Updated "EMC radiated emissions operating behaviors" to remove SAE level and also added data for 144LQFP. Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram". Added "ENOB vs. ADC_CLK for 16-bit differential and 16-bit single-ended modes" figures. Updated IDD_RUN numbers in 'Power consumption operating behaviors' section. Clarified 'Diagram: Typical IDD_RUN operating behavior' section and updated 'Run mode supply current vs. core frequency -- all peripheral clocks disabled' figure. In 'Voltage reference electrical specifications' section, updated CL, Vtdrift, and Vvdrift values. In 'USB electrical specifications' section, updated VDP_SRC, IDDstby, and 'VReg33out values. In 'LCD electrical characteristics' section, updated VIREG and RTRIM values. * * * * * * * * In "ESD handling ratings", added a note for ILAT. Updated "Voltage and current operating requirements". Updated "Voltage and current operating behaviors". Updated "Power mode transition operating behaviors". Updated "EMC radiated emissions operating behaviors" to add MAPBGA data. In "MCG specifications", updated the description of fints_t. In "16-bit ADC operating conditions", updated the max spec of VADIN. In "16-bit ADC electrical characteristics", updated the temp sensor slope and voltage specs. * Updated "I2C switching specifications". * In "SDHC specifications", removed the operating voltage limits and updated the SD1 and SD6 specs. * In "I2S switching specifications", added separate specification tables for the full operating voltage range. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 67 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Document Number: K40P100M100SF2 Rev. 7, 02/2013 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) 2011-2013 Freescale Semiconductor, Inc.